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UC1854, UC2854, UC3854
SLUS336A – JUNE 1998 – REVISED DECEMBER 2016
UCx854 High-Power Factor Preregulator
1 Features
•
•
•
•
•
•
•
•
•
•
•
1
In addition, the UC1854 contains a power MOSFETcompatible gate driver, 7.5-V reference, line
anticipator, load-enable comparator, low-supply
detector, and overcurrent comparator.
Control Boost PWM to 0.99 Power Factor
Limit Line-Current Distortion to < 5%
World-Wide Operation Without Switches
Feedforward Line Regulation
Average Current-Mode Control
Low Noise Sensitivity
Low Startup Supply Current
Fixed-Frequency PWM Drive
Low-Offset Analog Multiplier and Divider
1-A Totem-Pole Gate Driver
Precision Voltage Reference
The UC1854 uses average current-mode control to
accomplish fixed-frequency current control with
stability and low distortion. Unlike peak current-mode,
average current control accurately maintains
sinusoidal line current without slope compensation
and with minimal response to noise transients.
The high reference voltage and high oscillator
amplitude of the UC1854 minimize noise sensitivity
while fast PWM elements permit chopping
frequencies above 200 kHz. The UC1854 is used in
single-phase and three-phase systems with line
voltages that vary from 75 V to 275 V and line
frequencies across the 50-Hz to 400-Hz range. To
reduce the burden on the circuitry that supplies power
to this device, the UC1854 features low starting
supply current.
2 Applications
•
•
•
•
Offline AC-to-DC Converters
Medical, Industrial, Telecom, and IT Power
Supplies
Uninterruptible Power Supplies (UPS)
Appliances and White Goods
These devices are available packaged in 16-pin
plastic and ceramic dual in-line packages, and a
variety of surface-mount packages.
3 Description
Device Information(1)
The UC1854 provides active-power factor correction
for power systems that otherwise would draw nonsinusoidal current from sinusoidal power lines. This
device implements all the control functions necessary
to build a power supply capable of optimally using
available power-line current while minimizing linecurrent distortion. To do this, the UC1854 contains a
voltage amplifier, an analog multiplier and divider, a
current amplifier, and a fixed-frequency PWM.
PART NUMBER
PACKAGE
UC1854, UC2854,
UC3854
BODY SIZE (NOM)
SOIC (16)
7.50 mm × 10.30 mm
PLCC (20)
8.96 mm × 8.96 mm
CDIP (16)
6.92 mm × 19.56 mm
PDIP (16)
6.35 mm × 19.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
Line
Input
EMI
Filter
–
VOUT
400 VDC
+
VREF
VCC
5
10
2
ENA
PKLMT
4
3
16
CAOUT
GTDRV
VREF
MULTOUT ISENSE
VSENSE
6
IAC
8
VRMS
11
UC3854
VCC
VAOUT
VCC
CT
SS
RSET
GND
VREF
15
14
13
12
1
9
7
VREF
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UC1854, UC2854, UC3854
SLUS336A – JUNE 1998 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
6
6
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 1998) to Revision A
Page
•
Added Applications section, Device Information table, Pin Configuration and Functions section, Specifications
section, ESD Ratings table, Recommended Operating Conditions table, Detailed Description section, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Added Thermal Information table ........................................................................................................................................... 6
•
Changed IAC value in both Multiplier Output vs Multiplier Inputs images from mA to µA. ................................................... 8
2
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Copyright © 1998–2016, Texas Instruments Incorporated
Product Folder Links: UC1854 UC2854 UC3854
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SLUS336A – JUNE 1998 – REVISED DECEMBER 2016
5 Device Comparison Table
UC3854
UC3854A
UC3854B
Supply current, OFF
PARAMETER
2-mA maximum
400-µA maximum
400-µA maximum
Supply voltage (VCC)
35-V maximum
22-V maximum
22-V maximum
VCC turn-on threshold
16-V typical
16-V typical
10.5-V typical
VCC UVLO hysteresis
6-V typical
6-V typical
0.5-V typical
1-MHz typical
5-MHz typical
5-MHz typical
4-mV, –4-mV maximum
0-mV, –4-mV maximum
0-mV, –4-mV maximum
Current amplifier bandwidth
Current amplifier offset
MULTOUT voltage (high)
2.5-V typical
5-V typical
5-V typical
Multiplier gain tolerance
Not specified
–0.9 to –1.1
–0.9 to –1.1
ENABLE propagation delay
Not specified
300-ns typical
300-ns typical
VSENSE input
7.5 V
3V
3V
6-V typical
0.5-V typical
0.5-V typical
Voltage amplifier clamp
—
Internal
Internal
Current amplifier clamp
—
Internal
Internal
VREF good circuitry
—
Internal
Internal
IAC voltage
6 Pin Configuration and Functions
DW, J, and N Packages
16-Pin SOIC, CDIP, and PDIP
Top View
VCC
19
NC
1
GTDRV
GND
2
20
PKLMT
3
FN Package
20-Pin PLCC
Top View
PKLMT
2
15
VCC
CAOUT
3
14
CT
ISENSE
4
13
SS
CAOUT
4
18
CT
MULTOUT
5
12
RSET
ISENSE
5
17
SS
IAC
6
11
VSENSE
NC
6
16
NC
VAOUT
7
10
ENA
MULTOUT
7
15
RSET
VRMS
8
9
IAC
8
14
VSENSE
9
VREF
13
GTDRV
12
16
11
1
10
GND
Copyright © 1998–2016, Texas Instruments Incorporated
Product Folder Links: UC1854 UC2854 UC3854
ENA
VREF
NC
VRMS
VAOUT
Not to scale
Not to scale
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SLUS336A – JUNE 1998 – REVISED DECEMBER 2016
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Pin Functions
PIN
CDIP,
PDIP,
SOIC
NAME
CAOUT
3
PLCC
4
I/O
DESCRIPTION
O
Current amplifier output. This is the output of a wide-bandwidth operational amplifier that senses line
current and commands the pulse-width modulator (PWM) to force the correct current. This output
swings close to GND, allowing the PWM to force zero duty cycle when necessary. The current
amplifier remains active even if the IC is disabled. The current-amplifier output stage is an NPN
emitter-follower pullup and an 8-kΩ resistor to ground.
Oscillator timing capacitor. A capacitor from CT to GND sets the PWM oscillator frequency.
Use Equation 1:
CT
14
18
I
F=
1.25
RSET ´ CT
(1)
ENA
10
13
I
Enable. ENA is a logic input that enables the PWM output, voltage reference, and oscillator. ENA
also releases the soft-start clamp, allowing SS to rise. When not in use, connect ENA to a 5-V supply
or pull ENA high with a 22-kΩ resistor. The ENA pin is not intended to be used as a high speed
shutdown to the PWM output.
GND
1
2
—
Ground. All voltages are measured with respect to GND. VCC and VREF must be bypassed directly
to GND with an 0.1-µF or larger ceramic capacitor. The timing capacitor discharge current also
returns to this pin, so the lead from the oscillator timing capacitor to GND must also be as short and
as direct as possible.
O
Gate drive. The output of the PWM is a totem-pole MOSFET gate driver on GTDRV. This output is
internally clamped to 15 V so that the IC operates with VCC as high as 35 V. Use a series gate
resistor of at least 5 Ω to prevent interaction between the gate impedance and the GTDRV output
driver that might cause the GTDRV output to overshoot excessively. Some overshoot of the GTDRV
output is always expected when driving a capacitive load.
GTDRV
16
20
IAC
6
8
I
Input AC current. This input to the analog multiplier is a current. The multiplier is tailored for very low
distortion from this current input (IAC) to MULTOUT, this is the only multiplier input that must be used
for sensing instantaneous line voltage. The nominal voltage on IAC is 6 V, in addition to a resistor
from IAC to rectified 60 Hz, connect a resistor from IAC to REF. If the resistor to VREF is one-fourth
of the value of the resistor to the rectifier, then the 6-V offset is cancelled, and the line current has
minimal cross-over distortion.
ISENSE
4
5
I
Current-sense minus. This is the inverting input to the current amplifier. This input and the noninverting input, MULTOUT, remain functional down to and below GND. Take care to avoid taking
these inputs below –0.5 V because they are protected with diodes to GND.
MULTOUT
5
7
I/O
Multiplier output and current-sense plus. The output of the analog multiplier and the non-inverting
input of the current amplifier are connected together at MULTOUT. The cautions about taking
ISENSE below –0.5 V also apply to MULTOUT. As the multiplier output is a current, this is a highimpedance input similar to ISENSE, so the current amplifier can be configured as a differential
amplifier to reject GND noise. Figure 9 shows an example of using the current amplifier differentially.
NC
—
1, 6,
11, 16
—
No connection
PKLMT
2
3
I
Peak current limit. The threshold for PKLMT is 0 V. Connect this input to the negative voltage on the
current-sense resistor as shown in Figure 9. Use a resistor to VREF to offset the negative currentsense signal up to GND.
RSET
12
15
I
Oscillator charging current and multiplier limit set. A resistor from RSET to GND programs oscillator
charging current and maximum multiplier output. Multiplier output current does not exceed 3.75 V
divided by the resistor from RSET to GND.
I
Soft start. SS remains at GND as long as the device is disabled or VCC is too low. SS pulls up to
over 8 V by an internal 14-mA current source when both VCC becomes valid and the IC is enabled.
SS acts as the reference input to the voltage amplifier if SS is below VREF. With a large capacitor
from SS to GND, the reference to the voltage regulating amplifier rises slowly, and increases the
PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS quickly
discharges to ground and disables the PWM.
O
Voltage amplifier output. This is the output of the operational amplifier that regulates output voltage.
Like the current amplifier, the voltage amplifier remains active even if the IC is disabled with either
ENA or VCC. This means that large feedback capacitors across the amplifier stay charged through
momentary disable cycles. Voltage amplifier output levels below 1 V inhibit multiplier output. The
voltage amplifier output is internally limited to approximately 5.8 V to prevent overshoot. The voltage
amplifier output stage is an NPN emitter-follower pullup and an 8-kΩ resistor to ground.
SS
13
VAOUT
4
7
17
9
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UC1854, UC2854, UC3854
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SLUS336A – JUNE 1998 – REVISED DECEMBER 2016
Pin Functions (continued)
PIN
CDIP,
PDIP,
SOIC
NAME
PLCC
I/O
DESCRIPTION
VCC
15
19
—
Positive supply voltage. Connect VCC to a stable source of at least 20 mA above 17 V for normal
operation. Also bypass VCC directly to GND to absorb supply current spikes required to charge
external MOSFET gate capacitances. To prevent inadequate GTDRV signals, these devices are
inhibited unless VCC exceeds the upper undervoltage-lockout threshold and remains above the lower
threshold.
VREF
9
12
O
Voltage reference output. VREF is the output of an accurate 7.5-V voltage reference. This output is
capable of delivering 10 mA to peripheral circuitry and is internally short-circuit current limited. VREF
is disabled and remains at 0 V when VCC is low or when ENA is low. Bypass VREF to GND with an
0.1-µF or larger ceramic capacitor for best stability.
VRMS
8
10
I
RMS line voltage. The output of a boost PWM is proportional to the input voltage, so when the line
voltage into a low-bandwidth boost PWM-voltage regulator changes, the output changes immediately
and slowly recovers to the regulated level. For these devices, the VRMS input compensates for line
voltage changes if it is connected to a voltage proportional to the RMS input line voltage. For best
control, the VRMS voltage must stay between 1.5 V and 3.5 V.
VSENSE
11
14
I
Voltage amplifier inverting input. This is normally connected to a feedback network and to the boost
converter output through a divider network.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3) (4) (5)
MIN
Supply voltage
Input Voltage
Gate driver current Input current
Input current
MAX
UNIT
VCC
35
V
VSENSE, VRMS
11
ISENSE, MULTOUT
11
PKLMT
5
50% duty cycle
1.5
Continuous
0.5
RSET, IAC, PKLMT, ENA
10
Power dissipation
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
V
A
mA
1
W
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages with respect to GND.
All currents are positive into the specified terminal.
ENA input is internally clamped to approximately 14 V.
Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 1998–2016, Texas Instruments Incorporated
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Supply voltage
TJ
Operating junction temperature
MAX
10
20
UC1854
–55
125
UC2854
–40
85
UC3854
0
70
UNIT
°C
7.4 Thermal Information
UCx854
THERMAL METRIC (1)
DW (SOIC)
FN (PLCC)
J (CDIP)
N (PDIP)
UNIT
16 PINS
20 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
71.5
—
25
40.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.7
—
—
26.8
°C/W
RθJB
Junction-to-board thermal resistance
36.3
—
5.5
20.9
°C/W
ψJT
Junction-to-top characterization parameter
6.8
—
2.1
10.9
°C/W
ψJB
Junction-to-board characterization
parameter
35.8
—
5.4
20.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
3.4
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metricsapplication
report.
7.5 Electrical Characteristics
Unless otherwise stated, VCC = 18 V, RSET = 15 kΩ to ground, CT = 1.5 nF to ground, VPKLMT = 1 V, VENA = 7.5 V,
VRMS = 1.5 V, IAC = 100 µA, VISENSE = 0 V, VCAOUT = 3.5 V, VVAOUT = 5 V, VSENSE = 7.5 V, no load on SS, CAOUT, VAOUT,
VREF, GTDRV, TA = TJ, TA = –55°C to 125°C for the UC1854, TA = –40°C to 85°C for the UC2854,
and TA = 0°C to 70°C for the UC3854.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL
Supply current, OFF
VENA = 0 V
Supply current, ON
VCC turn-on threshold
14.5
1.5
2
mA
10
16
mA
16
17.5
V
VCC turn-off threshold
9
10
11
V
ENA threshold, rising
2.4
2.55
2.7
V
ENA threshold hysteresis
0.2
0.25
0.3
V
ENA input current
VENA = 0 V
–5
–0.2
5
µA
VRMS input current
VRMS = 5 V
–1
–0.01
1
µA
VVAOUT = 5 V
–8
8
mV
500
nA
VOLTAGE AMPLIFIER
Voltage amplifier offset voltage
VSENSE bias current
–500
–25
Voltage amplifier gain
70
100
Voltage amplifier output swing
0.5
dB
5.8
V
Voltage amplifier short circuit current
VVAOUT = 0 V
–36
–20
–5
mA
SS current
VSS = 2.5 V
–20
–14
–6
µA
4
mV
–120
500
nA
CURRENT AMPLIFIER
Current amplifier offset voltage
–4
ISENSE bias current
–500
Input range (ISENSE, MULTOUT)
–0.3
Current amplifier gain
6
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80
2.5
110
V
dB
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SLUS336A – JUNE 1998 – REVISED DECEMBER 2016
Electrical Characteristics (continued)
Unless otherwise stated, VCC = 18 V, RSET = 15 kΩ to ground, CT = 1.5 nF to ground, VPKLMT = 1 V, VENA = 7.5 V,
VRMS = 1.5 V, IAC = 100 µA, VISENSE = 0 V, VCAOUT = 3.5 V, VVAOUT = 5 V, VSENSE = 7.5 V, no load on SS, CAOUT, VAOUT,
VREF, GTDRV, TA = TJ, TA = –55°C to 125°C for the UC1854, TA = –40°C to 85°C for the UC2854,
and TA = 0°C to 70°C for the UC3854.
PARAMETER
TEST CONDITIONS
Current amplifier output swing
MIN
TYP
0.5
MAX
UNIT
16
V
–5
mA
Current amplifier short-circuit current
VCAOUT = 0 V
–36
–20
Current amplifier gain–bandwidth
product
TA = 25°C (1)
400
800
Reference output voltage
IREF = 0 mA, TA = 25°C
7.4
7.5
7.6
Reference output voltage
IREF = 0 mA, over temperature
7.35
7.5
7.65
VREF load regulation
–10 mA < IREF < 0 mA
–15
5
15
mV
VREF line regulation
15 V < VCC < 35 V
–10
2
10
mV
VREF short circuit current
VREF = 0 V
–50
–28
–12
mA
–220
–200
–180
µA
–2
–0.2
–2
µA
–280
–255
–220
µA
–50
–42
–33
µA
kHz
REFERENCE
V
V
MULTIPLIER
Multiplier out current IAC limited
IAC = 100 µA, RSET = 10 kΩ, VRMS = 1.25 V
Multiplier out current zero
IAC = 0 µA, RSET = 15 kΩ
Multiplier out current RSET limited
IAC = 450 µA, RSET = 15 kΩ, VRMS = 1 V,
VVAOUT = 6 V
Multiplier out current
IAC = 50 µA, VRMS = 2 V, VVAOUT = 4 V
Multiplier out current
IAC = 100 µA, VRMS = 2 V, VVAOUT = 2 V
–38
–27
–12
µA
Multiplier out current
IAC = 200 µA, VRMS = 2 V, VVAOUT = 4 V
–165
–150
–105
µA
Multiplier out current
IAC = 300 µA, VRMS = 1 V, VVAOUT = 2 V
–250
–225
–150
µA
Multiplier out current
IAC = 100 µA, VRMS = 1 V, VVAOUT = 2 V
–95
–80
–60
µA
Multiplier gain constant
See
(2)
–1
V
OSCILLATOR
Oscillator frequency
RSET = 15 kΩ
Oscillator frequency
RSET = 8.2 kΩ
46
55
62
kHz
86
102
118
kHz
CT ramp peak-to-valley amplitude
4.9
5.4
5.9
V
CT ramp valley voltage
0.8
1.1
1.3
V
18
V
GATE DRIVER (GTDRV)
Maximum gate driver output voltage
0-mA load on gate driver, 18 V < VCC < 35 V
13
14.5
Gate driver output voltage high
–200-mA load on gate driver, VCC = 15 V
12
12.8
Gate driver output voltage low, OFF
VCC = 0 V, 50-mA load on gate driver
Gate driver output voltage low
200-mA load on gate driver
Gate driver output voltage low
10-mA load on gate driver
Peak Gate driver current
10 nF from gate driver to GND
Gate driver rise and fall time
1 nF from gate driver to GND
Gate driver maximum duty cycle
VCAOUT = 7 V
V
0.9
1.5
V
1
2.2
V
0.1
0.4
V
1
A
35
ns
95%
CURRENT LIMIT
PKLMT offset voltage
(1)
–10
PKLMT input current
VPKLMT = –0.1 V
PKLMT to gate driver delay
VPKLMT falling from 50 to –50 mV
Specified by design. Not production tested.
IMult Out =
(2)
Multiplier gain constant (k) is defined by:
–200
10
mV
–100
µA
175
ns
k ´ IAC ´ (VA Out - 1)
VRMS2
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7.6 Typical Characteristics
TA = TJ = 25°C
120
Phase
Margin
degrees
120
Phase
Margin
degrees
100
80
100
80
60
60
Open-Loop 40
20
Gain
dB
0
Open-Loop 40
20
Gain
dB
0
-20
0.1
1
10
100
1000
10000
Frequency
kHz
Figure 1. Current Amplifier Gain and Phase vs Frequency
100%
-20
0.1
1
10
100
1000
10000
Frequency
kHz
Figure 2. Voltage Amplifier Gain and Phase vs Frequency
600
Mult Out=3V
95%
500
Mult Out=2V
Mult Out=1
90%
Mult Out=0V
Duty
85%
Cycle
400
Multiplier
Output 300
μA
80%
75%
VRMS=2V, VA Out=5V
200
70%
1
10
100
100
RSET, k Ω
0
0
100
200
300
400
500
600
700
800
IAC, μ A
Figure 4. Multiplier Output vs Voltage On MULTOUT
Figure 3. Gate-Drive Maximum Duty Cycle
600
250
VRMS=1.5V
VRMS=3V
VA Out=5V
500
200
VA Out=3.5V
400
150
300
VA Out=3V
VA Out=2.5V
Mult Out
μA
Mult Out
μA 100
200
VA Out=2V
VA Out=1.25V
50
100
VA Out=1.25V
0
0
0
8
100
200
300
400
500
0
100
200
300
400
500
IAC, mA
VMULTOUT = 0 V
IAC, mA
VMULTOUT = 0 V
Figure 5. Multiplier Output vs Multiplier Inputs
Figure 6. Multiplier Output vs Multiplier Inputs
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Typical Characteristics (continued)
TA = TJ = 25°C
160
140
VRMS=4V
VA Out=5V
140
VRMS=5V
120
VA Out=5V
120
100
VA Out=4V
100
Mult Out
μ A 80
80
Mult Out,
μA
VA Out=3V
VA Out=3V
60
60
VA Out=2V
40
40
VA Out=1.5V
VA Out=1.25V
20
20
0
0
0
100
200
300
400
500
0
IAC, μ A
100
200
300
400
500
VMULTOUT = 0 V
IAC, μA
VMULTOUT = 0 V
Figure 7. Multiplier Output vs Multiplier Inputs
Figure 8. Multiplier Output vs Multiplier Inputs
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8 Detailed Description
8.1 Overview
The UC3854 provides active power factor correction for systems that otherwise would draw non-sinusoidal
current from sinusoidal power lines. This device implements all the control functions necessary to build a power
supply capable of optimally using available power-line current while minimizing line current distortion.
The UC3854 uses average current-mode control to accomplish fixed-frequency current control with stability and
low distortion. The UC3854, with average current mode control, allows the boost stage to move between
continuous and discontinuous modes of operation without a performance change. Unlike peak current-mode,
average current control accurately maintains sinusoidal line current without slope compensation and with minimal
response to noise transients.
The UC3854 implements all the control functions necessary to build a power supply capable of optimally using
available power-line current while minimizing line-current distortion. The UC3854 contains a voltage amplifier, an
analog multiplier and divider, a current amplifier, and a fixed-frequency PWM. In addition, the UC3854 contains a
power MOSFET compatible gate driver, 7.5-V reference, line anticipator, load-enable comparator, low-supply
detector, and over-current comparator.
8.2 Functional Block Diagram
10
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8.3 Feature Description
The UC3854 integrated circuit contains all the circuits necessary to control a power factor corrector. The UC3854
is designed to implement average current mode control but is flexible enough to be used for a wide variety of
power topologies and control methods.
The top left corner, of the UC3854 block diagram, contains the under voltage lock out comparator and the enable
comparator. The output of both of these comparators must be true to allow the device to operate. The inverting
input to the voltage error amplifier is connected to pin VSENSE. The diodes shown around the voltage error
amplifier are intended to represent the functioning of the internal circuits rather than to show the actual devices.
The diodes shown in the block diagram are ideal diodes and indicate that the non-inverting input to the error
amplifier is connected to the 7.5-V DC reference voltage under normal operation but is also used for the soft-start
function. This configuration lets the voltage control loop begin operation before the output voltage has reached its
operating point and eliminates the turn-on overshoot which plagues many power supplies. The diode shown
between VSENSE and the inverting input of the error amplifier is also an ideal diode and is shown to eliminate
confusion about whether there might be an extra diode drop added to the reference or not. In the actual device
we do it with differential amplifiers. An internal current source is also provided for charging the soft-start timing
capacitor.
The output of the voltage error amplifier is available on pin VAOUT, of the UC3854, and it is also an input to the
multiplier. The other input to the multiplier is lAC, and this is the input for the programming wave shape from the
input rectifiers. This pin is held, internally, at 6 V and is a current input. The feedforward input is VFF, and its
value is squared before being fed into the divider input of the multiplier. The current (ISET) from the RSET pin is
also used in the multiplier to limit the maximum output current. The output current of the multiplier is IMO and it
flows out of pin MULTOUT which is also connected to the non-inverting input of the current error amplifier.
The inverting input of the current amplifier is connected to pin ISENSE. The output of the current error amplifier
connects to the pulse width modulation (PWM) comparator where it is compared to the oscillator ramp on pin CT.
The oscillator and the comparator drive the set-reset flip-flop which, in turn, drives the high current output on pin
GTDRV. The output voltage is clamped internally to the UC3854 at 15 V so that power MOSFETs do not have
their gates over driven. An emergency peak current limit is provided on pin PKLMT and it shuts off the output
pulse when it is pulled slightly below ground. The reference voltage output is connected to pin VREF and the
input voltage is connected to pin VCC.
8.4 Device Functional Modes
This device has no functional modes.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UC3854 control IC is generally applicable to the control of AC-DC power supplies that require Active Power
Factor Correction off Universal AC line. Applications using this IC generally meets the Class D equipment input
current harmonics standards per EN61000-3-2. This standard applies to equipment with rated powers higher
than 75 W.
Performance of the UC3854 Power Factor correction IC in a 250-W application example has been evaluated
using a precision PFC and THD instrument. The result was a power factor of 0.999 and Total Harmonic
Distortion (THD) of 3.81%, measured to the 50th line frequency harmonic at nominal line and full load.
9.2 Typical Application
The circuit of Figure 9 shows a typical application of the UC3854 as a preregulator with high power factor and
efficiency. The assembly consists of two distinct parts: the control circuit centering on the UC3854 and the power
section.
The power section is a boost converter, with the inductor operating in continuous mode. In this mode, the duty
cycle is dependent on the ratio between input and output voltages; also, the input current has low switchingfrequency ripple, which means that the line noise is low. Furthermore, the output voltage must be higher than the
peak value of the highest expected AC line voltage, and all components must be rated accordingly.
At full load, this preregulator exhibits a power factor of 0.99 at any power line voltage from 80 V to 260 VRMS.
This same circuit is used at higher power levels with minor modifications to the power stage. See Optimizing
Performance in UC3854 Power Factor Correction Applications and UC3854 Controlled Power Factor Correction
Circuit Design.
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Typical Application (continued)
Vrec
~
6A
+Vout
-
1mH
+
UHV806
~
0.1µF
R19
511k
t°
Vcc
1µF
385 VDC Out
+
450µF
~
~
-
R3
10k
R14
0.25 Ohms
GND
GND
Isense
Vrec
Multi_Out
Vcc
R15
30K
3W
R13
910K
R18 R9
100 4K
R10
4K
R12
1K6
R17
10
C9
620pF
R8
24K
C10 470pF
D6
C2
100uF
D1
22V
C8
C5
R11
62pF
GND
GND
10k
GND
0.1uF
GND
D5
R16
220k
15
VCC
2
9
REF
PKLMT
U1
16
12
GND
D4
IN5820
91k
C11
0.1uF
C3
0.1uF
1
4
CT
RSET
GT DRV
14
R5
CA OUT
5
ISEN
7
VA OUT
MULT OUT
ENA
VSENSE
IAC
VRMS
13
R4
910k
10
11
6
8
SS
47nF
ENA
3
R7
180k
C7
C6 R6
0.5uF 20k
C4
C1
0.01uF 820pF
R1
15k
GND
Copyright © 2016, Texas Instruments Incorporated
Boost inductor is fabricated with ARNOLD MPP toroidal core part number A-438381-2, using a 55-turn primary and a
13-turn secondary.
Figure 9. 250-W Preregulator Application
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
VIN
RMS input voltage
VOUT
Output voltage
fLine
AC line frequency
POUT(m
Maximum output power
MIN
TYP
80
MAX
UNIT
260
VRMS
65
Hz
250
W
390
47
V
ax)
9.2.2 Detailed Design Procedure
In the control section, the UC3854 provides PWM pulses (GTDRV) to the power MOSFET gate. The duty cycle
of this output is simultaneously controlled by four separate inputs to the chip.
Table 2. Output Duty Cycle
INPUT PIN
FUNCTION
VSENSE
Output DC voltage
IAC
Line voltage waveform
ISENSE, MULTOUT
Line current
VRMS
RMS line voltage
Additional controls of an auxiliary nature are provided. They are intended to protect the switching power
MOSFETS from certain transient conditions.
Table 3. Additional Controls of the Output Duty Cycle
INPUT PIN
FUNCTION
ENA
Startup delay
SS
Soft start
PKLMT
Maximum current limit
9.2.2.1 Protection Inputs
ENA (Enable): The ENA input must reach 2.5 V before the VREF and GTDRV outputs are enabled. This
provides a means to shut down the gate in case of trouble, or to add a time delay at power up. A hysteresis gap
of 200 mV is provided at this terminal to prevent erratic operation. Undervoltage protection is provided directly at
VCC, where the on and off thresholds are 16 V and 10 V. If the ENA input is unused, it must be pulled up to VCC
through a current-limiting resistor of 100 kΩ.
SS (Soft Start): The voltage at SS pin reduces the reference voltage used by the error amplifier to regulate the
output DC voltage. With SS open, the reference voltage is typically 7.5 V. An internal current source delivers
approximately 14 mA from SS. Thus a capacitor (CSS) connected between SS and ground charges linearly from
0 V to 7.5 V in [0.54 × CSS (µF)] s.
PKLMT (Peak Current Limit): Use PKLIM to establish the highest value of current to be controlled by the power
MOSFET. With the resistor divider values shown in Figure 9, the 0-V threshold at PKLIM is reached when the
voltage drop across the 0.25-Ω current-sense resistor is 7.5 V × 2 k / 10 k = 1.5 V, corresponding to 6 A. TI
recommends a bypass capacitor from PKLIM to GND to filter out very high frequency noise.
9.2.2.2 Control Inputs
VSENSE (Output DC Voltage Sense): The threshold voltage for the VSENSE input is 7.5 V and the input bias
current is typically 50 nA. The values shown in Figure 9 are for an output voltage of 400-V DC. In this circuit, the
voltage amplifier operates with a constant low-frequency gain for minimum output excursions. The 47-nF
feedback capacitor places a 15-Hz pole in the voltage loop that prevents 120-Hz ripple from propagating to the
input current.
14
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IAC (Line Waveform): To force the line current waveshape to follow the line voltage, a sample of the power line
voltage in waveform is introduced at IAC. This signal is multiplied by the output of the voltage amplifier in the
internal multiplier to generate a reference signal for the current control loop.
This input is not a voltage, but a current (hence IAC), and is set up by the 220-kΩ and 910-kΩ resistive divider
(see Figure 12). The voltage at IAC is internally held at 6 V, and the two resistors are chosen so that the current
flowing into IAC varies from zero (at each zero-crossing) to about 400 µA at the peak of the waveshape. The
following formulas are used to calculate these resistors:
Vpk
260VAC ´ 2
R AC =
=
= 910 k
IACpk
400 mA
where
•
VPK is the peak line voltage
(2)
R
RREF= AC = 220 k
4
(3)
ISENSE and MULTOUT (Line Current): The voltage drop across the 0.25-Ω current-sense resistor is applied to
ISENSE and MULTOUT as shown. The current-sense amplifier also operates with high low-frequency gain, but
unlike the voltage amplifier, it is set up to give the current-control loop a very wide bandwidth. This bandwidth
enables the line current to follow the line voltage as closely as possible. In the present example, this amplifier
has a zero at about 500 Hz, and a gain of about 18 dB thereafter.
VRMS (RMS Line Voltage): An important feature of the UC3854 preregulator is that it operates with a three-toone range of input line voltages, covering everything from low line in the US (85 VAC) to high line in Europe (255
VAC). This is done using line feedforward, which keeps the input power constant with varying input voltage
(assuming constant load power). To do this, the multiplier divides the line current by the square of the RMS value
of the line voltage. The voltage applied to VRMS, proportional to the average of the rectified line voltage and
proportional to the RMS value, is squared in the UC3854, and then used as a divisor by the multiplier block. The
multiplier output, at MULTOUT, is a current that increases with the current at IAC and the voltage at VAOUT, and
decreases with the square of the voltage at VRMS.
PWM Frequency: The PWM oscillator frequency in Figure 9 is 100 kHz. This value is determined by CT at pin CT
and RSET at pin RSET. RSET must be chosen first because it affects the maximum value of IMULT according to the
equation Equation 4.
-3.75 V
IMULTMAX =
RSET
(4)
This effectively sets a maximum PWM-controlled current. With RSET = 15 k,
-3.75 V
IMULTMAX =
= -250 µA
15 k
(5)
Also note that the multiplier output current never exceeds twice IAC.
With the 4-kΩ resistor from MULTOUT to the 0.25-Ω current-sense resistor, the maximum current in the currentsense resistor is:
-IMULTMAX ´ 4 k
= -4 A
IMAX =
0.25 W
(6)
Having thus selected RSET, the current sense resistor, and the resistor from MULTOUT to the current sense
resistor, calculate CT for the desired PWM oscillator frequency from Equation 7.
1.25
CT =
F ´ RSET
(7)
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9.2.3 Application Curves
700
1000
600
Rise Time
500
ns
Fall Time
400
300
100pF
Frequency
kHz 100
200
200pF
100
500pF
0
0
0.01
0.02
0.03
0.04
0.05
1nF
Load Capacitance, μF
10nF 5nF 3nF 2nF
10
1
Figure 10. Gate-Drive Rise and Fall Time
10
100
RSET, k Ω
Figure 11. Oscillator Frequency vs RSET and CT
10 Power Supply Recommendations
Bypass the VCC pin directly to the GND pin, using a ceramic capacitor of at least 0.1 µF. This bypass capacitor
absorbs supply current spikes required to charge external MOSFET gate capacitances.
VCC must be connected to a stable source that can deliver at least 20 mA. The VCC supply must exceed the
VCC turnon threshold to start switching operation and must remain above the VCC turnoff threshold for normal
operation.
A secondary winding on the PFC boost inductor can be used to deliver a regulated auxiliary bias supply with few
external components as shown in Figure 12. Unlike more conventional and unregulated single diode or bridge
rectifier techniques, this approach uses two diodes in a full wave configuration. This arrangement develops two
separate voltages across capacitors C1 and C2 each with 120-Hz components. However, when these two are
summed at capacitor C3, the line variations are cancelled, and a regulated auxiliary bias is obtained. The number
of turns on the secondary winding adjusts the bias supply voltage.
A bootstrap resistor and storage capacitor must be added, as shown in Figure 12 when VCC is obtained from a
PFC boost inductor auxiliary winding. These parts must be added to ensure the UC3854 controller has sufficient
VCC voltage to start up and operate through the soft-start process until sufficient voltage is available from the
auxiliary winding.
11 Layout
11.1 Layout Guidelines
Figure 12 and Figure 13 show good layout practice. The timing capacitor (C1) and bypass capacitors for VCC
and VREF (C3 and C5) must be connected directly from their respective pins to GND through the shortest route.
Ensure that the ISEN and MULTOUT pins do not drop more than 0.5 V below the GND pin; accomplished by
connecting a Schottky diode (D6) between GND and MULTOUT pins. The local controller GND must be
connected to the power circuit at a single point between the source of the power MOSFET and the current sense
resistor (R14). The power trace running between the power MOSFET source and current sense resistor (R14)
must be kept short. Traces from the upper terminals of R9 and R10 must run directly to each side of the current
sense resistor and not be shared with any other signal.
To minimize the possiblity of interference caused by magnetic coupling from the boost inductor, the device must
be located at least 1 in. away from the boost inductor. TI recommends the device not be placed underneath
magnetic elements.
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11.2 Layout Example
Figure 12. Layout Diagram (Top View)
Figure 13. Layout Diagram (Bottom View)
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Product Folder Links: UC1854 UC2854 UC3854
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Optimizing Performance in UC3854 Power Factor Correction Applications (SLUA172)
• UC3854 Controlled Power Factor Correction Circuit Design (SLUA144)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UC1854
Click here
Click here
Click here
Click here
Click here
UC2854
Click here
Click here
Click here
Click here
Click here
UC3854
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9326101MEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9326101ME
A
UC1854J/883B
UC1854J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
UC1854J
UC1854J883B
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9326101ME
A
UC1854J/883B
UC2854BJ
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-40 to 85
UC2854BJ
Samples
UC2854DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2854DW
Samples
UC2854DWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2854DW
Samples
UC2854N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
UC2854N
Samples
UC3854DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3854DW
Samples
UC3854DWG4
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3854DW
Samples
UC3854DWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3854DW
Samples
UC3854DWTRG4
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3854DW
Samples
UC3854N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3854N
Samples
UC3854NG4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3854N
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Aug-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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