SLUS195B − MARCH 1997 − REVISED NOVEMBER 2003
D Complies with SCSI, SCSI−2 and SPI−2
D
D
D
D
D
D Logic Command Disconnects all
Standards
6-pF Channel Capacitance during
Disconnect
100-µA Supply Current in Disconnect Mode
Meets SCSI Hot Plugging
−400-mA Sourcing Current for Termination
+400-mA Sinking Current for Active
Negation Drivers
D
D
D
D
Termination Lines
Trimmed Termination Current to 3%
Trimmed Impedance to 3%
Negative Clamping on all Signal Lines
Current Limit and Thermal Shutdown
Protection
description
The UC5603 provides 9 lines of active termination for a SCSI (Small Computers Systems Interface) parallel bus.
The SCSI standard recommends active termination at both ends of the cable segment.
The UC5603 provides a disconnect feature which, when opened or driven high, will disconnect all terminating
resistors, and disables the regulator; greatly reducing standby power. The output channels remain high
impedance even without Termpwr applied. A low channel capacitance of 6 pF allows units at interim points of
the bus to have little to no effect on the signal integrity.
Functionally the UC5603 is similar to its predecessor, the UC5601 − 18 line Active Terminator. Several electrical
enhancements were incorporated in the UC5603, such as a sink/source regulator output stage to accommodate
all signal lines at 5 V, while the regulator remains at its nominal value, reduced channel capacitance to 6 pF
typical, and as with the UC5601, custom power packages are utilized to allow normal operation at full power
conditions (1.2 watts).
functional block diagram
UDG-94049
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"# $"%&! ' #(
'"! ! $#!! $# )# # #*
" #
' ' + ,( '"! $!# - '# #!# &, !&"'#
# - && $ # # (
Copyright 2003, Texas Instruments Incorporated
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1
SLUS195B − MARCH 1997 − REVISED NOVEMBER 2003
description (continued)
Internal circuit trimming is utilized, first to trim the impedance to a 3% tolerance, and then most importantly, to
trim the output current to a 3% tolerance, as close to the max SCSI spec as possible, which maximizes noise
margin in fast SCSI operation.
Other features include negative clamping on all signal lines to protect external circuitry from latch-up, thermal
shutdown and current limit.
This device is offered in low thermal resistance versions of the industry standard 16 pin narrow body SOIC.
connection diagrams
DP PACKAGE
(TOP VIEW)
N PACKAGE
(TOP VIEW)
LINE7
LINE8
LINE9
N/C
SGND
DISCNCT
LINE1
LINE2
1
16
2
15
3
14
4
5
6
13
12
11
7
10
8
9
LINE6
LINE5
REG
N/C
N/C
TRMPWR
LINE4
LINE3
LINE7
LINE8
LINE9
GND*
SGND*
DISCNCT
LINE1
LINE2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
LINE6
LINE5
REG
GND*
GND*
TRMPWR
LINE4
LINE3
* DP package pin 5 serves as signal ground; pins 4,
12, 13 serve as heatsink/ground.
ORDERING INFORMATION
Packaged Devices
TA = TJ
DIL -16(N)
0°C to 70°C
UC5603N
SOIC-16 (DP){
UCUC5603DP
† DP (SOIC−16) packages are available taped and reeled. Add TR suffix to device type (e.g.
UC5603DPTR) to order quantities of 2000 devices per reel.
2
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SLUS195B − MARCH 1997 − REVISED NOVEMBER 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†}
Termpwr voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Signal line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 7 V
Regulator output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 A
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Unless otherwise specified all voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Consult
Packaging Section of Unitrode Integrated Circuits databook for thermal limitations and considerations of packages.
recommended operating conditions
Termpwr voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 V to 5.25 V
Signal line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5 V
Disconnect input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to Termpwr
electrical characteristics, these specifications apply for TA = 0°C to 70°C. TRMPWR = 4.75 V
DISCNCT = 0 V, TA = TJ, (unless otherwise stated)
supply current section
PARAMETER
Termpwr supply current
Power down mode
TEST CONDITIONS
MIN
TYP
MAX
UNITS
All termination lines = Open
12
18
mA
All termination lines = 0.5 V
200
220
mA
DISCNCT = Open
100
150
µA
output section (terminator lines)
PARAMETER
Terminator impedance
TEST CONDITIONS
∆ILINE = −5 mA to −15 mA
VTRMPWR = 4 V,
MIN
TYP
MAX
Ω
107
110
2.7
2.9
−21.1
−21.9
−22.4
mA
VLINE = 0.5 V
TJ = 25°C
0°C < TJ < 70°C
−20.5
−21.9
−22.4
mA
TRMPWR = 4 V,
−20.3
−21.9
−22.4
mA
Max output current
VLINE = 0.5 V,
See Note 1
TJ = 25°C
0°C < TJ < 70°C
−19.8
−21.9
−22.4
mA
VLINE = 0.2 V,
ILINE = −30 mA
TRMPWR = 4.0 V to 5.25 V
0°C < TJ < 70°C
−22.0
−24.0
−25.4
mA
Output clamp level
−0.2
−0.05
0.1
10
400
nA
100
µA
10
400
nA
6
8
pF
Output high voltage
Max output current
Output leakage
DISCNCT = 4 V
See Note 1
TRMPWR = 0 V to 5.25,
VREG = 0 V
TRMPWR = 0 V to 5.25 V,
VLINE = 0 V to 5.25 V
Output capacitance
DISCNCT = Open
See Note 2
VLINE = 0 to 4 V
VLINE = 5.25 V
REG = Open
DP Package
113
UNITS
V
V
NOTES: 1. Measuring each termination line while other 8 are low (0.5 V).
2. Ensured by design. Not production tested.
www.ti.com
3
SLUS195B − MARCH 1997 − REVISED NOVEMBER 2003
regulator section
PARAMETER
TEST CONDITIONS
Regulator output voltage
UNITS
2.9
3
2.9
3
V
TRMPWR = 4 V to 6 V
10
20
mV
IREG = 100 mA to −100 mA
All termination lines = 0.5 V
20
50
mV
0.7
1
V
−200
−400
−600
mA
200
400
600
mA
Line regulation
Load regulation
Sinking current capability
MAX
2.8
All termination lines = 5 V
Short circuit current
TYP
2.8
Regulator output voltage
Drop out voltage
MIN
VREG = 0 V
VREG = 3.5 V
Thermal shutdown
Thermal shutdown hysteresis
V
170
°C
10
°C
disconnect section
PARAMETER
TEST CONDITIONS
Disconnect threshold
Threshold hysteresis
Input current
DISCNCT = 0 V
MIN
TYP
MAX
UNITS
1.3
1.5
1.7
V
100
160
250
mV
10
15
mA
APPLICATION INFORMATION
UDG-94050
Figure 1. Typical Wide SCSI Bus Configurations Utilizing 1 UC5601 and 1 UC5603 Device
4
www.ti.com
SLUS195B − MARCH 1997 − REVISED NOVEMBER 2003
APPLICATION INFORMATION
UDG-94051
Figure 2. Typical Wide SCSI Bus Configurations Utilizing 3 UC5603 Devices
www.ti.com
5
PACKAGE OPTION ADDENDUM
www.ti.com
25-Mar-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UC5603DP
LIFEBUY
SOIC
D
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC5603DP
UC5603DPG4
LIFEBUY
SOIC
D
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC5603DP
UC5603DPR
NRND
SOIC
D
16
TBD
Call TI
Call TI
0 to 70
UC5603DPRTR
NRND
SOIC
D
16
TBD
Call TI
Call TI
0 to 70
UC5603DPTR
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
0 to 70
UC5603DPTRG4
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
0 to 70
UC5603J
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
0 to 70
UC5603QPTR
NRND
PLCC
FN
28
TBD
Call TI
Call TI
0 to 70
UC5603DP
UC5603QP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Mar-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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