UCC20520DW

UCC20520 SLUSCN0A – NOVEMBER 2016 – REVISED JANUARY 2022 UCC20520 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver with Single Input 1 Features 3 Description • • • The UCC20520 is an isolated single input, dualchannel gate driver with 4-A source and 6-A sink peak current. It is designed to drive power MOSFETs, IGBTs, and SiC MOSFETs up to 5-MHz with best-inclass propagation delay and pulse-width distortion. • • • • • • • • • • • 2 Applications • • • • • • • Isolated converters in offline AC-to-DC power supplies Server, telecom, IT and industrial infrastructures Motor drive and DC-to-AC solar inverters LED lighting Inductive heating Uninterruptible power supply (UPS) HEV and BEV battery chargers The input side is isolated from the two output drivers by a 5.7-kVRMS reinforced isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 1500-VDC. This driver can be used for half-bridge driver with programmable dead time (DT). A disable pin shuts down both outputs simultaneously when it is set high, and allows normal operation when left open or grounded. As a fail-safe measure, primary-side logic failures force both outputs low. The device accepts VDD supply voltages up to 25-V. A wide input VCCI range from 3-V to 18-V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection. With all these advanced features, the UCC20520 enables high efficiency, high power density, and robustness in a wide variety of power applications. Device Information PART NUMBER UCC20520 (1) PACKAGE(1) DW SOIC (16) BODY SIZE (NOM) 10.30 mm × 7.50 mm For all available packages, see the orderable addendum at the end of the data sheet. VCCI 3,8 16 VDDA Driver PWM 1 DIS 5 NC 2,7 DT MOD DEMOD Reinforced Isolation • Single input, dual output Operating temperature range: –40 to 125°C Switching parameters: – 19-ns typical propagation delay – 10-ns minimum pulse width – 5-ns maximum delay matching – 6-ns maximum pulse-width distortion Common-mode transient immunity (CMTI) greater than 100-V/ns Surge immunity up to 12.8-kV Isolation barrier life >40 Years 4-A peak source, 6-A peak sink output TTL and CMOS compatible inputs 3-V to 18-V input VCCI range to interface with both digital and analog controllers Up to 25-V VDD output drive supply Programmable dead time Rejects input pulses and noise transients shorter than 5-ns Fast disable for power sequencing Industry standard wide body SOIC-16 (DW) package Safety-related and regulatory approvals: – 8000-VPK isolation per DIN V VDE V 0884-11:2017-01 – 5700-VRMS isolation for 1 minute per UL 1577 – CSA certification per IEC 60950-1, IEC 62368-1, IEC 61010-1 and IEC 60601-1 end equipment standards – CQC certification per GB4943.1-2011 Disable, UVLO and Deadtime 6 UVLO 15 OUTA 14 VSSA 13 NC Functional Isolation 12 NC 11 VDDB Driver MOD GND DEMOD UVLO 4 10 OUTB 9 VSSB Copyright © 2016, Texas Instruments Incorporated Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC20520 www.ti.com SLUSCN0A – NOVEMBER 2016 – REVISED JANUARY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Power Ratings.............................................................5 6.6 Insulation Specifications............................................. 6 6.7 Safety-Related Certifications...................................... 7 6.8 Safety-Limiting Values................................................ 7 6.9 Electrical Characteristics.............................................8 6.10 Switching Characteristics..........................................9 6.11 Insulation Characteristics Curves............................10 6.12 Typical Characteristics............................................ 11 7 Parameter Measurement Information.......................... 15 7.1 Propagation Delay and Pulse Width Distortion......... 15 7.2 Rising and Falling Time.............................................15 7.3 PWM Input and Disable Response Time.................. 15 7.4 Programable Dead Time........................................... 16 7.5 CMTI Testing.............................................................16 8 Detailed Description......................................................17 8.1 Overview................................................................... 17 8.2 Functional Block Diagram......................................... 17 8.3 Feature Description...................................................18 8.4 Device Functional Modes..........................................21 9 Application and Implementation.................................. 23 9.1 Application Information............................................. 23 9.2 Typical Application.................................................... 23 10 Layout...........................................................................35 10.1 Layout Guidelines................................................... 35 10.2 Layout Example...................................................... 36 11 Device and Documentation Support..........................38 11.1 Documentation Support.......................................... 38 11.2 Receiving Notification of Documentation Updates.. 38 11.3 Support Resources................................................. 38 11.4 Trademarks............................................................. 38 11.5 Electrostatic Discharge Caution.............................. 38 11.6 Glossary.................................................................. 38 4 Revision History Changes from Revision * (November 2016) to Revision A (January 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Changed maximum pulse-width distortion value in Features from "5 ns" to "6 ns"............................................ 1 • Changed maximum pulse width distortion specification in Section 6.10 from "5 ns" to "6 ns"............................9 • Updated bench test waveform colors for better readability only. No data or measurment changes. ............... 33 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: UCC20520 UCC20520 www.ti.com SLUSCN0A – NOVEMBER 2016 – REVISED JANUARY 2022 5 Pin Configuration and Functions PWM 1 16 VDDA NC 2 15 OUTA VCCI 3 14 VSSA GND 4 13 NC DISABLE 5 12 NC DT 6 11 VDDB NC 7 10 OUTB VCCI 8 9 VSSB Not to scale Figure 5-1. DW Package, 16-Pin SOIC (Top View) Table 5-1. Pin Functions PIN NAME DISABLE DT NO. 5 6 TYPE1 DESCRIPTION I Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. I Programmable dead time function. Tying DT to VCCI disables the DT function with dead time ≅ 0 ns. Leaving DT open sets the dead time to 8 mm >8 mm >21 µm > 600 V CPG External creepage(1) Shortest terminal to terminal distance across the package surface DTI Distance through insulation Distance through internal isolation (internal clearance) CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 Material group According to IEC 60664-1 Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III DIN V VDE 0884-10 (VDE V 0884-10): I 2006-2012(2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK VIOWM Maximum isolation working voltage Time dependent dielectric breakdown (TDDB) test, (See Figure 6-1) 1500 VRMS 2121 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM t = 60 sec (qualification) t = 1 sec (100% production) 8000 VPK VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 12800 VPK (qualification) 8000 VPK Apparent charge(4) qpd CIO Barrier capacitance, input to output(5) RIO Isolation resistance, input to output Method a, After Input/Output safety test subgroup 2/3. Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s pC pF Ω 109 Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO (1) (2) (3) (4) (5) 6 Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification), VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production) 5700 VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-terminal device. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: UCC20520 UCC20520 www.ti.com SLUSCN0A – NOVEMBER 2016 – REVISED JANUARY 2022 6.7 Safety-Related Certifications VDE Certified according to DIN VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01 CSA UL CQC Approved under CSA Component Certified according to UL 1577 Acceptance Notice 5A, IEC component recognition program 60950-1 and IEC 60601-1 Certified according to GB 4943.1-2011 Reinforced insulation maximum transient isolation voltage, 8000 VPK; Reinforced insulation per CSA maximum repetitive peak 60950-1-07+A1+A2 and IEC isolation voltage, 60950-1 2nd Ed. 2121 VPK; maximum surge isolation voltage, 8000 VPK Single protection, 5700 VRMS Reinforced insulation, Altitude ≤ 5000 m, Tropical climate, 400 VRMS maximum working voltage Certification number: 40040142 File number: E181974 Certification number: CQC16001155011 Agency qualification planned 6.8 Safety-Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER IS Safety output supply current PS Safety supply power TS Safety temperature TEST CONDITIONS SIDE MIN TYP MAX UNIT RθJA = 78.1°C/W, VDDA/B = 12 V, TA = 25°C, TJ = 150°C See Figure 6-2 DRIVER A, DRIVER B 64 mA RθJA = 78.1°C/W, VDDA/B = 25 V, TA = 25°C, TJ = 150°C DRIVER A, DRIVER B 31 mA INPUT 50 DRIVER A 775 DRIVER B 775 TOTAL 1600 RθJA = 78.1°C/W, TA = 25°C, TJ = 150°C See Figure 6-3 150 mW °C The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Section 6.4 table is that of a device installed on a High-K test board for leaded surface mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: UCC20520 7 UCC20520 www.ti.com SLUSCN0A – NOVEMBER 2016 – REVISED JANUARY 2022 6.9 Electrical Characteristics VVCCI = 3.3 V or VVCCI = 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IVCCI VCCI quiescent current DISABLE = VCCI 1.5 2.0 mA IVDDA, IVDDB VDDA and VDDB quiescent current DISABLE = VCCI 1.0 1.8 mA IVCCI VCCI operating current (f = 500 kHz) current per channel, COUT = 100 pF 2.5 mA IVDDA, IVDDB VDDA and VDDB operating current (f = 500 kHz) current per channel, COUT = 100 pF 2.5 mA VCCI SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS VVCCI_ON Rising threshold VCCI_ON 2.55 2.7 2.85 V VVCCI_OFF Falling threshold VCCI_OFF 2.35 2.5 2.65 V VVCCI_HYS Threshold hysteresis 0.2 V VDDA/VDDB SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS VVDDA_ON, VVDDB_ON Rising threshold VDDA_ON, VDDB_ON VVDDA_OFF, VVDDB_OFF Falling threshold VDDA_OFF, VDDB_OFF VVDDA_HYS, VVDDB_HYS Threshold hysteresis 8 8.5 9 V 7.5 8 8.5 V 0.5 V PWM AND DISABLE VPWMH, VDISH Input high voltage VPWML, VDISL Input low voltage 8 VPWM_HYS, VDIS_HYS Input hysteresis VPWM Negative transient, ref to GND, 50 ns pulse 1.6 1.8 2 V 0.8 1 1.2 V 0.8 Not production tested, bench test only Submit Document Feedback –5 V V Copyright © 2022 Texas Instruments Incorporated Product Folder Links: UCC20520 UCC20520 www.ti.com SLUSCN0A – NOVEMBER 2016 – REVISED JANUARY 2022 VVCCI = 3.3 V or VVCCI = 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOA+, IOB+ Peak output source current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 4 A IOA-, IOB- Peak output sink current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 6 A ROHA, ROHB Output resistance at high state IOUT = –10 mA, TA = 25°C, ROHA, ROHB do not represent drive pullup performance. See tRISE in Section 6.10 and Section 8.3.4 for details. 5 Ω ROLA, ROLB Output resistance at low state IOUT = 10 mA, TA = 25°C 0.55 Ω VOHA, VOHB Output voltage at high state VVDDA, VVDDB = 12 V, IOUT = –10 mA, TA = 25°C 11.95 V VOLA, VOLB Output voltage at low state VVDDA, VVDDB = 12 V, IOUT = 10 mA, TA = 25°C OUTPUT 5.5 mV Pull DT pin to VCCI 0 ns DT pin is left open, min spec characterized only, tested for outliers 8 15 ns 200 240 ns DEADTIME AND OVERLAP PROGRAMMING Dead time RDT = 20 kΩ 160 6.10 Switching Characteristics VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 6 16 ns 7 12 ns 20 ns tRISE Output rise time, 20% to 80% measured points COUT = 1.8 nF tFALL Output fall time, 90% to 10% measured points COUT = 1.8 nF tPWmin Minimum pulse width tPDHL Propagation delay from INx to OUTx falling edges 19 30 ns tPDLH Propagation delay from INx to OUTx rising edges 19 30 ns tPWD Pulse width distortion |tPDLH – tPDHL| 6 ns tDM Propagation delays matching between VOUTA, VOUTB f = 100 kHz 5 ns Static common-mode transient immunity (See Section 7.5) Slew rate of GND versus VSSA and VSSB, PWM is tied to GND or VCCI CMTI Output off for less than minimum, COUT = 0 pF 100 V/ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: UCC20520 9 UCC20520 www.ti.com SLUSCN0A – NOVEMBER 2016 – REVISED JANUARY 2022 6.11 Insulation Characteristics Curves 1.E+11 1.E+10 Safety Margin Zone: 1800 VRMS, 254 Years Operating Zone: 1500 VRMS, 135 Years TDDB Line (