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UCC24630
SLUSC82A – MARCH 2015 – REVISED MARCH 2015
UCC24630 Synchronous Rectifier Controller
With Ultra-Low-Standby Current
1 Features
3 Description
•
The UCC24630 SR controller is a high-performance
controller and driver for N-channel MOSFET power
devices used for secondary-side synchronous
rectification.
Secondary-Side SR Controller Optimized for 5-V
to 24-V Flyback Systems
Operating Frequency Up to 200 kHz
Volt-Second Balance SR On-Time Control
Minimize Effect of MOSFET Device and Layout
Inductance
CCM Operation Compatibility
Compatible with PSR and SSR Control
Auto Low-Power Detect and 110-µA Standby
Mode Current
Wide VDD Range from 3.6 V to 28 V
Rail-to-Rail Gate Driver with 13-V Clamp
Open and Short Pin Fault Protection
1
•
•
•
•
•
•
•
•
•
The combination of controller and MOSFET emulates
a near-ideal diode rectifier. This solution not only
directly reduces power dissipation of the rectifier but
also reduces primary-side losses as well, due to
compounding of efficiency gains.
2 Applications
•
5-V to 24-V Output Flyback and Forward
Converters
USB-PD Adapters and Chargers with Type-C
Connector
Chargers for Smart Phones and Tablets
Notebook and Ultrabook Adapters
High Efficiency Auxiliary Power in Server, Desktop
and Appliance Applications
Industrial and Medical SMPS
•
•
•
•
•
Utilizing a volt-second balancing control method, the
UCC24630 is ideal for flyback power supplies over a
wide-output voltage range since the device is not
connected directly to the MOSFET drain. The SR
drive turn-off threshold is not dependent on the
MOSFET RDS(on) which allows optimizing for
maximum conduction time. Also secondary current
ringing due to device and layout inductance does not
affect the SR turn-off threshold.
The UCC24630 controller offers a programmable
false-trigger filter, a frequency detector to
automatically switch to standby mode during low
power conditions and pin fault protections. The
UCC24630 is compatible with DCM, TM and CCM
operation.
The wide VDD operating range, wide programming
range of the VPC voltage and blanking time, allows
use in a variety of flyback converter designs.
Device Information(1)
PART NUMBER
UCC24630
PACKAGE
SOT23 (6)
BODY SIZE (NOM)
2.92 mm x 1.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
IOUT
VBLK
NP
VDD
R2
VPC
VSC
2
COUT
4
VDD
HV
7
DRV TBLK
GND
5
2
VS
3
CBC
DRV
6
CS
5
GND
4
5A
UCC24630
UCC28710
1
1-m RDSON MOSFET Example
R3
6
1
NA
15 A
VOUT
NS
VSEC
R1
VAC
Gate-Drive Timing vs VDS Sensing SR Driver
R4
3
RPL
0.85 A
Secondary
Current
R5
Gate Drive
GND
VDS Sensing
Driver
300 ns
Gate Drive
UCC24630
5 Ps
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC24630
SLUSC82A – MARCH 2015 – REVISED MARCH 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 22
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
8.3 Do's and Don'ts ...................................................... 29
9 Power Supply Recommendations...................... 30
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 33
11.1
11.2
11.3
11.4
Device Support ....................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
Changes from Original (March 2015) to Revision A
•
2
Page
Changed Applications section typo. ...................................................................................................................................... 1
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5 Pin Configuration and Functions
DBV Package
6-Pin SOT23
Top View
VPC
1
6
VDD
VSC
2
5
GND
TBLK
3
4
DRV
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
DRV
4
O
DRiVe is an output used to drive the gate of an external synchronous rectifier N-channel MOSFET
switching transistor, with source pin connected to GND.
GND
5
G
The GrouND pin is both the reference pin for the controller and the low-side return for the drive output.
Special care should be taken to return all AC decoupling capacitors as close as possible to this pin and
avoid any common trace length with analog signal return paths.
TBLK
3
–
Time BLanK pin is used to select the blanking time of the VPC rising edge. A programmable range from
200 ns to 1 µs is available to prevent false detection of the primary on-time due to ringing during DCM
operation.
VDD
6
P
VDD is the bias supply input pin to the controller. A carefully placed bypass capacitor to GND is required
on this pin.
VPC
1
I
The Voltage during Primary Conduction pin is connected to a resistor divider from the SR MOSFET
drain. This pin determines a sample of the primary-side MOSFET volt seconds during the primary on-time.
This voltage programs a voltage controlled current source for the internal VPC ramp charging current.
VSC
2
I
The Voltage during Secondary Conduction pin is connected to a resistor divider from the power-supply
output. This pin determines a sample of the secondary-side output voltage used to determine SR MOSFET
conduction time. This voltage programs a voltage controlled current source for the internal VSC ramp
charging current.
(1)
P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
–0.3
30
V
Continuous gate current sink, DRV
50
mA
Continuous gate current source, DRV
–50
mA
IVPC
Peak VPC pin current
–1.2
mA
VDRV
Gate drive voltage at DRV
–0.3
Self limiting
V
VVPC, VVSC
Voltage range, VPC, VSC
–0.3
4.5
V
TJ
Operating junction temperature range
–55
150
°C
TL
Lead temperature 0.6 mm from case for 10 seconds
TSTG
Storage temperature
VVDD
Bias supply voltage, VDD
IDRV
IDRV
(1)
260
–65
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VVDD
Bias supply operating voltage
3.75
28
CVDD
VDD bypass capacitor
0.47
TJ
Operating junction temperature
VVPC, VVSC
Operating Range
UNIT
V
µF
-40
125
°C
–0.3
2.3
V
6.4 Thermal Information
THERMAL METRIC (1)
UCC24630
DBV (6 Pins)
RθJA
Junction-to-ambient thermal resistance
180
RθJC(top)
Junction-to-case (top) thermal resistance
71.2
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
5.1
ψJB
Junction-to-board characterization parameter
13.8
(1)
4
44
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Over operating free-air temperature range, VDD = 12V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY INPUT
IRUN
Supply current, run
IDRV = 0, run state, FSW = 0 kHz
0.9
1.2
mA
ISTBY
Supply current, standby
IDRV = 0, standby mode
110
160
µA
UNDER-VOLTAGE LOCKOUT
VVDD(on)
VDD turn-on threshold
VVDD low to high
3.9
4
4.3
V
VVDD(off)
VDD turn-off threshold
VVDD high to low
3.3
3.6
3.7
V
RDRVLS
DRV low-side drive resistance
IDRV = 100 mA
VDRVST
DRV pull down in start-up
VDD= 0 to 2 V, IDRV= 10 µA
VDRCL
DRV clamp voltage
VVDD = 30 V
11
VPMOS
Disable PMOS high-side drive
VDD voltage to disable rail-to-rail
drive, VDD rising
VPMOS-HYS
PMOS enable hysteresis
VDD voltage hysteresis to enable rail
to rail drive, VDD falling
VDRHI
DRV pull-up high voltage
VVSCEN
DRV
2
Ω
0.95
V
13
15
V
9.3
10
10.5
V
0.75
1
1.25
V
VVDD = 5 V, IDRV = 15 mA
4.6
4.75
5
V
SR enable voltage
VVSC > VVSCEN, VVSC rising
250
300
340
VVSC-HYS
SR enable hysteresis
VVSC falling
VVSCDIS
SR disable voltage
IVSC
Input bias current
VVSC = 2 V
VVPCEN
SR enable voltage
VVPCEN < VVPC
VVPCDIS
VPC threshold to disable SR
VVPC > VVPCDIS
VVPC-TH
Threshold of VVPC rising edge
VVPC = 0.95 V, VVPC-TH = 0.85 x VVPC
previous cycle
VVPC-TH-CLP
Clamp threshold of VVPC rising edge
IVPC
Input bias current
1
VSC INPUT
50
220
mV
mV
280
mV
0
0.4
µA
345
400
450
mV
2.6
2.85
3.1
V
0.76
0.808
0.86
V
VVPC = 2 V
0.9
1
1.1
V
VVPC = 2 V
–0.25
0
0.4
µA
VVPC = 1.25 V, tVPC = 1 µs,
VVSC = 1.25 V
3.97
4.17
4.35
VVPC = 1.25 V, tVPC = 5 µs,
VVSC = 1.25 V
3.95
4.17
4.37
VVPC = 2 V, tVPC = 1 µs,
VVSC = 1.25 V
3.85
4.09
4.26
VVPC = 1.25 V, tVPC = 1 µs,
VVSC = 0.45 V
3.85
4.07
4.28
140%
150%
165%
–0.25
VPC INPUT
CURRENT EMULATOR
RatioVPC_VSC
KVPC/KVSC
CCM DEAD TIME
KCCM-FAULT
If tSW (N+1) > tSW (N) x KCCM-FAULT,
disable SR
nCCM-FLT
Number of cycles to exit CCM fault if
tSW (N+1) < tSW (N) x KCCM-FAULT
4
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Electrical Characteristics (continued)
Over operating free-air temperature range, VDD = 12V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
STANDBY OPERATION
nENTO
Number of switching cycles to enter
standby operation during tENTO
64
nEN
Number of switching cycles to exit
standby operation during tEN (1)
32
OVER TEMPERATURE PROTECTION
T(STOP)
(1)
Thermal shutdown temperature
Internal junction temperature
165
°C
The device exits standby operation as soon as nEN occurs within tEN.
6.6 Timing Requirements
Over operating free-air temperature range, VDD = 12 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
DRV
tR
DRV high-side rise time
tF
DRV low-side fall time
VVDD = 12 V, CL = 3.3 nF, VDRV = 2 V to 8 V
27
54
ns
VVDD = 5 V, CL = 3.3 nF, VDRV = 1 V to 4 V
50
100
ns
VVDD = 12 V, CL = 3.3 nF, VDRV = 8 V to 2 V
20
54
ns
VVDD = 5 V, CL = 3.3 nF, VDRV = 4 V to 1 V
15
50
ns
80
160
ns
65
95
ns
100
125
ns
tDRVON
Propagation delay to DRV High
VVPC = 1 V to –0.05 V falling to DRV high,
VVDD = 12 V, VDRV = 0 V to 2 V
tDRVOFF
Propagation delay to DRV Low
Test mode
VPC Input
tVPC-SPL
VPC sampling time window
tVPC-BLK
Minimum VPC pulse for SR DRV
operation
81
RTBLK = 5 kΩ
169
203
239
ns
RTBLK = 50 kΩ
0.87
1.04
1.2
µs
SR On Control
tSRONMIN
SR minimum on time after VPC falling.
300
350
425
ns
tOFF
SR off blanking time from DRV falling.
2.35
2.5
2.65
us
FSW = 100 kHz, RTBLK = 50 kΩ
(1 µs tVPC-BLK setting)
500
600
700
ns
11.5
12.8
14.1
ms
2.3
2.56
2.82
ms
CCM Dead Time
tCCMDT
SR turn-off dead time in CCM cycle
limit
Standby Operation
tENTO
Time to disable SR operation, enter
standby
Time to disable DRV
tEN
Time to enable SR operation, exit
standby operation
Time to enable DRV (1)
(1)
6
The device exits standby operation as soon as nEN occurs within tEN.
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6.7 Typical Characteristics
VVDD = 12 V, TJ = 25°C, unless otherwise noted.
4.75
150
4.63
140
4.50
4.38
130
VVDD(On)
ISTBY (µA)
VVDD (V)
4.25
4.13
4.00
3.88
120
110
3.75
100
VVDD(Off)
3.63
3.50
90
3.38
3.25
80
±50
±25
0
25
50
75
100
125
150
Temperature (oC)
±50
0
475
375
450
350
VVSCEN (mV)
400
400
375
50
75
100
125
150
C002
Figure 2. Standby Current vs Temperature
500
425
25
Temperature (oC)
Figure 1. VDD Turn-On and Turn-Off Threshold vs
Temperature
VVPCEN (mV)
±25
C001
325
300
275
350
250
325
225
300
200
±50
0
±25
25
50
75
100
125
Temperature (oC)
±50
±25
0
25
50
75
100
125
150
Temperature (oC)
C003
Figure 3. VPC Enable Threshold vs Temperature
C004
Figure 4. VSC Enable Threshold vs Temperature
4.60
4.80
4.50
4.60
4.40
4.30
RatioVPC_VSC
RatioVPC_VSC
4.40
4.20
4.10
4.00
4.20
4.00
3.80
3.90
3.60
3.80
3.70
3.40
±50
±25
0
25
50
75
Temperature (oC)
VVPC = 1.25 V
tVPC = 1 µs
100
125
150
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
VVPC (V)
C005
VVSC = 1.25 V
Figure 5. VPC-to-VSC Ramp Gain Ratio vs Temperature
VVSC = 1.25 V
C006
tVPC × VVPC = 3 V-µs
Figure 6. VPC-to-VSC Ramp-Gain Ratio vs VPC Voltage
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Typical Characteristics (continued)
VVDD = 12 V, TJ = 25°C, unless otherwise noted.
4.8
300
280
4.6
240
4.2
220
tBLK (ns)
RatioVPC_VSC
260
4.4
4.0
200
180
160
3.8
140
3.6
120
3.4
100
0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7
VVSC (V)
VVPC = 12 V
±50
50
75
100
125
150
C009
Figure 8. VPC Blanking Time vs Temperature (minimum
setting)
700
1.25
680
1.20
660
1.15
640
1.10
tCCMDT (ns)
tVPC-BLK (µs)
25
RTBLK = 5 kΩ
1.30
1.05
1.00
0.95
0.90
620
600
580
560
0.85
540
0.80
520
0.75
0.70
500
±50
±25
0
25
50
75
100
125
Temperature (oC)
150
±50
±25
0
Fsw = 100 kHz
Figure 9. VPC Blanking Time vs Temperature (maximum
setting)
2.9
380
2.8
370
2.7
360
2.6
tOFF (µs)
3.0
390
340
75
100
125
150
C011
RTBLK = 50 k
2.5
2.4
330
2.3
320
2.2
310
2.1
300
50
Figure 10. CCM Dead Time vs Temperature
400
350
25
Temperature (oC)
C010
RTBLK = 50 kΩ
tSRONMIN (ns)
0
Temperature (oC)
tVPC = 2 µs
Figure 7. VPC-to-VSC Ramp-Gain Ratio vs VSC Voltage
2.0
±50
±25
0
25
50
75
Temperature (oC)
100
125
150
±50
±25
0
25
50
75
Temperature (oC)
C014
Figure 11. DRV Minimum On Time vs Temperature
8
±25
C007
100
125
150
C015
Figure 12. DRV Minimum Off Time vs Temperature
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7 Detailed Description
7.1 Overview
The UCC24630 SR controller is targeted for flyback converters operating in DCM, TM, and CCM modes of
operation. The control method to determine SR on time is based on the volt-second balance principle of primary
and secondary conduction volt-second product. In converters operating in DCM and TM, the secondary current
always returns to zero in each cycle. In CCM operation, volt-second balance occurs in steady state operation.
The inductor charge voltage and time product is equal to the discharge voltage and time product. The device
uses internal current ramp emulators to predict the proper SR on time based on voltage and time information on
the VPC and VSC pins.
In CCM converters during the transition from DCM operation into CCM, volt-second balance does not occur for a
number of cycles. In this case CCM operation compatibility is achieved by limiting the maximum SR MOSFET on
time with a CCM dead time function based on the previous switching period. There is fault protection to disable
the SR in the event the operating periods become unstable during extreme operating transients.
To achieve very low standby power in the converter, the UCC24630 has a standby mode of operation that
disables the SR MOSFET drive and reduces the device bias current to ISTBY. The device monitors the average
switching frequency of the converter to enter and exit the standby mode of operation, and is compatible with
converters operating in burst mode or constant frequency in light-load mode.
7.2 Functional Block Diagram
Thermal
SD
VPC
1
S&H
UVLO
4.0/3.6V
6
VDD
4
DRV
5
GND
2
VSC
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9
VPC
Thresh
+
SR Control Bias
Bias
tVPC-BLK
+
VPC
Blanking
Timer
TBLK
Fsw Detect
Stand By
VVPCEN
Stand By
VPC
3
Min Toff
tVPC-BLK
SR_On
Detect
S
Q
R
Q
SRon
CCM
Dead Time
Control
Ramp
Enable
DRV
Enable
VPC Ramp
+
-
VSC Ramp
One
Shot
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+
VVSCEN
+
-
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7.3 Feature Description
7.3.1 Start Up and UVLO
The UCC24630 features a wide operating VDD range and low UVLO thresholds. The start up of the device is
dependent on voltage levels on three pins: VDD, VPC and VSC. The VDD pin can be directly connected to the
power supply output on converters from 5-V to 24-V nominal outputs. The start UVLO threshold is VVDD(on), 4.0 V
typical, and stop threshold is VVDD(off), 3.6 V typical. The DRV output is not enabled unless the voltage on the
VPC pin is greater than VVPCEN for a time longer than tVPC-BLK and the voltage on the VSC pin is greater than
VVSCEN. Once the VDD, VSC and VPC voltage and time thresholds are met, there is an internal initialization time
and a four-cycle-initialization start sequence before the DRV output is enabled.
Refer to Figure 13 for a startup sequence that illustrates the timing sequence and configurable DRV output
based on VDD level. In most converter designs, the conditions for the VPC and VSC voltage to enable the
device are met before the VDD start-voltage threshold, this is reflected in the timing diagram. When VDD
exceeds VVDD(on) UVLO threshold the device starts the initialization sequence of 150 µs to 250 µs illustrated as
tINITIALIZE. After the device initialization, there is a logic initialization of 20 µs at which time VTBLK is enabled (high).
After the device is enabled, the CCM dead-time block requires four cycles to initialize the dead-time control
before the DRV output is enabled. At VDD < VPMOS the driver high-side PMOS device is enabled and the DRV
peak will be close to VDD. When VDD exceeds VPMOS the PMOS device is disabled and the driver is operating
as a high-side NMOS only and DRV is approximately 1.2 V to 1.5 V lower than VDD. As VDD continues to
increase, the DRV output is limited to VDRCL regardless of VDD up to the recommended maximum rating.
VPMOS
VVDD(on)
VVDD
tINITIALIZE
20 Ps
VTBLK
VVPC
4 cycle
CCM initialize
VDRCL
VDRV
t
Figure 13. Start-Up Operation
10
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Feature Description (continued)
7.3.2 Volt-Sec SR Driver On-Time Control
Refer to the timing diagrams in Figure 14 and Figure 15 for functional details of the UCC24630 volt-sec on-time
control.
VIN/NPS
Pri Volt-Sec
VOUT
Sec VoltSec
SR VDS
VVPC Pk
VVPC-TH (0.85 VVPC Pk)
VVPCEN
VVPC
DRV
Enable
ramp EN
Primary Drive
and VDRV
Primary
MOSFET
Primary
MOSFET
DRV
DRV
tVPC-BLK
VPC Blanking Time
tVPC-SPL
VPC Sample Time
tOFF
tOFF
tOFF
DRV Inhibit
VPC Ramp
VPC Ramp
VSC Ramp
VSC Ramp
V/s Control
Ramps
IPRI
Normalized Pri
and Sec Current
tPRI
ISEC/NPS
IPRI
ISEC/NPS
tVSC TH
tSEC DIS
Figure 14. Operation in DCM
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Feature Description (continued)
VIN/NPS
VOUT
SR VDS
VVPC Pk
VVPC-TH (0.85 VVPC Pk)
VVPC
DRV
Enable
Ramp EN
Normalized Pri
and Sec Current
IPRI
ISEC/NPS
VPC ramp
IPRI
ISEC/NPS
VPC ramp
VSC ramp
VSC ramp
V/s Control Ramps
tVPC-BLK
VPC Blanking Time
tVPC-SPL
VPC Sample Time
DRV
DRV
VDRV
tOFF
DRV Inhibit
tOFF
tOFF
Figure 15. Operation in CCM
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Feature Description (continued)
The UCC24630 uses the VPC and VSC pins to sense the SR MOSFET VDS voltage and converter VOUT voltage
through resistor dividers. The information of VIN/NPS, tPRI, and VOUT can be obtained from the information on VPC
and VSC pins. The SR MOSFET turn on is determined when the SR MOSFET body diode starts conducting and
the VPC pin voltage falls to near zero; the SR MOSFET turn off is determined by the current emulator control
ramps. The SR timing determined by the volt-sec balance function is the dominant mode of operation with all
flyback converters, including CCM.
The UCC24630 volt-sec control generates the internal VPC ramp and VSC ramp to emulate the transformer VoltSec balancing as shown in Figure 14 and Figure 15.
The secondary current discharge time, tSEC-DIS can be determined indirectly. The primary volt-sec ramp and
secondary volt-sec ramp both start when VPC rises above VVPC-EN and VVPC-TH. The charge currents for the VPC
and VSC ramps are determined by the voltage on the VPC and VSC pins respectively.
When VPC is higher than VVPC-EN and VVPC-TH for t > tVPC-BLK, the VPC pulse is qualified as a primary conduction
pulse and the SR can be enabled on the VPC falling edge. The VPC ramp continues to rise until the VPC falling
edge based on the real time voltage on the VPC pin and holds the peak for the cycle. The DRV output is turned
on during the VPC falling edge near zero volts, and DRV is turned off when the VSC rising ramp crosses the
VPC ramp held level.
Both VPC and VSC ramps are reset to zero on each VPC rising edge above the VVPC-EN and VVPC-TH thresholds.
To discriminate primary on-time pulses from DCM ringing, there are voltage and time criteria that must be
satisfied on the VPC pin to enable the DRV output. tVPC-BLK can be adjusted through the resistor on TBLK pin.
At the rising edge of VPC when the voltage exceeds VVPC-EN and VVPC-TH the blanking time tVPC-BLK is initiated. At
the end of tVPC-BLK, the VPC voltage is sampled during tVPC-SPL window, which is 100 ns nominal. Also at the end
of tVPC-BLK, the DRV output can be enabled.
The VPC voltage sampled during tVPC-SPL determines the VPC dynamic threshold VVPC-TH which is normally 85%
of the sampled VPC voltage. The dynamic threshold provides the ability to reject the DCM ringing and detect the
primary on-time. Noise immunity during the turn-on event of DRV at the falling edge of the VPC pin is enhanced
by a minimum DRV on time of tSRONMIN, which is 350 ns nominal.
During the falling edge of DRV, the tOFF timer is initiated which inhibits turn on of the SR until tOFF expires. This
eliminates false turn on of DRV if the DCM ringing is close to ground.
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Feature Description (continued)
The UCC24630 is designed to operate in a variety of flyback converter applications over a wide operating range.
The internal volt-sec control ramps do have a dynamic range limit based on volt-sec on the VPC pin. As shown
in Figure 16, a Volt-sec product exceeding 7 V-µs on the VPC pin will result in saturation of the VPC volt-sec
control ramp. Operation beyond this point results in a DRV on-time less than expected. For example, if VVPC =
0.5 V, tVPC should be < 14 µs, or if VVPC = 2.0 V, tVPC should be < 3.5 µs, to operate within the dynamic range of
the device. Assuming a converter operating in transition mode at low line and full load with a 50% duty cycle, the
operating period is 28 µs which results in a frequency that is under 40 kHz. The UCC24630 low-frequency
operating range extends to the standby mode threshold of 5 kHz; but each switching cycle VVPC Volt-sec product
should be less than 7 V-µs.
RatioVPC_VSC
The device can support switching frequencies exceeding 200 kHz but the following timing limits need to be
confirmed to be compatible with the power train. The minimum primary on time when the device is expected to
be active needs to be compatible with the minimum VPC blanking time (tVPC-BLK) setting of 203 ns plus the
sampling window (tVPC-SPL) of 100 ns. The minimum secondary current conduction time should be less than the
minimum SR on time (tSR(min)) of 350 ns. The minimum time from the SR drive turn off until the next SR drive turn
on should be greater than the SR minimum off time (tOFF) of 2.5 µs.
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
VPC V-us (uWb)
8.5
C008
Figure 16. RatioVPC_VSC vs VPC V-µs
IOUT
VOUT
NS
6
VSEC
R3
VDD
R1
1
R2
VPC
VSC
2
COUT
UCC24630
4
DRV
TBLK
3
R4
RPL
GND
5
R5
Figure 17. SR Controller Components
14
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Feature Description (continued)
Determining the VPC and VSC divider resistors is based on the operating voltage ranges of the converter and
RatioVPC-VSC gain ratio. Referring to Figure 17, the following equation determines the VPC divider values.
For R2 a value of 10 kΩ is recommended for minimal impact on time delay, and low-resistor dissipation. A higher
R2 value reduces resistor divider dissipation but may increase the DRV turn-on delay due to the time constant of
~2 pF pin capacitance and divider resistance. A lower R2 value can be used with the tradeoff of higher
dissipation in the resistor divider. A factor of 10% over the VPC threshold, VVPCEN, is shown in Equation 1 for
design margin.
éæ VIN(min)
ù
ö
+ VOUT(min) ÷÷ - VVPCEN ´ 1.1ú ´ R2
êçç
êè NPS
ø
ûú
R1 = ë
VVPCEN ´ 1.1
where
•
•
•
•
VIN(min) is the converter minimum primary bulk capacitor voltage.
VOUT(min) is the minimum converter output voltage in normal operation.
VVPCEN is the VPC enable threshold, use the specified maximum value.
NPS is the transformer primary to secondary turns ratio.
(1)
The operating voltage range on the VPC pin should be within the range of 0.45 V < VVPC < 2 V. Referring to
Figure 6, if VVPC is greater than 2.3 V the dynamic range is exceeded and RatioVPC_VSC is reduced; in this
condition the DRV on time is less than expected. If VVPC is greater than 2.6 V for 500 ns, a fault is generated and
DRV is disabled for the cycle, refer to Pin Fault Protection . To ensure the maximum voltage is within range
confirm with Equation 2.
VVPC(max)
æ VIN(max)
ö
+ VOUT(max) ÷ ´ R2
ç
NPS
ø
=è
R1 + R2
where
•
•
•
VIN(max) is the converter maximum primary bulk capacitor voltage.
VOUT(max) is the maximum converter output voltage at OVP.
NPS is the transformer primary-to-secondary turns ratio.
(2)
The program voltage on the VSC pin is determined by the VPC divider ratio and the device's parameter
RatioVPC_VSC. The current emulator ramp gain is higher on the VPC pin by the multiple RatioVPC_VSC, so the VSC
resistor divider ratio is reduced by the same RatioVPC_VSC accordingly. Determine the VSC divider resistors using
equation 3 below. To minimize resistor divider dissipation, a recommended range for R4 is 25 kΩ to 50 kΩ.
Higher R4 values results in increasing offset due to VSC input current, IVSC. Lower R4 values increases the
resistor divider dissipation. To ensure DRV turn off slightly before the secondary current reaches zero, 10%
margin is shown for initial values. Use a nominal value of 4.15 for RatioVPC_VSC.
éæ
R1 + R2
ö ù
êç
÷ ú
R2
R3 = êç
÷ - 1ú ´ R4
êçç Ratio VPC _ VSC ´ 1.1 ÷÷ ú
êëè
ø úû
where
•
RatioVPC_VSC is the device parameter VPC and VSC gain ratio, use a value of 4.15.
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Feature Description (continued)
The operating voltage on the VSC pin should be within the range of 0.3 V < VVSC < 2 V. Referring to Figure 7, if
VVSC is greater than 2.3 V, the dynamic range is exceeded and RatioVPC_VSC is increased; in this condition the
DRV on time is more than expected. To ensure the VSC voltage is within range confirm with Equation 4 and
Equation 5.
R4
´ VOUT(min) ³ 0.3V
R3 + R4
(4)
R4
u VOUT(max) d 2.0 V
R3 R4
where
•
•
VOUT(min) is the minimum converter output operating voltage of the SR controller.
VOUT(max) is the maximum converter output operating voltage of the voltage at OVP.
(5)
Discrimination of ringing during DCM operation from valid primary on-time is achieved by a dynamic VPC rising
threshold and programmable blanking time. The dynamic threshold VVPC-TH is 85% typical ratio of the previous
VPC pin peak voltage. Referring to Figure 14, the VPC pin voltage is sampled after the VPC voltage is greater
than VVPCEN and VVPC-TH for t > tVPC-BLK. The function of the dynamic threshold VVPC-TH is to reject the ringing in
DCM operation from the primary conduction pulses. The dynamic threshold has an active range from the
minimum VVPCEN voltage to a maximum of 1 V clamp. The blanking time is programmable from 200 ns to 1 µs in
order to accommodate a variety of converter designs.
Refer to Figure 18 for guidance on selecting the blanking time. The blanking time should be selected as long as
reasonable and still accommodate the minimum primary on-time at light-load condition and high-line voltage. In
the high-line minimum load condition, select a blanking time that meets the following criteria (Equation 6) to
accommodate tolerance of the blanking time and the tVPC-SPL sampling time window.
tVPC-BLK = (tPRI x 0.85) – 120 ns
(6)
For rejection of DCM ringing, the blanking time should be longer than the time that the ring is above the VVPC-TH
dynamic threshold, which is 85% of the minimum SR VDS peak voltage. Determine these criteria at low line and
maximum load condition. It is recommended that the transformer turns ratio be selected such that the secondary
reflected voltage is < 85% of VIN(min) bulk capacitor voltage at the highest load when DCM operation occurs at the
low line input condition.
To determine the resistor value for tVPC-BLK use Equation 7 to select from a range of 200 ns to 1 µs.
- 100 ns
t
R5 = VPC-BLK
18 pF
where
•
tVPC-BLK is the target blanking time.
(7)
Additional discrimination for proper SR timing control is provided by the tOFF function. Refer to Figure 14 and
Figure 15 for the timing details. After the DRV turn off, the DRV is inhibited from turning on again until the tOFF
timer expires. This protects against SR false turn on from SR VDS DCM ringing below ground.
16
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Feature Description (continued)
High Line Minimum Load
Low Line Maximum Load
Vout
SR VDS
VVPC-TH (1V)
VPC Pk
VVPC-TH (0.85 X VPC Pk)
VVPC
tVPC-BLK
tVPC-BLK
tVPC-SPL
tVPC-SPL
tVPC-BLK
t
tVPC-BLK
tPRI
Figure 18. VPC Blanking Time Criteria
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Feature Description (continued)
7.3.3 CCM Dead Time
Operation of CCM converters during transition from DCM to CCM results in a number of switching cycles where
volt-sec balance is not achieved. To accommodate CCM operation the UCC24630 SR controller incorporates
CCM dead-time protection to ensure turn off of the SR MOSFET before the next primary MOSFET turn on. The
function provides a limit of the total period of the primary on time plus SR on time to the previous cycle minus the
dead time, 600 ns typical. This is accomplished by limiting the SR on time of the active cycle, t (N+1), to the
previous recorded cycle, t (N), minus tCCMDT. As can be seen in Figure 19, the CCM dead time limits the DRV on
time even though the VSC volt-sec ramp threshold is not satisfied.
VIN/NPS
VOUT
SR VDS
VVPC
Primary
MOSFET
Primary
MOSFET
DRV
DRV
Primary
MOSFET
DRV
Primary
MOSFET
DRV
Primary Drive
and VDRV
VPC ramp
VSC ramp
Volt-sec
Control Ramps
Normalized Pri
and Sec Current
IPRI
IPRI
ISEC/NPS
ISEC/NPS
IPRI
ISEC/NPS
IPRI
ISEC/NPS
tCCMDT
tCCMDT
t (N )
t (N) - tCCMDT
t
t(N+1)
Figure 19. CCM Dead-Time Function
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Feature Description (continued)
CCM cycle fault provides protection if the switching frequency is unstable during abnormal conditions. The CCM
cycle fault triggers if the switching period exceeds the previous switching period by KCCM-FAULT, 150% typical. The
CCM cycle fault disables the DRV output for four consecutive cycles. During the four-cycle disable interval if
another CCM cycle fault occurs the fault is retriggered for another four cycles, DRV will not be enabled until four
consecutive cycles occur that do not generate a CCM cycle fault. Refer to Figure 20 and Figure 21 for CCM
cycle fault behavior.
The N+1 cycle with the longer period sets up the next following cycle to have a longer allowable maximum SR on
time based on t(N) – tCCMDT; if CCM operation occurs in this case the maximum allowable SR on time could
conflict with the primary turn on if the converter switching period returns to the previous time. The DRV output is
disabled to prevent this potential timing conflict with the primary switch.
SR VDS
Pri
DRV
Pri
DRV
Pri
Pri
Pri
Pri
Pri
DRV
Primary Drive
and VDRV
CCM Fault
t
t (N+1) > t (N) x KCCM-FAULT
t (N)
Figure 20. CCM Cycle-Fault Behavior, CCM Operation
SR VDS
Pri
DRV
Pri
DRV
Pri
Pri
Pri
Pri
Pri
DRV
Primary Drive
and VDRV
CCM Fault
t (N+1) > t (N) x KCCM-FAULT
t
t (N)
Figure 21. CCM Cycle-Fault Behavior, DCM Operation
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Feature Description (continued)
7.3.4 Standby Operation
To minimize power consumption at very light load and standby conditions, the UCC24630 disables the SR DRV
output and enters a low current operating state. The criteria for operating in standby mode or normal operation
are determined by the average frequency detected on the VPC pin. The frequency detection is compatible with
burst mode operation or continuous low frequency FM operation. At start up the device is in normal operation to
enable DRV to the SR MOSFET. If < 64 cycles occur in tENTO,12.8 ms typical, the device disables the DRV
output and enters low-current operating mode with bias current of ISTBY. In standby mode the criteria to enter
normal operating mode is when > 32 cycles occur within tEN, 2.56 ms typical. The device enters normal operation
as soon as the 32 cycles occur to reduce the response time exiting standby operation. The average frequency of
entering standby mode is 5 kHz typical, and the average frequency of exiting standby mode is 12.5 kHz typical.
Refer to Figure 22 for an illustration of standby mode timing.
Fsw Averaging
Window
tENTO
tEN
tEN
tENTO
> 32 cycles
5 kHz the device is
in normal operation determining the DRV time based on volt-sec control, or CCM dead time control. IDD will be
IRUN.
1. The device operates in volt-sec control when the primary on-time plus the DRV on-time is less than the
previous cycle minus tCCMDT. This is the mode of operation the majority of the time.
2. The device operates in CCM dead-time control when the primary on-time plus DRV on time would be
greater, as determine by the volt-sec control ramps, than the previous cycle minus tCCMDT. This occurs only in
CCM converters, during the transition of DCM into CCM operation
7.4.3 Standby Operation
If the number of VPC pulses is less than nENTO, 64, during tENTO the device enters standby mode. DRV operation
stops and most device functions are shut down. IDD is ISTBY during standby operation. To exit standby mode the
number of VPC pulses must exceed nEN, 32, during tEN. IDD returns to IRUN and the DRV output starts after 4
VPC cycles.
7.4.4 Conditions to Stop Operation
The following conditions can disable DRV operation, IDD is IRUN during these conditions.
1. VPC overvoltage: When VVPC > VVPCDIS for >500 ns the DRV output is disabled for the cycle.
2. CCM Fault: If the current cycle period is greater than the previous cycle times KCCM_FAULT, the DRV output is
disabled for 4 cycles. The 4-cycle count can be reset, and extended if another CCM fault occurs during the
4-cycle DRV disable counter.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC24630 is a high performance controller driver for N-channel MOSFET power devices used for
secondary-side synchronous rectification. The UCC24630 is designed to operate as a companion device to a
primary-side controller to help achieve efficient synchronous rectification in switching power supplies. The
controller features a high-speed driver and provides appropriately timed logic circuitry that seamlessly generates
an efficient synchronous rectification system. With its current emulator architecture, the UCC24630 has enough
versatility to be applied in DCM, TM and CCM modes. The UCC24630 SR on-time adjustability allows optimizing
for PSR and SSR applications. Additional features such as pin fault protection, dynamic VPC threshold sensing,
and voltage sense blanking time and make the UCC24630 a robust synchronous controller. CCM dead-time
protection shuts off the DRV signal in the event of an unstable switching frequency.
8.2 Typical Application
8.2.1 AC-to-DC Adapter, 19.5 V, 65 W
This design example describes the design of a 65-W off-line flyback converter providing 19.5 V at 3.33-A
maximum load and operating from a universal AC input. The design uses the LM5023 AC-to-DC quasi-resonant
primary-side controller in a DCM type flyback converter and achieves over 92% full-load efficiency with the use of
the secondary side UCC24630 synchronous rectifier controller.
• The design requirements are detailed in Section 9.2.2
• The design procedure for selecting the component circuitry for use with the UCC24630 is detailed in
Calculation of Component Values.
• Test results shown in section 9.2.4 highlight the unique advantages of using the UCC24630.
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Typical Application (continued)
4
3
2
~
3
2
~
3
2
2
2
1
3
3
3
1
4
2
Figure 23. AC-to-DC Adapter 19 V, 65 W
24
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Typical Application (continued)
8.2.2 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Performance Specifications AC-to-DC Adapter 19 V, 65 W
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Input Characteristics
VACIN
Input voltage
90
115/230
265
V
fLINE
Frequency
47
50/60
64
Hz
VAC(uvlo)
Brownout voltage
VAC(run)
Brownout recovery voltage
IIN
Input current
IOUT = IOUT(nom)
VACIN = VACIN(min), IOUT = IOUT(nom)
80
VRMS
90
VRMS
1.65
A
Output Characteristics
VOUT
Output voltage
VACIN = VACIN(min) to VACIN(max),
IOUT = 0 to IOUT(nom)
IOUT(nom)
Nominal output current
VACIN = VACIN(min) to VACIN(max)
3.33
A
IOUT(min)
Minimum output current
VACIN = VACIN(min) to VACIN(max)
0
A
ΔVOUT
Output voltage ripple
VACIN = VACIN(min) to VACIN(max),
IOUT = 0 to IOUT(nom)
500
mV
POUT
Output power
VACIN = VACIN(min) to VACIN(max)
65
18.5
19.5
20.5
V
System Characteristics
ηavg
Average efficiency
VACIN = VACIN(nom), IOUT = 25%, 50%, 75%, 100% of
IOUT(nom)
89%
90%
ƞ10%
10% Load efficiency
VACIN = VACIN(nom), IOUT = 10% of IOUT(nom)
79%
82%
PNL
No load power
VACIN = VACIN(nom), IOUT = 0
60
120
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8.2.3 Calculation of Component Values
IOUT
VOUT
NS
6
VSEC
R17
VDD
R15
1
R16
VPC
VSC
2
COUT
UCC24630
4
DRV
TBLK
3
R18
RPL
GND
5
R19
Figure 24. UCC24630 Circuit Design
For ease of understanding, Figure 24 is a modified version of Figure 17 where the component reference
designators are the same as the schematic drawing of Figure 23.
8.2.3.1 VPC Input
For minimal power dissipation:
R16 10k:
R15
ª§ VIN(min)
º
·
VOUT(min) ¸ VVPC _ EN u 1.1» u R16
Ǭ
«¬© NPS
»¼
¹
VVPC _ EN
VOUT(min)
NPS
18 V
5.5
VIN(min)
60 V
R15 = 574 k:
(8)
With R15 = 576 kΩ
VIN(max)
(
VOUT(max) ) u R16
NPS
VVPC(max)
R15 R16
VVPC(max) 1.50 V
(
VIN(min)
VVPC(min)
NPS
VVPC(min)
0.49 V
(9)
VOUT(min) ) u R16
R15 R16
(10)
Therefore, VVPC is within the recommended range of 0.45 V to 2 V.
26
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8.2.3.2 VSC Input
The value of R18 is recommended to be with the range of 25 kΩ to 50 kΩ.
R18 = 47 kW
éæ
R15 + R16
ö ù
êç
÷ ú
R16
R17 = êç
÷ - 1ú ´ R18
êçç Ratio VPC _ VSC ´ 1.1 ÷÷ ú
ø ûú
ëêè
R17 = 554 kW
(11)
With R17 = 590 kΩ the operating range of the VSC pin is:
R18
ª
º
VVSC(min) «(
)» u VOUT(min)
¬ R17 R18 ¼
VVSC(min) 1.32 V
VVSC(max)
VVSC(max)
(12)
R18
ª
º
«( R17 R18 )» u VOUT(max)
¬
¼
1.55 V
(13)
Therefore, VVSC is within the recommended range of 0.3 V to 2 V.
8.2.3.3 TBLK Input
The blanking time is set with resistor R19.
Select the blanking time to meet the following criteria based on minimum primary on-time at high line.
tVPC-BLK = (tPRI × 0.85) – 120 ns
spacer
R19 =
t VPC-BLK - 100 ns
18 pF
(14)
A value of R19 = 18 kΩ results in a blanking time of approximately 420 ns.
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8.2.4 Application Curves
C2(RED): DRV signal to synchronous rectifier Q1
C1(YELLOW): Drain of synchronous rectifier Q1
C2(RED): DRV signal to synchronous rectifier Q1
C1(YELLOW): Drain of synchronous rectifier Q1
Figure 25. DRV Timing at 230 VAC, 65 W
Figure 26. DRV Timing at 115 VAC, 65 W
C2(RED): DRV signal to synchronous rectifier Q1
C1(YELLOW): Drain of primary-side MOSFET Q3
C2(RED): DRV signal to synchronous rectifier Q1
C1(YELLOW): Drain of primary-side MOSFET Q3
Efficency (%)
Figure 27. DRV Timing at 230 VAC, 12 W
Figure 28. Light-Load Behavior (230 VAC, 8 W)
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
115 VAC
230 VAC
6
12
18
24
30
36
42
Output Power (V)
48
54
60
66
D001
Figure 29. Efficiency vs Output Power
28
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8.3 Do's and Don'ts
•
•
•
•
•
•
Do operate the device within the recommended operating maximum parameters. Consider output overvoltage
conditions when determining stress.
Do consider the guideline for setting the blanking time resistor value illustrated in Figure 18.
Do not use the UCC24630 with converters that operate in constant skip cycle mode at high-power levels. The
skip cycle behavior results in numerous CCM faults and missing DRV pulses.
Do not use the UCC24630 in CCM designs that are operating in CCM while the flyback controller is operating
in variable frequency, FM, modulation. The CCM dead-time function is compatible with CCM operation during
fixed-frequency, PWM operation.
Do not use the UCC24630 in hysteretic control CCM flyback converters. Constant skip-cycle operation at
high-power levels results in numerous CCM cycle faults resulting in efficiency loss.
Do not use the UCC24630 in LLC converters.
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9 Power Supply Recommendations
The UCC24630 is recommended as a synchronous rectifier controller in a wide variety of flyback power supplies.
It is compatible with Discontinuous Conduction Mode (DCM) and Transition Mode (TM) controllers in fixed
frequency or variable frequency applications. It is compatible with Continuous Conduction Mode (CCM)
controllers in fixed frequency applications.
It is suitable as a synchronous rectifier for flyback power supplies with an input of 85 VAC to 265 VAC and an
output from 5 V to 24 V. It can also be used in other flyback applications with different input and/or output
voltages. But be sure all voltages and currents are within the recommended operating conditions and absolute
ratings of the device.
It is compatible with flyback converters operating at the transition mode limit, at low line, with switching
frequencies as low as 40 kHz. It may also be used in switching speeds up to 200 kHz.
The VDD operating range allows direct connection to converter outputs from 5 V to 24 V. Since the driver and
control share the same VDD and ground, it is recommended to place a good quality ceramic capacitor as close
as possible to VDD and GND pins. To reduce VDD noise and eliminate high-frequency ripple current injected
from the converter output, it is recommended to place a small resistance of 2.2 Ω to 10 Ω between the converter
output and VDD. The device can tolerate VDD rise times from 100 µs to very long rise times typical of constant
current chargers. The start-up sequence will always be as shown in Figure 13. VDD can be connected to an
external bias to extend the device's operating range below 3.5 V or above 24-V converter outputs.
30
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10 Layout
10.1 Layout Guidelines
In general, try to keep all high current loops as short as possible. Keep all high current/high frequency traces
away from other traces in the design. If necessary, high-frequency/high-current traces should be perpendicular to
signal traces, not parallel to them. Shielding signal traces with ground traces can help reduce noise pick up.
Always consider appropriate clearances between the high-voltage connections and any low-voltage nets.
10.1.1 VDD Pin
The VDD pin must be decoupled to GND with good quality, low ESR, low ESL ceramic bypass capacitors with
short traces to the VDD and GND pins. The value of the required capacitance on VDD is determined as shown in
Section 7.3 . To eliminate high-frequency ripple current in the SR control circuit, it is recommended to place a
small value resistance of 2.2 Ω to 10 Ω between VDD and the converter output voltage.
10.1.2 VPC Pin
The trace between the resistor divider and the VPC pin should be as short as possible to reduce/eliminate
possible noise coupling. The lower resistor of the resistor divider network connected to the VPC pin should be
returned to GND with short traces. Avoid adding any significant external capacitance to the VPC pin so that there
is no delay of signal. If filtering is necessary a recommended maximum capacitance is 10 pF with a lower resistor
divider network value of 10 kΩ. Avoid high dV/dt traces close to the VPC pin and connection trace such as the
SR MOSFET drain and DRV output.
10.1.3 VSC Pin
The trace between the resistor divider and the VSC pin should be as short as possible to reduce/eliminate
possible noise coupling. The lower resistor of the resistor divider network connected to the VSC pin should be
returned to GND with short traces. Avoid adding any external capacitance to the VPC pin so that there is no
delay of signal. If filtering is necessary a recommended maximum capacitance is 47 pF with a lower resistor
divider network value of 50 kΩ. Avoid high dV/dt traces close to the VSC pin and connection trace such as the
SR MOSFET drain and DRV output.
10.1.4 GND Pin
The GND pin is the power and signal ground connection for the controller. The effectiveness of the filter
capacitors on the signal pins depends upon the integrity of the ground return. Place all decoupling capacitors as
close as possible to the device pins with short traces. The device ground and power ground should meet at the
output bulk capacitor’s return. Try to ensure that high frequency/high current from the power stage does not go
through the signal ground.
10.1.5 TBLK Pin
The programming resistor is placed on TBLK to GND, with short traces. The value may have to be adjusted
based on the time delay required. Avoid high dV/dt traces close to the TBLK pin and connection trace such as
the SR MOSFET drain and DRV output.
10.1.6 DRV Pin
The track connected to DRV carries high dv/dt signals. Minimize noise pickup by routing the trace to this pin as
far away as possible from tracks connected to the device signal inputs, VPC, VSC, and TBLK.
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10.2 Layout Example
SGND
Vout
C9
T1 pins 8,9
C8
T1 pins 10,11
32
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
11.1.1.1 Definition of Terms
• VIN(min) = 60 V: converter minimum primary bulk capacitor voltage
• VIN(max) = 370 V: converter maximum primary bulk capacitor voltage
• VOUT(min) = 18 V: minimum converter output operating voltage of the UCC24630
• VOUT(max) = 21 V: maximum converter output operating voltage of the UCC24630
• VVPC_EN = 0.45 V: synchronous rectifier enable voltage
• VVPC(max) = 2.0 V: maximum operating level of VPC
• NPS = 5.5: transformer primary to secondary turns ratio
• RatioVPC_VSC = 4.15 : Current emulator gain KVPC/KVSC
• tVPC_BLK: Minimum VPC pulse for synchronous rectifier operation
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC24630DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
U630
UCC24630DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
U630
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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