UCC2541PWPRG4

  SLUS621A − AUGUST 2004 − SEPTEMBER 2005     
 
   APPLICATIONS D High Efficiency Non-Isolated Converters FEATURES D On-Chip Predictive Gate Drivet for D D D D D D D D D D High-Efficiency Synchronous Buck Operation Dual ±3-A TrueDrivet Outputs On-Board Programmable Oscillator with 1-MHz Frequency Operation TR Input for Sequencing Operation Overcurrent Protection using a Parallel Average Current Mode Control Loop 3 Modes to Support 2.7-V to 35-V Input Bias Reverse Current Protection for Output Stage User Programmable Shutdown Using SS Pin ±1.0% Initial Tolerance Bandgap Reference High Bandwidth Error Amplifiers Thermally Enhanced HTSSOP 20-Pin PowerPADt Package and QFN−32 Pin Synchronization Input Supports Pre-Bias Applications D D Requiring Advanced Features such as Pre-Bias Support and Tracking Capability Point-of-Load Modules for Servers, Telecom, and Data communication Equipments Good for Input Voltages of 3.3 V, 5.0 V, 12.0 V, or Intermediate Bus Voltages DESCRIPTION The UCC2541 is a synchronous buck PWM controller for high current and low output voltage applications. For higher efficiency, it incorporates the Predictive Gate Drivet technology that virtually eliminates body diode conduction losses in synchronous rectifiers. D D SIMPLIFIED APPLICATION DIAGRAM TR Input 1 RSET UCC2541 SWS 2 REF 3 G2C 4 20 VIN BST 19 G1 18 SYNCIN SW 17 5 RAMP VDD 16 6 GND 7 VEA− G2 14 8 CEA− VDRV 13 9 COMP G2S 12 10 TR VOUT PGND 15 SS 11 Predictive Gate Drive, TrueDrive and PowerPAD are trademarks of Texas Instruments Incorporated. 
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  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DESCRIPTION (CONT.) The UCC2541 is available in the extended temperature range of –40°C to 105°C and is offered in thermally enhanced PowerPADt 20-pin HTSSOP (PWP) or 32-pin quad flatpack (RHB) package. This space saving package with standard 20-pin TSSOP footprint has a drastically lower thermal resistance of 1.4°C/W θJC to accommodate the dual high-current drivers on board. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted)(1)(2) Supply voltage range, VDD Supply current, IVDD VDD CEA−, COMP, G2C, RAMP, SS, TR, VEA− UNIT 36 V 50 mA −0.3 to 3.6 VDRV Analog input voltages UCC2541 −0.3 to 9 G1, BST SW−0.3 to SW+9 SW, SWS −1 to 36 G2, G2S −1 to 9 SYNCIN −0.3 to 8.0 Sink current (peak), IOUT_SINK G1, G2 3.5 Source current (peak), IOUT_SOURCE G1, G2 −3.5 Operating junction temperature range, TJ −55 to 150 Storage temperature, Tstg −65 to 150 V A °C C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal. RECOMMENDED OPERATING CONDITIONS MIN 2 TYP MAX Supply voltage, VDD Mode 1 8.5 35 Supply voltage, VDRV Mode 2 4.75 9.00 Supply voltage, REF Mode 3 3.0 3.3 Supply voltage bypass, CVDD 1.0 2.2 Reference bypass capacitor, CREF 0.1 1.0 VDRV bypass capacitor, CVDRV 0.2 BST−SW bypass capacitor, CBST−SW 0.1 2.2 10 50 PWM ramp capacitor range, CRAMP 100 680 Turn-off capacitor range, CG2C 120 1000 6.5 Junction operating temperature, TJ −40 www.ti.com V 3.6 Timer current resistor range, RRSET COMP pin load range, RLOAD UNIT µF F kΩ pF kΩ 105 °C 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 ORDERING INFORMATION TA = TJ HTSSOP−20 (PWP)(1) QFN−32 (RHB)(1) Bulk Bulk −40°C to +105°C UCC2541PWP (1) The PWP and RHB packages are also available at 73 devices per tube and taped and reeled at 3,000 devices per reel. Add an R suffix to the device type (i.e., UCC2541PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. UCC2541RHB CONNECTION DIAGRAM RHB PACKAGE (TOP VIEW) NC NC NC NC NC SWS BST BST 31 30 29 28 27 26 25 SYNCIN 4 21 VDD RAMP 5 20 PGND GND 6 19 PGND VEA− 7 18 G2 CEA− 8 17 G2 16 SW NC 22 VDRV 3 15 G2C 14 G1 G2S 23 13 2 SS VREF 12 G1 NC 24 11 1 TR RSET NC SWS BST G1 SW VDD PGND G2 VDRV G2S SS 9 20 19 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 10 COMP RSET REF G2C SYNCIN RAMP GND VEA− CEA− COMP TR 32 PWP PACKAGE (TOP VIEW) NC − No internal connection NOTE: The PowerPADt is not directly connected to any lead of the package, but is thermally connected to the substrate of the device. The exposed dimension is 1.3 mm x 1.7 mm for the PWP package and 3.25 mm x 3.25 mm for the RHB package. However, the tolerances can be +1.05 mm / −0.05 mm (+41 mils / −2 mils) due to position and mold flow variation. THERMAL INFORMATION PACKAGE FAMILY PACKAGE DESIGNATOR θJA (°C/W) (with PowerPAD) θJC (°C/W) (without PowerPAD) θJC (°C/W) (with PowerPAD) MAXIMUM DIE TEMPERATURE PowerPAD HTSSOP−20 PWP 22.3 to 32.6 (500 to 0 LFM) 19.9 1.4 125°C Quad Flatpack QFN−32 RHB 22.3 to 32.6 (500 to 0 LFM) 19.9 1.4 125°C www.ti.com 3 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, CRAMP = 517 pF, RSET = 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX DC, after G2 timeout 5 8 10 CLOAD = 2.2 nF 9 18 30 UNIT OVERALL IVDD Operating current mA UNDERVOLTAGE LOCKOUT VVDD VVDD Start threshold voltage MODE 1 8.0 8.5 9.0 Stop threshold voltage MODE 1 7.5 8.0 8.5 VVDD VVDRV Hysteresis MODE 1 0.3 0.5 0.8 Start threshold voltage MODE 2 4.30 4.65 4.85 VVDRV VVDRV Stop threshold voltage MODE 2 4.0 4.3 4.6 Hysteresis MODE 2 0.15 0.35 0.55 VREF VREF Start threshold voltage MODE 3 2.5 2.8 3.2 Stop threshold voltage MODE 3 2.2 2.5 2.8 MODE 3 0.15 0.35 0.55 TA = 25°C Total variation 3.28 3.30 3.35 3.2 3.3 3.4 10 13 20 0 1.5 15 0 30 70 270 300 330 0.10 0.25 0.50 1.7 2.0 2.3 VREF Hysteresis VOLTAGE REFERENCE (REF) VREF Reference output voltage ISC Short circuit current VVDD= VVDRV Line regulation VREF = 0 V, TA = 25°C 5.25 V ≤ VDRV ≤ 7.2 V Load regulation 0 mA ≤ IREF ≤ 5 mA V V mA mV OscillatorPWM (RAMP) fSW DMIN Oscillator frequency VRAMP Offset voltage Minimum duty cycle 0% Oscillator peak voltage tDEAD IRAMP G1 deadtime at maximum duty cycle ratio Ramp charge current kHz RRSET = 10 kΩ V 150 175 200 ns −325 −300 −275 µA 45 50 55 3 4 CURRENT ERROR AMPLIFIER VCEA+ GBW VOL Offset voltage Total variation Gain bandwidth(3) Low-level output voltage VOH High-level output voltage AVOL IBIAS Open loop ICOMP = 0 A, VVEA− = 2.0 V VCEA− = 3.3 V, ICOMP = 100 µA, VVEA− = 1 V VCEA− = 1.5 V ICOMP = 0 A, VVEA− = 1 V VCEA− = 0 V, Bias current ISINK Sink current CMR Common mode input range(3) VCOMP = 1.0 V, VVEA− = 1 V 0.1 V 0 0.60 0.90 2.2 2.5 3.0 V 60 100 160 dB −200 −80 −10 nA 0.30 0.80 1.70 mA 0 (3) Ensured by design. Not production tested. 4 VCEA− = 1.5 V, www.ti.com mV MHz 2 V 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, CRAMP = 517 pF, RSET = 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.40 0.75 1.00 V 1.485 1.500 1.515 1.47 1.50 1.53 3 4 VOLTAGE ERROR AMPLIFIER VSS_OFF VTR_OFF Offset voltage from soft-start input Offset voltage from tracking input VVEA+ Threshold voltage (from VEA− to COMP) GBW Gain bandwidth(3) VOL Low-level output voltage VOH High-level output voltage AVOL IBIAS Open loop ISINK Sink current VCOMP = VVEA−, VSS− = 1.5 V VTR = 1.0 V 0°C ≤ TA ≤ 105°C Total variation ICOMP = 0 A, VVEA− = 2.0 V, VCEA− = 3.3 V, ICOMP = 100 µA, VVEA− = 1 V, VCEA− = 0 V, VTR = 0 V ICOMP = 0 A, VVEA− = 1 V VCEA− = 0 V −10 10 mV V MHz 0.1 0 0.60 0.9 2.2 2.5 3.0 V 60 100 140 dB −500 −250 −50 nA 0.30 0.80 1.70 mA RRSET = 10 kΩ −158 −150 −142 µA RSET voltage RRSET = 10 kΩ SYNCHRONIZATION AND SHUTDOWN TIMER (SYNCIN, G2C) 1.42 1.50 1.58 V 2.3 2.5 2.7 1.50 1.65 1.80 Bias current VCOMP = 1.0 V, VVEA− = 1.0 V, VCEA− = 0 V, VTR = 0 V CURRENT SET IOUT VRSET Output current Timer threshold SYNCIN threshold V µA ICHG(G2C) Shutdown timer charge current SOFT-START (SS) RRSET = 10 kΩ −325 −300 −275 ICH(SS) IDSCH(SS) Charge current RRSET = 10 kΩ −230 −200 −170 Discharge current RRSET = 10 kΩ 45 70 100 0.35 0.45 0.55 V 6.87 7.20 7.53 V Discharge/shutdown threshold A µA DRIVE REGULATOR (VDRV) VVDRV Output voltage Line regulation 9 V ≤ VVDD ≤ 35 V 0 50 100 Load regulation −5 mA ≤ IVDRV ≤ 0 mA 0 50 100 15 30 50 VSWS = 0 V VSWS = 0 V 1.90 2.25 3.10 1.00 1.25 1.30 VG2S = 0 V −0.70 −0.50 −0.37 VG2S = 0 V VG2S = 0 V 1.90 2.25 2.90 1.0 1.2 1.3 VSWS = 0 V Outputs disabled −1.8 −1.3 −0.9 mA 1.0 µA −0.1 V ISC Short-circuit current G2S GATE DRIVE SENSE G2S rising threshold voltage G2S falling threshold voltage IG2S Current SWS SWITCH NODE SENSE SWS rising threshold voltage SWS falling threshold voltage ISWS Current Negative threshold voltage −1.0 −0.5 −0.3 mV mA V mA V (3) Ensured by design. Not production tested. www.ti.com 5 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, CRAMP = 517 pF, RSET = 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.3 0.7 1.3 10 25 45 UNIT G1 MAIN OUTPUT RSINK Sink resistance RSRC Source resistance Sink current(3) ISINK ISRCE tRISE tFALL VSW = 0 V, VSW = 0 V, VBST = 6 V, VBST = 6 V, VG1 = 0.3 V VG1 = 5.7 V Source current(3) VSW = 0 V, VSW = 0 V, VBST = 6 V, VBST = 6 V, VG1 = 3.0 V VG1 = 3.0 V Rise time CLOAD = 2.2 nF, from G1 to SW 12 25 Fall time CLOAD = 2.2 nF, from G1 to SW 12 25 15 30 Ω 3 A −3 ns G2 SYNCHRONOUS RECTIFIER OUTPUT RSINK ISINK ISRC tRISE tFALL Sink resistance Sink current(3) VG2 = 0.3 V VG2 = 3.25 V Source current(3) −3 Rise time VG2 = 3.25 V CLOAD = 2.2 nF, from G2 to PGND 12 25 Fall time CLOAD = 2.2 nF, from G2 to PGND 12 25 6.2 6.7 7.5 RAMP rising to G1 rising 90 115 130 SYNCIN falling to G1 falling 50 70 90 Delay control resolution 3.5 5.0 6.5 VOH High-level output voltage, G2 DEADTIME DELAY (see Figure 1) tON(G1) tOFF(G1) tON(G2) tOFF(G2) 5 Ω 3 VSW = GND tON(G2) tON(G2) G2 on-time minimum wrt G1 falling −24 G2 on-time maximum wrt G1 falling 62 tOFF(G2) tOFF(G2) G2 off-time minimum wrt G1 rising −68 G2 off-time maximum wrt G1 rising 10 A ns V ns (3) Ensured by design. Not production tested. tOFF,G1 CLK 2.0V V ERR RAMP G2C t ON,G1 tON,G2 G1 tOFF,G2 G2 Figure 1. Predictive Gate Drive Timing Diagram 6 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 FUNCTIONAL BLOCK DIAGRAM RSET 1 REF ISET + 1.5V − 20 SWS VREF VDRV VDD VDRV VREF 2 HIGH SIDE DRIVER UVLO REFERENCE GLO PWR 18 G1 VREF 2 I SET G1D G2C GLO G2 UVLO 3 SYNCIN 4 17 SW G2 TIMER G2TO G1D UVLO DRIVE REGULATOR 100nsCLK CLK GEN 16 VDD 15 PGND VREF 2 I SET RAMP 5 GND 19 BST PREDICTIVE LOGIC RAMP 6 PGND PWM OSCILLATOR RAMP & PWM LOGIC BIAS PWR LOW SIDE DRIVER 14 G2 VERR VEA− 7 CEA− 8 COMP 9 PGND ERROR AMPLIFIERS AND FAULT LOGIC 13 VDRV VREF HUP 1.33 I 12 G2S SET 11 SS TR 10 1.73 I SET www.ti.com 7 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 PIN ASSIGNMENTS TERMINAL NAME NO. I/O DESCRIPTION BST 19 I Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on time. Bypass BST to SW with an external capacitor. CEA− 8 I Inverting input of the current error amplifier used for output current regulation. COMP 9 I Output of the voltage and current error amplifiers for compensation. G1 18 O High-side gate driver output that swings between SW and BST. G2 14 O Low-side gate driver output that swings between PGND and VDRV. G2C 3 I Timer pin to turn off synchronous rectifier. The capacitor connected to this pin programs the maximum duration that G2 is allowed to stay HIGH. G2S 12 I Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate deadtime. GND 6 − Ground for internal circuitry. GND and PGND should be tied together under the device. See layout guidelines for further details. PGND 15 − Ground return for the G2 driver. Connect PGND to the pc-board ground plane with several vias. RAMP 5 I Input pin to connect timing capacitor to GND to generate the oscillator PWM ramp. REF(1) 2 I/O RSET 1 I Pin to program timer currents for G2C, RAMP, SS charge and SS discharge. This pin generates a current proportional to the value of the external resistor connected from RSET pin to GND. RSET range is 10 kΩ to 50 kΩ (giving a programmable nominal ISET range of 30 µA to 150 µA, respectively). SS 11 I Soft start and shutdown pin. Connect a capacitor to GND to set the soft-start time. Add switch to GND for immediate shutdown functionality. 3.3-V reference pin. All analog control circuits are powered from this 3.3-V rail. Bypass this pin with at least 0.1 µF of capacitance for REF loads that are 0 mA to −1 mA. Bypass this pin with at least 1 µF of capacitance if it is used as an input (Mode 3) or if it has large or pulsating loads. SYNCIN 4 I Input pin for timing signal. Tie to logic high (VREF) when not used. SW 17 − G1 driver return connection. SWS 20 I Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain close to the MOSFET package. TR 10 I Tracking input to the voltage error amplifier. Connect to REF when not used. VDD 16 I Power supply pin to the device and input to the internal VDRV drive regulator. Normal VDD range is from 4.5 V to 36 V. Bypass the pin with at least 1 µF of capacitance. VDRV 13 I Output of the drive regulator and power supply pin for the G2 driver. VDRV is also the supply voltage for the internal logic and control circuitry. VEA− 7 I Inverting input of the voltage error amplifier used for output voltage regulation. (1) REF is an input in Mode 3 only. 8 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION The UCC2541 is a high-efficiency synchronous buck controller that can be used in many point-of-load applications. CEA− and VEA− pins: Current Limit and Hiccup Mode Typical power supply load voltage versus load current is shown in Figure 2. This figure shows steady state operation for no-load to overcurrent shutdown (soft-start retry is not depicted in the diagram). During the voltage regulation conditions, the voltage error amplifier output is lower than the current error amplifier, allowing the voltage error amplifier to control operation. During the current limit conditions, the current error amplifier output is lower than the voltage error amplifier, allowing the current error amplifier to control operation. The boundary between voltage and current control occurs when the difference between CEA− and VEA− tries to exceed 50 mV. VLOAD − Load Voltage − V Current limiting begins to occur when the difference between CEA− and VEA− exceeds 50 mV. For currents that exceed this operating condition, the UCC2541 controls the converter to operate as a pure current source until the output voltage falls to half of its rated steady state level. Then the UCC2541 sets both G1 and G2 outputs to LOW and it latches a fault that discharges the soft-start voltage at 30% of its charging rate. The UCC2541 inhibits a retry until the soft-start voltage falls below 0.5 V. A functional diagram of the voltage and current error amplifiers is shown in Figure 3. VREG Limited Current Shutdown ILOAD − Load Current − A UDG−04053 Figure 2. Typical Power Supply Load Voltage vs Current www.ti.com 9 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION From Power MOSFET Switch Node RS RLOAD C RI1 0.7 V + + + + SS 1.5 R Voltage Error Amplifier TR RV1 R 1.5 V 1.5 V + VEA− 7 VERR to Modulator Inverting Amplifier 50 mV + CEA− COMP + 9 8 Current Error Amplifier ZFV RFV UCC2541 CFV ZFV ZIV CST RI2 RFI CFI CFIR RV2 ZIV Figure 3. Error Amplifier Configuration Component selection includes setting the voltage regulation threshold, then the current limit threshold, as described below. Voltage vs. Current Programming (refer to Figure 3): 1. Determine the ratio V LOAD(reg) V LOAD(reg) R V1 + *1V+ *1V R V2 V VEA* ) Threshold Voltage 1.5 V (typ) ǒ 2. Sense resistor R S + 1 ) Ǔ R V1 R V2 V CEA)offset voltage , where IS(max) is the current limit level, I S(max) VCEA+offset = 50 mV (typ). 3. Arbitrarily select either RV1 or RV2 so that the smallest of the two resistors is between 6.5 kΩ and 20 kΩ. Then calculate the value of the other resistor using the equation in the first step. If the converter is in a current-limit condition and the output voltage falls below half of the regulated output voltage, the UCC2541 enters into a hiccup (restart-retry) mode. Figure 4 shows typical signals during hiccup mode. 10 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION SYNCIN 3.3 V SS 0.5 V ILOAD VLOAD RAMP G2C G1 G2 UDG−04046 Figure 4. Typical Hiccup Mode waveforms COMP, VEA− and CEA− pins: Voltage and Current Error Amplifiers From no-load to full rated load operating conditions, the UCC2541 operates as a voltage mode controller. Above the programmed rated current, there are two levels of over current protection; constant current limit and overcurrent reset/retry. This section gives suggestions on how to design the voltage controller and current controller so that they interact with one another in a stable fashion. Refer to the functional diagram of the voltage and current error amplifiers in Figure 3. The voltage error amplifier in the figure shows three non-inverting inputs. The lowest of the three non-inverting inputs (1.5 V, SS and TR) is summed with the inverting input to achieve the voltage error signal. The lowest of the two outputs drives the inverting stage which in turn, drives the modulator. During steady state voltage control operation, the feedback elements in the current loop have no effect on the loop stability. When current limit occurs, the voltage error amplifier effectively shuts OFF and the current error amplifier takes control. During steady state current limit operation, the negative feedback elements in the voltage error amplifier loop become positive feedback elements in the current error amplifier loop. In order for the current error amplifier to be stable, the impedances in the feedback path of the current error amplifier must be lower than the impedances in the feedback path of the voltage error amplifier. This means that resistors in the current error amplifier negative feedback path must be less than the resistors in the voltage error amplifier negative feedback path. Also capacitors in the current error amplifier negative feedback path must be larger than capacitors in the negative feedback path of the voltage error amplifier negative feedback path. (Capacitance is really an admittance value rather than an impedance value). This concept is illustrated in Figure 3. In order for the current loop to be stable in Figure 3, ||ZIV|| must be less than ||ZFV|| over all frequencies. This can be achieved if RFI < RFV and CFI > CFV. www.ti.com 11 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION Another issue that can occur during current limit operation is modulator stability. In order for the modulator to be stable, the rising slope of the current ripple measured at the COMP pin must be smaller than the rising slope that is measured at the RAMP pin. This can be met either in the selection of the ratio of ||ZIV|| to ||ZFV||, or by the addition of a capacitor in parallel to RFI and CFI, such as CFIR, in Figure 3. In some applications, this current and voltage error amplifier configuration may lead to difficulties with startup at turn on and with restarting after current limit hiccup operation. A small capacitor from CEA− to ground can filter this node to alleviate this issue. This capacitor is shown as CST in Figure 3. Stable Dynamic Current Loop Design (refer to Figure 3): 1. Using any favorite approach, design the voltage error amplifier for stable voltage mode design. Use at least 15 kΩ for any resistors in the negative feedback path of the voltage error amplifier (between pins 9 and 7). This does not apply to resistance values between the power supply output voltage and pin 7; it also does not apply to resistance values between ground and pin 7. 2. The goal is to design the current limit control loop so that it drives the converter to maintain 50 mV between the VEA− pin and the CEA− pin during current-limit conditions. Select the current sense element and the voltage divider ratios for the VEA− pin to ground and the CEA− pin to ground to provide the desired current limit level. 3. Place the same configuration of components in the negative feedback path of the current error amplifier (between pins 9 and 8), that are in the negative feedback path of the voltage error amplifier (between pins 9 and 7). However, use resistors with values that are 67% of the corresponding resistors that are between pins 9 and 7 and use capacitors that are 150% of the corresponding capacitors that are between pin 9 and pin 7. 4. Check the COMP signal. If it is unstable, place a capacitor (or increase the capacitance) between pins 9 and 8 in order to attenuate the current ripple. Raise the value of the capacitor until the COMP pin voltage becomes stable. Compare the COMP voltage with the RAMP voltage. With stable operation, the rising slope of the COMP voltage ripple is less than the rising slope of the RAMP pin. 12 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION RSET, RAMP, G2C, SS pins: Programming the Timer Currents Set the base current to the timers with a resistor between RSET and GND. The block diagram of the UCC2541 shows the interaction of the RSET pin and the dependent current sources for the RAMP, G2C and SS features. The RSET pin is a voltage source; the current of the RSET pin is reflected and multiplied by a gain and distributed to the RAMP (gain = 2), G2C (gain = 2) and SS (charge gain = 1.33, net discharge gain = 0.4). The resistance applied to the RSET pin and GND should be in the range of 10 kΩ < RRSET < 50 kΩ. RAMP, G2C and SS timers are programmed by the selection of capacitors tied between each of their respective pins and GND. G2C pin: G2 Timer for Output Stage Reverse Current Protection G2C 2 y IRSET 2.5 V G2 Timeout Comparator *G1D + G2C Latch S Q RD Q 3 CG2C G2TO UVLO GLO G2 *G1 with delay, but not blanked UDG−04047 Figure 5. Functional diagram of the G2 Timer The G2C pin programs the maximum duration of the synchronous rectifier to facilitate low or zero duty ratio operation. Figure 5 shows the functional diagram. This function is programmed by connecting a capacitor between the G2C pin and GND. The capacitor on G2C should be slightly larger than the capacitor on the RAMP pin. For best results, program the typical G2 time limit to be between 1.5 and 3 times the switching period (T). Notice that when the G2 timer reaches its limit, both G1 and G2 are forced to a LOW output. This feature prevents the current in the output inductor from excessive negative excursions during zero-duty ratio conditions. Program the G2 time-out (G2TO) duration using equation (1): C G2C + 2 V RSET R RSET G2 Timeout Duration , Farads G2C Timer Threshold (1) where D VRSET = 1.5 V(typ) D 1.5 T < G2 Timeout Duration < 3TS D G2C Timer Threshold = 2.5 V (typ) www.ti.com 13 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION RAMP pin: Oscillator and PWM Ramp The RAMP pin serves two purposes: (1) a capacitor on this pin sets the oscillator charging time to program the frequency of operation for the converter and (2) the peak voltage on RAMP defines the gain of the PWM modulator. The UCC2541 has a leading edge modulator that compares the error output with the RAMP voltage. A diagram of the oscillator and PWM modulator is shown in Figure 6. The current charging the capacitor from RAMP to ground is equal to 2 x IRSET. In the UCC2541, with leading edge modulation, a switching cycle can be considered to begin when the oscillator ramp reaches 2.0 V. This voltage level triggers the negative-going clock signal which enables the RAMP discharge transistor and simultaneously sends a G1 turn-off command to the PWM control. The internal clock signal is held low for approximately 100 ns, and this sets the maximum desired value for the capacitor on the RAMP pin. Note that the RAMP discharge transistor must also sink 2 x IRSET while it is discharging the external RAMP capacitor. PWM COMPARATOR PWM LATCH VERR 0.25V − S Q + + RD Q OSC RAMP COMPARATOR + − 2.0 V 2 y IRSET RAMP 5 ENA PWM CLK GEN CLK 4 SYNCIN Figure 6. Oscillator and PWM Modulator The oscillator frequency is programmed by proper selection of the resistor connected to RSET (pin 1) and the capacitor connected to RAMP (pin 5). With RSET selected within the preferred range of 10 kΩ to 50 kΩ the RAMP capacitor CRAMP can be selected from: ǒ 1.5 C RAMP + Ǔ 1 * 100 ns fSW R SET (2) where fsw is the desired switching frequency, and RSET is the resistor connected to pin 1. This expression is derived by summing the time required for a linear current source to change the RAMP capaitor with the internal delay of approximately 100 ns. The constant term 1.5 is equal to: ǒ 14 I RAMP I RSET Ǔǒ Ǔ V RSET V RAMP(pk) (3) www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION The UCC2541 can be synchronized to an external source if an external SYNCIN signal (falling edge) is applied to pin 4 before the oscillator reaches 2.0 V. The internal circuitry uses the falling edge on SYNCIN to generate the 100-ns internal clock signal and turn off G1. The free-running frequency programmed by the internal oscillator/RAMP capacitor should be approximately 20% lower than an intended external sync frequency. The SYNCIN pin should be tied to VREF if not used. OSCILLATOR FREQUENCY vs TIMING RESISTOR 900 fSW − Oscillator Frequency − kHz 800 700 150 pF 600 500 270 pF 400 300 390 pF 200 100 680 pF 0 10 20 30 40 50 VVDD − Timing Resistor − kΩ Figure 7 VDD, VDRV, VREF and BST pins: Modes of Operation Depending on the available bias voltage for the UCC2541, the startup, shutdown, and restart conditions are different. There are three distinct configurations or modes of biasing the UCC2541. The mode is detected and latched into an internal register during power-up when VREF crosses 2 V. The register is cleared when VDD, VDRV and VREF are simultaneously less than 1 V. A summary of the modes and their programming requirements are listed in Table 1. Table 1. Modes and Programming Requirements Mode VBIAS Range (V) Bias Pin UVLO ON (V) UVLO OFF (V) 1 8.5 to 36 VDD [16] VVDD = 8.5 VVDD = 8.0 2 4.75 to 8.5 VDRV [13] VVDRV = 4.65 3 3.0 to 3.6 VREF [2] VREF = 2.8 Mode Requirement at Power-Up and VVREF = 2 V V VDD u ǒV VDRV and V REFǓ Remarks Widest line operation VVDRV = 4.3 V VDRV u ǒV VDD and V REFǓ VREF= 2.5 www.ti.com V REF u ǒV VDD and V VDRVǓ Needs regulated bias and low VTH power MOSFETs 15 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION VDD, VDRV, VREF and BST pins: Modes of Operation (cont.) D Mode 1, or normal operation requires the availability of a bias of 8.5 V or higher for the device. Here, the bias drives the VDD pin. The low-side drive bias, VVDRV = 7 V, is generated from an internal linear regulator and it directly draws current from the VDD pin. The high-side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin, when G2 is HI, via a diode between G2 and BST. The UCC2541 operates in Mode 1 if VVDD > (VVDRV and VVREF) when VVREF rises above 2 V. Mode 1 permits the widest range of bias voltages, operational from 8.5 V < VVDD < 35 V. This mode is compatible with systems that have a 12 VDC bias supply already available. D Mode 2 is suitable for applications where the bias is typically 5 V (between 4.5 V and 8.0 V). The bias voltage is applied to the VDRV terminal of the UCC2541. The high-side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin, when G2 is HI. Bias voltage to the VDD pin is obtained through an external voltage-doubler charge pump. If the system uses low threshold voltage power MOSFETs, VDD can be directly tied to the VDRV pin. The bias voltage could be either a bus converter output or an auxiliary supply. D Mode 3 is for synchronous buck converter applications where the bias voltage is a regulated 3.3-V source. This is a common main output voltage in multiple output power converters. The bias voltage is applied to the VREF pin of the UCC2541. The UCC2541 operates in Mode 3 if it detects (VVREF > VVDRV and VDD) when VVREF rises above 2 V. Assorted combinations of modes and biasing schemes are shown in Figure 7 through Figure 12. In Mode 1 and Mode 2, the bias voltage can either be an independent auxiliary supply or it can be supplied by the power stage voltage, as shown in Figure 7 through Figure 11. A regulated auxiliary supply must be used with Mode 3 because the tolerance of the VREF voltage is the control tolerance of the UCC2541. In Mode 3, the regulated auxiliary supply can be independent of the power supply input voltage (as shown in Figure 12), or the regulated auxiliary supply can be the same source as the power supply input voltage. 16 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION UCC2541 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High−Side Driver SWS SW Predictive Logic G2 Low−Side Driver G2S PGND 8.5 V ≤ VVDD ≤ 35 V 16 13 2 19 C2 C3 C4 Q1 18 C1 20 D1 17 Q2 14 12 UDG−04038 15 Figure 8. Mode 1 With Combined Power/Bias for Input Voltages Between 8.5 V and 35 V UCC2541 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High−Side Driver SWS SW Predictive Logic G2 Low−Side Driver G2S PGND AUX Bias 8.5 V ≤ VVDD ≤ 35 V 16 13 0 V ≤ VIN ≤ 35 V 2 19 C2 C3 C4 Q1 18 C1 20 D1 17 Q2 14 12 15 UDG−04039 Figure 9. Mode 1 With Separate Power/ Bias Voltages Between 8.5 V and 35 V www.ti.com 17 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION UCC2541 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High−Side Driver SWS SW Predictive Logic G2 Low−Side Driver G2S PGND Bias and Power 4.75 V ≤ VVDRV ≤ 8.0 V D2 16 D4 13 D3 2 19 C2 C3 C4 C5 Q1 18 C1 20 D1 17 Q2 14 12 15 UDG−04040 Figure 10. Mode 2 With Common Bias and Power Input Voltages Between 4.75 V and 8.0 V UCC2541 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High−Side Driver SWS SW Predictive Logic G2 Low−Side Driver G2S PGND AUX Bias 4.75 V ≤ VVDRV ≤ 8.0 V D2 16 D4 13 D3 2 0 V ≤ VIN ≤ 35 V 19 C2 C3 C4 C5 Q1 18 C1 20 17 D1 Q2 14 12 15 UDG−04041 Figure 11. Mode 2 With Separate Power/ Bias (4.75 V and 8.0 V) 18 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION UCC2541 Drive (7.2 V) Regulator AUX Bias 4.75 V ≤ VVDRV ≤ 8.0 V VDD 16 VDRV VREF (3.3 V) Regulator 13 VREF BST 19 G1 High−Side Driver C3 C4 Q1 (Low VTH) C1 SWS 20 D1 17 G2 Low−Side Driver C2 18 SW Predictive Logic 0 V ≤ VIN ≤ 35 V 2 Q2 (Low VTH) 14 G2S 12 PGND 15 UDG−04042 Figure 12. Mode 2 With Auxiliary Biasing for Bias Voltages Between 4.75 V and 8.0 V and Logic Level or Low Threshold Power MOSFET Transistors UCC2541 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High−Side Driver SWS SW Predictive Logic G2 Low−Side Driver G2S PGND D2 16 D3 Regulated 3.3-VDC Bias DC or Pulse Train 13 1.8 V ≤ VIN ≤ 5 V 2 19 C2 C4 C5 Q1 (Low VTH) 18 C1 20 17 D1 Q2 (Low VTH) 14 12 15 UDG−04043 Figure 13. Mode 3 With Regulated 3.3-VDC Bias, Low Threshold Power MOSFETs www.ti.com 19 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION Figure 14 illustrates a combined operational mode (referred to as Mode 4) which allows a converter operating from intermediate bus voltages ranging from 6 V to >14 V to safely cross the boundary between Mode 1 and Mode 2 operation. A simple circuit utilizing an NPN transistor, zener diode, and resistor allows the circuit to start under the control of Mode 2 UVLO thresholds. Once the power stage is operational VDD is pumped up by D2 and D3 and the internal VDRV regulator raises VDRV to 7.2 V, shutting off the NPN transitor. The zener clamp on the NPN base prevents VDRV voltage rating from being exceeded during 12-V startup. It should be noted the circuit will run down to input voltages below 3.5 V, shutting off when VDRV has fallen to its turn-off threshold of 4.3 V. D2 D3 6.2V 5k UCC2541 1 RSET 2 REF 3 G2C SWS 20 BST 19 G1 18 4 SYNCIN SW 17 5 RAMP VDD 16 6 GND PGND 15 7 VEA− 8 CEA− VDRV 13 9 COMP G2S 12 10 TR G2 SS VIN = 6−14V D1 VOUT 14 11 Figure 14. Mode 4 Operation 20 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION Charge Pump Capacitor Selection Capacitors C1 through C5 are all part of a charge distribution network that allows the UCC2541 to pass charge to the MOSFET gates of Q1 and Q2 (all reference designators in this section refer to the schematics in Figure 8 through Figure 13). This section gives guidelines on selecting the values of C1 through C5 so that the converter functions properly. Specific capacitor values may need to be larger than the recommended value due to MOSFET characteristics, diode D1 – D4 characteristics and closed-loop converter performance. All three modes of operation require a charge pump capacitor and diode, C1 and D1, in order to drive the high-side power MOSFET. Modes 2 and 3 require additional charge pump capacitors and diodes in order to supply voltage to VDD. In general, all charge pump diodes should be Schottky diodes in order to have low forward voltage and high speed. The charge pump capacitors should be ceramic capacitors with low effective series resistance (ESR), such as X5R or X7R capacitors. The value of the charge pump capacitor C1 depends on the power MOSFET gate charge and capacitance, the voltage level of the Miller plateau threshold, the forward drop of D1 and the closed-loop response time. The unloaded high-side gate driver typically draws 2 nC of charge per rising edge plus 30 µA of direct current from C1. Usually, the unloaded high−side gate driver load is miniscule compared to the gate charge requirements of the high-side power MOSFET, Q1. Typical values for C1 are approximately 50 to 100 times the input capacitance (CISS) of MOSFET Q1. This usually allows for transient operation at extremely large duty ratio, where C1 does not have sufficient time to fully recharge. If C1 is excessively large, its ESR and ESL prevents it from recharging during transients, including the start-up transient. Capacitors C2 through C5 are then selected based on the direction of charge transfer and the requirements of the UCC2541. Selection guidelines are shown in Table 2. Keep in mind that each converter design may require adjustments for larger capacitor ratios than those that are suggested in Table 2. The selection process begins at the left side of Table 2 and progresses towards the right side of the table, which is the reverse order of the charge flow during the first few cycles of start-up. If iteration is required in the design process, review the progression of the capacitors in the order from left to right that is shown in the table. Table 2. Charge Pump and Bias Capacitor Selection Guidelines Mode High-Side Drive Capacitor (≥ 0.1 µF) VDRV Filter Capacitor VREF Filter Capacitor VDD Filter Capacitor VDD Charging Capacitor 1 C1 > 50 CISS C3 > 2 × C1 C2 > 0.1 µF C4 > 1 µF n/a 2 C1 > 50 CISS C3 > 2 × C1 C2 > 0.1 µF C4 > 1 µF, 2 × C3 C5 > 2 × C4 C1 > 50 CISS C4 > 1 µF 2 × C1 C2 > 1.0 µF C4 > 1 µF, 2 × C1 C5 > 2 × C4 3 For Modes 2 and 3, the VDD filter capacitor, C4, in Table 2 must supply the IVDD idle current to the UCC2541 (approximately 11 mA) plus the charge to drive the gates G1 and G2. Capacitor C4 must be large enough to sustain adequate operating voltages during start-ups and other transients under the full operational IVDD current. Knowing the operating frequency and the MOSFET gate charges (QG), the average IVDD current can be estimated as: I VDD + I VDD(idle) ) ǒQ G1 ) Q G2Ǔ fS (4) D where fS is switching frequency In order to prevent noise problems, C4 must be at least 1 µF. Furthermore, it needs to be large enough to pass charge along to the power MOSFET gates. Thus C4 often needs to have at least twice the capacitance of the VDRV filter capacitor, as shown in Table 2. www.ti.com 21 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION Output Stage The UCC2541 includes dual gate drive outputs and each is capable of ±3-A peak current. The pull-up/ pull-down circuits of the driver are bipolar and MOSFET transistors in parallel. High-side and low-side dual drivers provide a true 3-A high-current capability at the MOSFET’s Miller Plateau switching region where it is most needed. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. The output drivers can switch from VDD to GND. Each output stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external-schottky-clamp diodes are not required. The outputs are also designed to withstand 500-mA reverse current without either damage to the device or logic upset. For additional information on drive current requirements at MOSFET’s Miller plateau region, refer to the Power Supply Seminar SEM−1400 [3]. Predictive Gate DriveTM Technology The Predictive Gate Drive technology maximizes efficiency by minimizing body diode conduction. It utilizes a digital feedback system to detect body diode conduction, and adjusts the deadtime delays to minimize the conduction time interval. This closed loop system virtually eliminates body diode conduction while adjusting for different MOSFETs, temperature, and load dependent delays. Since the power dissipation is minimized, a higher switching frequency can be utilized, allowing for a smaller component size. Precise gate timing at the nanosecond level reduces the reverse recovery time of the synchronous rectifier MOSFET body diode, which reduces reverse recovery losses seen in the main (high-side) MOSFET. Finally, the lower power dissipation results in increased reliability. 19 BST 18 G1 17 SW Predictive Logic 20 SWS 12 G2S VDRV 14 G2 15 PGND UDG−02149 Figure 15. For additional information on Predictive Gate Drive control and efficiency comparisons to earlier adaptive delay and adaptive control techniques, refer to the Application Note SLUA285 [1]. 22 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION VDD and IDD Although quiescent VDD current is low, total supply current is higher, depending on output gate drive requirements and the programmed oscillator frequency. Total VDD current (IVDD) is the sum of quiescent VDD current and the average output currents of G1 and G2, as described in equation (5). Knowing the operating frequency and the MOSFET gate charge (QG), average driver output current, per gate, can be calculated from: IG + QG fS (5) where D fS is switching frequency To prevent noise problems, connect a 1-µF ceramic capacitor between the VDD and GND pins. Place the 1-µF ceramic capacitor as close to the UCC2541 as possible. This capacitor is in addition to any electrolytic energy storage capacitors that may be used in the bias supply design. Soft-Start and Tracking Features Separate pins are provided for the soft-start feature and the tracking feature. Soft-start or tracking (sequencing) can be easily implemented with this configuration using a minimum number of external components. During a power-up transient, the converter output tracks the lower of the SS voltage, the TR voltage or a 1.5-V internal reference, provided the system is not in current limit. In other words, the voltage control loop is closed during power-up, provided the system is not current limited. Figure 16 shows the UCC2541 configured for soft-start operation. For applications that do not use the tracking feature, connect the TR pin to either SS or REF, as shown in the figure. Remote shutdown and sequential power-up can be easily implemented as a transistor switch across CSS. TR UCC2541 10 REF (3.3 V) Voltage 1.33 y IRSET SS Error 0.7 V + 11 1.5 V + + + Amplifier COMP CSS 1.73 y IRSET UVLO VEA− HUP 50 mV + 7 To Positive Input of Current Error Amplifier UDG−04045 Figure 16. Using the Soft-Start Feature www.ti.com 23 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION The soft-start interval begins when the UCC2541 recognizes that the appropriate voltage (see Mode 1, 2 or 3) is above the UVLO level. The voltage of CSS then linearly increases until it is clamped at the REF voltage of 3.3V. Regulation should be reached when the soft-start voltage reaches about 2.2 V (1.5 V plus a diode drop). Select a CSS capacitor value using equation (5) to program a desired soft-start duration, ∆tSS. V RSET R SET C SS + 1.33 Dt SS + 1.33 DV SS Dt SS Farads 2.2 V 1.5 V R SET (6) If a UVLO fault is encountered, both outputs of the UCC2541 are disabled and the soft-start pin (SS) is discharged to GND. The UCC2541 does not retry until the UVLO fault is cleared. Using the TR pin, the UCC2541 can be programmed to track another converter output voltage. If the voltage to be tracked is between 0 V and 3.3 V, simply connect the TR pin to the voltage to be tracked with a resistor that is approximately equal to the DC impedance that is connected to the VEA− terminal (RV1 || RV2, in Figure 3). If the voltage is above that range, use a voltage divider, again with an equivalent resistance that approximately equals the DC impedance that is connected to the VEA− terminal. Other strategies can be used to achieve sequential, ratiometric or simultaneous power supply tracking[4]. An implementation of sequential sequencing using TPS3103K33[2] in a multiple output power supply[4] is shown in Figure 17. Applications where the loads include a processor with a core voltage of 1.5 V and I/O ports that require 3.3 V can require sequential sequencing in order to resolve system level bus contention problems during start-up. In this circumstance the core must power-up first, then after an initialization period of 130 ms, the ports are allowed to power-up. This is illustrated in Figure 18. From dc Power Source UCC2541 TPS3103K33 TR G1 SS G2 I/O 3.3 V RESET VDD CSS GND PFO 1.6 kΩ MR PFI 1 kΩ UCC2541 10 kΩ REF TR G1 Core 1.5 V G2 SS CSS UDG−04061 Figure 17. Sequencing a Multiple Output Post Regulated Power Supply 24 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION Regulation loss due to loss of primary line voltage V − Voltage − V 130 ms 3.3 1.5 1.43 VI/O VCORE 0 t − Time UDG−04061 Figure 18. Using the TR pin, the UCC2541 can be programmed to ratio-metrically track another converter output voltage[4]. Ratio-metric tracking is when the ratio of the output voltages is constant from zero volts to the point where one or more of the outputs lock into regulation. The TR pin is easier to use for tracking than the SS pin because the external currents that would be applied to the SS pin may interfere with SS discharge currents and fault recovery. It should be understood that the voltage that is being tracked must lag the bias voltages (VDD, VDRV and REF) on start-up and lead the bias voltages during shutdown. Furthermore, the output that is being tracked must not reach its steady state DC level before the output that is tracking reaches its steady state DC level. Figure 18 illustrates the concept of programming an output voltage VC, to ratio-metrically track another output, VM. VM (Leader) Main Power Supply (Leader) + MM VC (Tracker) VM (a) ratio−metric sequencing MC VM (Leader) MM Core Power Supply (Trader) VC UCC2541 7 + MC TR VC (Tracker) VM (Leader) Tracking Ratio AT ^ ǒ Ǔ MC MM MM VC (Tracker) MC (b) simultaneous sequencing (c) ratio−metric sequencing UDG−04061 Figure 19. Ratio−Metric Tracking www.ti.com 25 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION The general circuit to program the UCC2541 to track the leader supply voltage by the tracking ratio AT is shown in Figure 20. To program the tracking profile gains GT1 and GT2, follow the ratio-metric tracking design procedure that is listed below. The special case of simultaneous sequencing for VM > 1.5V is the simplest to design; set RT1= RV1 and RT2= RV2, GT2 is not needed. In many other cases, the circuit can be simplified with the removal of the operational amplifier for GT2 and the Zener clamping diode. If an operational amplifier is necessary, it should be capable of rail to rail operation and usually low voltage bias; the TLV271 is an inexpensive solution for both of those requirements. Notice that the tracking circuit in Figure 20 also has a soft-start capacitor, CSS. The soft-start capacitor is useful for limiting the time between short-circuit retry attempts and it can prevent overshoot when recovering from a fault that is experienced in only the tracking supply but not the main supply. Ratio-Metric Tracking Design Procedure (see Figures 22 and 23) 1. Determine the tracking ratio, AT. AT + MC MM (7) where MC and MM are the soft-start slopes of VC and VM, respectively. 2. Determine GV. GV + R V2 R V1 ) R V2 (8) where RV2 and RV1are selected when designing the voltage control loop. 3. Test GT2 if necessary when VM ≤ 1.5 V or ATGV > 1. a. If GT2 is needed, set GT2 so that both equations (8) and (9) apply. G T2 + 1 ) R F1 R F2 (9) so that both of the following apply: G T2 + ǒ Ǔ 1.5 V V M G T1 and G T2 u ǒA T G VǓ (10) b. If GT2 is not needed, set GT2 = 1. 4. Set GT1 . G T1 + AT GV R T2 + R T1 ) R T2 G T2 (11) 5. Select RT1 and RT2 so that RT1 || RT2 ≈ RV1 || RV2 to minimize offset differences. 26 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION RF2 TLV271 RF1 G T2 + 1 ) R F1 R F2 Main Power Supply (Leader) Use GT2 stage if ATGV > 1 OR if VMGT1 ≤ 1.5 V at steady-state + + VM Rectified Secondary Voltage TR RT2 G T1 + R T2 R T1 ) R T2 nVIN UCC2541 RT1 0V G1 + *DZ 3.3 V SS VC G2 CSS VEA− RV1 RV2 *DZ needed only if VMGT1GT2 > 3 V GV + R V2 R V1 ) R V2 Determined by voltage loop design UDG−04059 Figure 20. Programming the UCC2541 to Track Another Output More elaborate power supply sequencing and tracking can easily be implemented by extending the above techniques. Consult Reference [4] for further information. The following schematic shows an example POL (point of load) converter capable of delivering 20 A at 2.5 V from an unregulated IBC (intermediate bus converter) providing 9 V to14 V. In this application, the UCC2541 is configured to operate in Mode 1, and the converter turns ON when the UCC2541 UVLO threshold of 8.5 V is exceeded. The upper input voltage rating is limited by the MOSFET and capacitor voltage ratings, not the UCC2541. For lower current requirements from 10 A to15 A a single lower MOSFET would suffice. www.ti.com 27 28 www.ti.com Figure 21. 20-A POL (Point of Load) Converter 8.2k 15k 26.7k 1nF 6.8nF 3.3nF 270pF 470pF 680pF 0.1uF 26.7k 10k COMP TR 10 CEA− SS G2S VDRV G2 PGND GND VEA− VDD RAMP SW G1 BST UCC2541 SWS SYNCIN G2C REF RSET 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 0.18uF 17.8k HAT2165H Q2: 2 x 2.2uH IC through PowerPAD GND and PGND tied together under 0.22uF 0.39uF 1uF 1N5819 Q1: HAT2168H 22uF 17.8k 0.0032 22uF 2.2nF 787 2 x 330uF POSCAP VOUT=2.5V VIN=9−14V
 SLUS621A − AUGUST 2004 − SEPTEMBER 2005  APPLICATION INFORMATION 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 APPLICATION INFORMATION In the 20-A converter the output current is sensed by R4. The UCC2541 limits output current when the CEA− (pin 8) exceeds the VEA− (pin 7) by 50 mV. To select the current sense resistor the 50-mV signal must be gained up by the reciprocal of the output feedback divider ratio given by: R8 R12 + R12 ) R10 R8 ) R9 (12) For this 2.5-V output, the divider ratio is 0.6, and the following calculation can determine the typical voltage across the sense resistor to begin current limit operation: V RSNS + V R4 + 1 0.6 50 mV + 83.3 mV (13) The peak inductor ripple current should also be considered in RSNS selection, and is 1/2 the peak-to-peak inductor current calculated during the OFF-time of the converter: ǒ Ǔ VO dI PP 1 * f S V IN f S VO + 3 A PP L (14) with VO=2.5 V, VIN=12 V, fS=300 kHz, and L1=2.2 µH. In this design IL1, peak =21.5 A. For a 20-A converter with current limiting at 20% overload the sense resistor can be calculated as: R SNS + V RSNS + 83.3 mV + 3.2 mW 1.2 21.5 A 1.2 IL PEAK (15) With this value of sense resistor the average power dissipation can be calculated to be: P RSNS + I OUT 2 R SNS + 20 A 2 3.2 mW + 1.28 W (16) Low value current sense resistors are commonly available in 1-W surface mount packages, so two packages should be paralleled to meet the power dissipation requirements in high current designs, and the final value used will be a compromise of available components. In surface mount applications a Kelvin connection to the sense resistor is not easily attainable, so the connection resistance from the sense resistors to the PCB must be included in the effective sense resistance. The voltage and current feedback component magnitudes were ratioed according to the discussion in section, COMP, VEA− AND CEA− pin: Voltage and Current Error Amplifiers. In this application, the optional component CFIR was not needed. However, a 1-nF capacitor (CST in Figure 3) was needed to filter the CEA− signal to allow the converter to start at turn on and to restart after current limit hiccup operation. www.ti.com 29 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 THERMAL INFORMATION The useful temperature range of a controller that contains high-current output drivers is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC2541 is available in the 20-pin HTSSOP PowerPADt package and also the 32-pin QFN PowerPADTM package. The PowerPADTM offers the most effective means of removing the heat from the semiconductor junction and therefore long term reliability improvement. As illustrated in [5], the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the device package, reducing the θjc down to 2°C/W. Data is presented in [5] to show that the power dissipation can be quadrupled in the PowerPADt configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in [6] to realize a significant improvement in heat−sinking over standard non-PowerPADt surface mount packages. TYPICAL CHARACTERISTICS RAMP CURRENT vs TEMPERATURE OUTPUT REFERENCE VOLTAGE vs TEMPERATURE −275 3.40 −285 IRAMP − Ramp Current − µA VVREF − Reference Voltage − V RRSET = 10 kΩ 3.35 3.30 3.25 −295 −305 −315 3.20 −50 0 50 100 150 −325 −50 50 100 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 22 30 0 Figure 23 www.ti.com 150 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 TYPICAL CHARACTERISTICS IG2C/IRAMP AND ISS/IRAMP vs TEMPERATURE 1.1 7.6 MODE 1 VVDRV − Regulator Output Voltage − V IG2C/IRAMP, RRSET =10kΩ 1.0 IG2C/IRAMP, RRSET =50kΩ µA/µA 0.9 0.8 ISS/IRAMP, RRSET = 10kΩ 0.7 ISS/IRAMP, RRSET = 50kΩ 0.6 0.5 −50 0 50 100 TJ − Junction Temperature − °C REGULATOR OUTPUT VOLTAGE vs TEMPERATURE 7.4 7.2 7.0 6.8 −50 150 0 Figure 24 fSW − Oscillator Frequency − kHz VCEA− − Current Error Amplifier Offset Voltage − mV 600 C = 450 pF 500 450 400 350 C = 270 pF 300 250 200 −50 0 50 100 TJ − Junction Temperature − °C 100 150 Figure 25 OSCILLATOR FREQUENCY vs TEMPERATURE 550 50 TJ − Junction Temperature − °C 150 55 CURRENT ERROR AMPLIFIER OFFSET vs TEMPERATURE 53 51 49 47 45 −50 0 50 100 150 TJ − Junction Temperature − °C Figure 26 Figure 27 www.ti.com 31 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 TYPICAL CHARACTERISTICS SYNCIN THRESHOLD VOLTAGE vs TEMPERATURE 1.70 1.65 1.60 0 −45 Phase −90 Gain −10 −135 −15 −180 −20 −225 1.55 −25 1k 0 50 100 TJ − Junction Temperature − °C 10 k 100 k 150 1M 10 M −270 100 M f − Frequency − Hz Figure 28 Figure 29 CURRENT ERROR AMPLIFIER GAIN AND PHASE vs FREQUENCY VOLTAGE ERROR AMPLIFIER GAIN AND PHASE vs FREQUENCY 120 0 120 0 100 100 Gain 80 −90 40 20 Phase − ° 60 Gain − dB −45 Phase −135 0 −45 60 −90 40 Phase − ° Gain 80 Gain − dB 0 −5 1.50 −50 Phase 20 0 −135 −20 −20 −40 1 32 5 Phase − ° 1.75 Gain − dB VSYNCHIN − Timing Signal Voltage − V 1.80 INVERTING AMPLIFIER GAIN AND PHASE vs FREQUENCY 10 100 1k −180 10 k 100 k 1 M 10 M 100 M −40 1 10 100 1k −180 10 k 100 k 1 M 10 M 100 M f − Frequency − Hz f − Frequency − Hz Figure 30 Figure 31 www.ti.com 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 TYPICAL CHARACTERISTICS OPERATING CURRENT (DC) vs BIAS VOLTAGE 12 IVDD − Bias Current − mA 10 8 6 5.0 V/div. 4 5.0 V/div. 2 0 0 5 10 15 20 25 30 VVDD − Bias Voltage − V Figure 32 35 40 t − Time − 20 ns/div Figure 33. Predictive Gate Drive − G2 Falling www.ti.com 33 
  SLUS621A − AUGUST 2004 − SEPTEMBER 2005 RELATED PRODUCTS D UCC27223 High Efficiency Predictive Synchronous Buck Driver with Enable D UCC2540 High-Efficiency Secondary-Side Synchronous Buck PWM Converter D TPS40070/1 High-Efficiency Midrange Input Synchronous Buck Controller With Voltage Feed-Forward REFERENCES 1. Application Note, Predictive Gate DriveE FAQ, by Steve Mappus (SLUA285) 2. Datasheet, TPS3103K33 Ultra-Low Supply Current/Supply Voltage Supervisory Circuits, (SLVS363) 3. Power Supply Seminar SEM−1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by L. Balogh, (SLUP133) 4. Power Supply Seminar SEM1600 Topic 2: Sequencing Power Supplies in Multiple Voltage Rail Environments, by D. Daniels, D. Gehrke, and M. Segal, (SLUP224) 5. Technical Brief, PowerPAD Thermally Enhanced Package, (SLMA002) 6. Application Brief, PowerPAD Made Easy, (SLMA004) 34 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCC2541PWPR NRND HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 UCC2541 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of