UCC27322QDGNRQ1

Sample & Buy Product Folder Technical Documents Support & Community Tools & Software UCC27321-Q1, UCC27322-Q1 SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 UCC2732x-Q1 Single 9-A High-Speed Low-Side MOSFET Driver With Enable 1 Features 3 Description • • The UCC2732x-Q1 family of high-speed drivers delivers 9 A of peak drive current in an industrystandard pinout. These drivers can drive large MOSFETs for systems requiring extreme Miller current due to high dV/dt transitions. This eliminates additional external circuits and can replace multiple components to reduce space, design complexity, and assembly cost. Two standard logic options are offered, inverting (UCC27321-Q1) and noninverting (UCC27322-Q1). 1 • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 Industry-Standard Pinout With Addition of Enable Function High Peak-Current Drive Capability of ±9 A at the Miller Plateau Region Using TrueDrive™ Technology Efficient Constant-Current Sourcing Using a Unique Bipolar and CMOS Output Stage TTL and CMOS-Compatible Inputs Independent of Supply Voltage 20-ns Typical Rise and 15-ns Typical Fall Times With 10-nF Load Typical Propagation Delay Times of 25 ns With Input Falling and 35 ns With Input Rising 4-V to 15-V Supply Voltage Available in Thermally Enhanced MSOP PowerPAD™ Package TrueDrive Output Architecture Using Bipolar and CMOS Transistors in Parallel Device Information(1) PART NUMBER 2 Applications • • • • • • Using a design that minimizes shoot-through current, the outputs of these devices can provide high gate drive current where it is most needed at the Miller plateau region during the MOSFET switching transition. A unique hybrid-output stage paralleling bipolar and MOSFET transistors (TrueDrive) allows efficient current delivery at low supply voltages. With this drive architecture, UCC2732x-Q1 can be used in industry standard 6-A, 9-A, and many 12-A driver applications. Latch-up and ESD protection circuits are also included. Finally, the UCC2732x-Q1 provides an enable (ENBL) function to better control the operation of the driver applications. ENBL is implemented on pin 3, which was previously left unused in the industry-standard pinout. It is internally pulled up to VDD for active-high logic and can be left open for standard operation. Switch-Mode Power Supplies DC-DC Converters Motor Controllers Line Drivers Class-D Switching Amplifiers Pulse Transformer Driver PACKAGE BODY SIZE (NOM) UCC27321-Q1, UCC27322-Q1 SOIC (8) UCC27322-Q1 MSOP-PowerPAD (8) 4.90 mm × 3.00 mm 6.00 mm × 4.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram INPUT/OUTPUT TABLE VDD 1 8 VDD INVERTING 7 OUT VDD IN 2 NON INVERTING 6 AGND IN OUT 0 0 0 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 OUT R ENBL ENBL INVERTING UCC27321-Q1 ENBL NON INVERTING UCC27322-Q1 3 4 5 PGND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC27321-Q1, UCC27322-Q1 SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 3 4 8.1 8.2 8.3 8.4 8.5 8.6 8.7 4 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 9.1 Overview ................................................................. 11 9.2 Functional Block Diagram ....................................... 11 9.3 Feature Description................................................. 11 9.4 Device Functional Modes........................................ 15 10 Application and Implementation........................ 16 10.1 Application Information.......................................... 16 10.2 Typical Application ................................................ 16 11 Power Supply Recommendations ..................... 19 12 Layout................................................................... 19 12.1 12.2 12.3 12.4 Layout Guidelines ................................................. Layout Example .................................................... Thermal Considerations ........................................ Power Dissipation ................................................. 19 20 20 21 13 Device and Documentation Support ................. 22 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 22 14 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (January 2012) to Revision D Page • Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1 • Changed UCC3732x to UCC2732x-Q1 throughout document............................................................................................... 1 • Deleted Ordering Information table; see POA added at the end of the data sheet ............................................................... 1 • Changed table descriptions for AGND and PGND................................................................................................................. 3 • Updated values in the Thermal Information table to align with JEDEC standards................................................................. 4 • Changed x-axis values from 1, 10, 100 to 0.1, 1, 10 in Rise Time vs Load Capacitance graph ........................................... 7 • Deleted note reference [1] .................................................................................................................................................... 12 Changes from Revision B (January 2011) to Revision C • 2 Page Changed enable impedance maximum from 135 kΩ to 145 kΩ ............................................................................................ 5 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: UCC27321-Q1 UCC27322-Q1 UCC27321-Q1, UCC27322-Q1 www.ti.com SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 5 Description (Continued) In addition to 8-pin SOIC (D) package offerings, the UCC2732x-Q1 also comes in the thermally enhanced but tiny 8-pin MSOP-PowerPAD (DGN) package. The PowerPAD package drastically lowers the thermal resistance to extend the temperature operation range and improve long-term reliability. 6 Device Comparison Table Table 1. Related Products PRODUCT DESCRIPTION PACKAGE UCC2742x-Q1 Dual 4-A low-side drivers with enable MSOP-8 PowerPAD, SOIC-8, PDIP-8 TPS2811-Q1 Dual 2-A low-side drivers with internal regulator TSSOP-8, SOIC-8, PDIP-8 TPS2819-Q1 Single 2-A low-side driver with internal regulator 5-pin SOT-23 TPS2829-Q1 Single 2-A low-side driver 5-pin SOT-23 7 Pin Configuration and Functions D Package 8-Pin SOIC Top View DGN Package 8-Pin MSOP with PowerPAD Top View VDD 1 8 VDD IN 2 7 OUT ENBL 3 6 OUT AGND 4 5 PGND VDD 1 IN 2 8 VDD 7 OUT PowerPAD ENBL 3 6 OUT AGND 4 5 PGND Not to scale Not to scale Pin Functions PIN NAME NO. TYPE DESCRIPTION The AGND and the PGND must be connected by a single thick trace directly under the device. There must be a low ESR, low ESL capacitor of 0.1 µF between VDD (pin 1) and AGND. The power MOSFETs must be placed on the PGND side of the device while the control circuit must be on the AGND side of the device. The control circuit ground must be common with the AGND while the PGND must be common with the source of the power FETs. AGND 4 GND ENBL 3 I Enable input for the driver with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with a pullup resistor for active-high operation. The output state when the device is disabled is low, regardless of the input state. IN 2 I Input signal of the driver, which has logic-compatible threshold and hysteresis. For UCC27321-Q1, IN is inverting, and for UCC37322-Q1, IN is noninverting. 6, 7 O Driver outputs that must be connected together externally. The output stage is capable of providing 9-A peak drive current to the gate of a power MOSFET. 5 GND Common ground for output stage. This ground must be connected very close to the source of the power MOSFET which the driver is driving. Grounds are separated to minimize ringing effects due to output switching di/dt, which can affect the input threshold. There must be a low ESR, low ESL capacitor of 0.1 µF between VDD (pin 8) and PGND. VDD 1, 8 PWR Supply voltage and the power input connections for this device. These pins must be connected together externally. PowerPAD Pad GND PowerPAD on DGN package only. The PowerPAD thermal pad is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate, which is the ground of the device. OUT PGND Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: UCC27321-Q1 UCC27322-Q1 Submit Documentation Feedback 3 UCC27321-Q1, UCC27322-Q1 SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) Supply voltage Output current MIN MAX UNIT –0.3 16 V 0.6 A –5 6 or VDD + 0.3 V 650 mW OUT Input voltage IN, ENBL D package Power dissipation at TA = 25°C DGN package 3 W Operating junction temperature, TJ –55 150 °C Storage temperature, Tstg –65 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal. 8.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) 2000 Charged-device model (CDM), per AEC Q100-011 1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VDD Supply voltage VDD MIN MAX 4.5 15 UNIT V 8.4 Thermal Information THERMAL METRIC (1) (2) (3) UCC2732x-Q1 UCC27322-Q1 D (SOIC) DGN (MSOPPowerPAD) UNIT 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 113 58.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 61.7 45.3 °C/W RθJB Junction-to-board thermal resistance 53.2 34.3 °C/W ψJT Junction-to-top characterization parameter 16 1.7 °C/W ψJB Junction-to-board characterization parameter 52.7 34 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — 11.9 °C/W (1) (2) (3) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. In general, the system designer must attempt to use larger traces on the PCB where possible to spread the heat away from the device more effectively. For information on the PowerPAD package, see PowerPad™ Thermally Enhanced Package and PowerPad™ Made Easy. The PowerPAD thermal pad is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate, which is the ground of the device. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: UCC27321-Q1 UCC27322-Q1 UCC27321-Q1, UCC27322-Q1 www.ti.com SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 8.5 Electrical Characteristics VDD = 4.5 V to 15 V, TJ = TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN IN = Low, ENBL = Low, VDD = 15 V UCC27321-Q1 IN = High, ENBL = Low, VDD = 15 V IDD Static operating current IN = Low, ENBL = High, VDD = 15 V UCC27322-Q1 IN = High, ENBL = High, VDD = 15 V TYP MAX 150 225 440 650 370 550 370 550 150 225 450 650 75 125 675 1000 UNIT µA INPUT (IN) VIH Logic 1 input threshold VIL Logic 0 input threshold 2 0 V ≤ VIN ≤ VDD Input current V –10 Latch-up protection (1) 0 1 V 10 µA 500 mA OUTPUT (OUT) Peak output current (1) (2) VDD = 14 V VOH High-level output voltage VOH = VDD – VOUT, IOUT = –10 mA VOL Low-level output voltage IOUT = 10 mA Output resistance high (3) Output resistance low (3) 9 A 150 300 mV 11 25 mV Ω IOUT = –10 mA, VDD = 14 V 15 25 IOUT = 10 mA, VDD = 14 V 1.1 2.5 Latch-up protection (1) 500 Ω mA ENABLE (ENBL) VEN_H Enable rising threshold voltage Low-to-high transitions 1.5 2.2 2.7 V VEN_L Enable falling threshold voltage High-to-low transition 1.1 1.65 2 V 0.18 0.55 0.9 V 75 Hysteresis R(ENBL) Enable impedance VDD = 14 V, ENBL = Low 100 145 kΩ tD3 Propagation delay time CLOAD = 10 nF (see Figure 2) 60 95 ns tD4 Propagation delay time CLOAD = 10 nF (see Figure 2) 60 95 ns (1) (2) (3) Specified by design The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. 8.6 Switching Characteristics VDD = 4.5 V to 15 V, TJ = TA = –40°C to 125°C (unless otherwise noted) (see Figure 1) TYP MAX tR Rise time (OUT) PARAMETER CLOAD = 10 nF TEST CONDITIONS 20 75 ns tF Fall time (OUT) CLOAD = 10 nF 20 35 ns tD1 Delay time, IN rising (IN to OUT) CLOAD = 10 nF 25 75 ns tD2 Delay time, IN falling (IN to OUT) CLOAD = 10 nF 35 75 ns Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: UCC27321-Q1 UCC27322-Q1 MIN Submit Documentation Feedback UNIT 5 UCC27321-Q1, UCC27322-Q1 SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 www.ti.com (a) (b) 5V IN VTH 0V tD1 VTH IN VTH tD2 VTH tD1 tD2 tF VDD 80% 80% 80% tR OUT 80% tR OUT 20% tF 20% 0V The 20% and 80% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 1. Switching Waveforms for Inverting Driver (a) and Noninverting Driver (b) 5V ENBL VIN_L VIN_H 0V tD3 tD4 VDD 80% 80% tF tR OUT 20% 0V The 20% and 80% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 2. Switching Waveforms for Enable to Output 6 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: UCC27321-Q1 UCC27322-Q1 UCC27321-Q1, UCC27322-Q1 www.ti.com SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 8.7 Typical Characteristics 700 700 600 ENBL = 0V IN = 5V 500 400 IDD – InputCurrentIdle – μA IDD – InputCurrentIdle – μA 600 ENBL = VDD IN = 5V 300 ENBL = 0V IN = 0V 200 ENBL = 0V IN = 5V 500 400 ENBL = 0V IN = 0V 300 ENBL = VDD IN = 5V 200 ENBL = VDD , IN = 0V 100 100 ENBL = VDD , IN = 0V 0 0 2 0 4 6 8 10 12 VDD – Supply Voltage – V 14 16 0 700 700 IDD – InputCurrentIdle – μA IDD – InputCurrentIdle – μA 800 ENBL = HI IN = LO ENBL = HI IN = HI 500 400 ENBL = LO IN = LO 300 6 8 10 12 14 16 Figure 4. Input Current Idle vs Supply Voltage (UCC27322-Q1) 800 ENBL = LO IN = HI 4 VDD – Supply Voltage – V Figure 3. Input Current Idle vs Supply Voltage (UCC27321-Q1) 600 2 200 ENBL = HIIGH IN =HIIGH 600 ENBL = LOW 500 IN = HIIGH 400 ENBL = LOW IN = LOW 300 ENBL = HIIGH IN = LOW 200 100 100 0 -- 50 -- 25 0 25 50 75 100 125 0 -- 50 -- 25 TJ – Temperature – °C 0 25 50 100 75 125 TJ – Temperature – °C Figure 5. Input Current Idle vs Temperature (UCC27321-Q1) Figure 6. Input Current Idle vs Temperature (UCC27322-Q1) 70 CLOAD = 10 n F CLOAD = 10 nF 60 tA = – 40°C tR – Rise Time – ns 50 40 tA = 105°C tA = 25°C 30 20 tA = 0°C 10 0 4 6 8 10 12 14 16 VDD – Supply Voltage – V Figure 7. Rise Time vs Supply Voltage Figure 8. Fall Time vs Supply Voltage Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: UCC27321-Q1 UCC27322-Q1 Submit Documentation Feedback 7 UCC27321-Q1, UCC27322-Q1 SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 www.ti.com Typical Characteristics (continued) 40 200 VDD = 5 V VDD = 5 V 160 VDD = 10 V VDD = 10 V VDD = 15 V tR – Fall Time – ns tR – Rise Time – ns 30 VDD = 15 V 20 120 80 10 40 0 0.1 1 0 10 0.1 1 CLOAD – Load Capacitance – nF CLOAD –- Load Capacitance – nF 10 Figure 10. Fall Time vs Output Capacitance Figure 9. Rise Time vs Load Capacitance 70 70 CLOAD = 10 n F CLOAD = 10 n F tA = 105°C 60 60 tA = 25°C 50 tD2 – Delay Time -- ns tD1 -– Delay Time -- ns tA = 105°C 50 tA = 25°C 40 30 20 40 30 tA = 0°C 20 tA = –40°C tA = –40°C 10 10 tA = 0°C 0 0 4 6 8 10 12 14 16 4 6 VDD – Supply Voltage – V 10 12 14 16 Figure 12. tD2 Delay Time vs Supply Voltage 70 70 60 60 VDD = 5 V 50 VDD = 5 V tD2 – Delay Time – ns tD1 – Delay Time –- ns Figure 11. tD1 Delay Time vs Supply Voltage VDD = 10 V 40 30 20 50 40 30 VDD = 15 V VDD = 10 V 20 VDD = 15 V 10 10 0 1 10 100 CLOAD – Load Capacitance – nF Figure 13. tD1 Delay Time vs Load Capacitance 8 8 VDD – Supply Voltage – V Submit Documentation Feedback 0 1 10 CLOAD – Load Capacitance – nF 100 Figure 14. tD2 Delay Time vs Load Capacitance Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: UCC27321-Q1 UCC27322-Q1 UCC27321-Q1, UCC27322-Q1 www.ti.com SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 Typical Characteristics (continued) 2.0 50 45 VDD = 15 V CLOAD = 10 n F TA = 25°C tD2 Propagation Time -- ns tRISE 35 30 25 20 15 10 tFALL tD1 1.9 VON – Input Threshold Voltage – V 40 1.8 1.7 1.6 1.5 VDD = 10 V VDD = 4. 5 V 1.4 1.3 5 0 0 5 10 VIN(peak) – Peak Input Voltage – V 1.2 --50 15 -- 25 0 25 50 75 100 125 TJ – Temperature – °C Figure 15. Propagation Times vs Peak Input Voltage Figure 16. Input Threshold vs Temperature 150 3.0 140 ENBL -- ON 2.5 130 RENBL – Enable Resistance – Ω Enable thresholdand hysteresis – V VDD = 15 V 2.0 1.5 1.0 ENBL -- OFF 120 110 100 90 80 70 0.5 60 ENBL -- HYSTERESIS 0 -- 50 -- 25 0 25 50 75 TJ – Temperature –°C 100 50 -- 50 125 --25 0 25 50 75 Figure 17. Enable Threshold and Hysteresis vs Temperature 125 Figure 18. Enable Resistance vs Temperature IN = GND ENBL = VDD VDD – Input Voltage – V 1 V/div IN = GND ENBL = V DD VDD – Input Voltage – V 1 V/div 100 TJ – Temperature – °C VDD OUT OUT 0V 0V 10 nF Between Output and GND 50 μs/div Figure 19. Output Behavior vs VDD (UCC27321-Q1) VDD 10 nF Between Output and GND 50 μs/div Figure 20. Output Behavior vs VDD (UCC27321-Q1) Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: UCC27321-Q1 UCC27322-Q1 Submit Documentation Feedback 9 UCC27321-Q1, UCC27322-Q1 SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 www.ti.com Typical Characteristics (continued) IN = VDD ENBL = VDD VDD – Supply Voltage – V 1 V/div VDD – Supply Voltage – V 1 V/div IN = VDD ENBL = VDD VDD OUT VDD OUT 0V 0V 10 nF Between Output and GND 50 μs/div Figure 21. Output Behavior vs VDD (Inverting) 10 nF Between Output and GND 50 μs/div Figure 22. Output Behavior vs VDD (Inverting) IN = GND ENBL = VDD VDD OUT 0V 10 VDD – Supply Voltage – V 1 V/div VDD – Supply Voltage – V 1 V/div IN = GND ENBL = VDD VDD OUT 0V 10 nF Between Output and GND 50 μs/div 10 nF Between Output and GND 50 μs/div Figure 23. Output Behavior vs VDD (Noninverting) Figure 24. Output Behavior vs VDD (Noninverting) Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: UCC27321-Q1 UCC27322-Q1 UCC27321-Q1, UCC27322-Q1 www.ti.com SLUSA13D – FEBRUARY 2010 – REVISED SEPTEMBER 2016 9 Detailed Description 9.1 Overview The UCC27321-Q1 and UCC27322-Q1 drivers serve as an interface between low-power controllers (discrete controllers, DSPs, MCUs, or microprocessors) and power MOSFETs. High-frequency power supplies often require high-speed, high-current drivers such as the UCC2732x-Q1 family. A leading application provides a highpower buffer stage between the PWM output of the control device and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the device drives the power device gates through a drive transformer. Synchronous rectification supplies also have the need to drive multiple devices simultaneously, which can present an extremely large load to the control circuitry. The inverting driver (UCC27321-Q1) is useful for generating inverted gate-drive signals from controllers that have outputs of the opposite polarity. For example, this driver can provide a gate signal for ground-referenced, Nchannel synchronous rectifier MOSFETs in buck derived converters. This driver can also be used for generating a gate-drive signal for a P-channel MOSFET from a controller that is designed for N-channel applications. MOSFET gate drivers are generally used when it is not feasible to have the primary PWM regulator device directly drive the switching devices for one or more reasons. The PWM device may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases, there may be a desire to minimize the effect of high-frequency switching noise by placing the highcurrent driver physically close to the load. Also, newer devices that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high-impedance input to a driver such as the UCC2732x-Q1. Finally, the control device may be under thermal stress due to power dissipation and an external driver can help by moving the heat from the controller to an external package. 9.2 Functional Block Diagram INPUT/OUTPUT TABLE VDD 1 8 VDD INVERTING 7 OUT VDD IN 2 NON INVERTING 6 AGND IN OUT 0 0 0 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 OUT R ENBL ENBL INVERTING UCC27321-Q1 ENBL NON INVERTING UCC27322-Q1 3 4 5 PGND Copyright © 2016, Texas Instruments Incorporated 9.3 Feature Description 9.3.1 Input Stage The IN threshold has a 3.3-V logic sensitivity over the full range of VDD voltage; yet, it is equally compatible with 0-V to VDD signals. The inputs of UCC2732x-Q1 family of drivers are designed to withstand 500-mA reverse current without either damage to the device or logic upset. In addition, the input threshold turnoff of the UCC2732x-Q1 is slightly raised for improved noise immunity. The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is satisfied in typical power-supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (