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UCC27423-EP, UCC27424-EP
SLUS704C – FEBRUARY 2007 – REVISED DECEMBER 2014
UCC2742x-EP Dual 4-A High-Speed Low-Side MOSFET Driver With Enable
1 Features
3 Description
•
•
•
•
The UCC27423 and UCC27424 high-speed MOSFET
drivers can deliver large peak currents into capacitive
loads. Two standard logic options are offered – dual
inverting and dual noninverting drivers. The
UCC27424 thermally-enhanced 8-pin PowerPAD™
MSOP package (DGN) drastically lowers the thermal
resistance to improve long-term reliability. The
UCC27423 is offered in a standard SOIC-8 (D)
package.
1
•
•
•
•
•
•
•
Industry-Standard Pinout
Enable Functions for Each Driver
High Current-Drive Capability of ±4 A
Unique Bipolar and CMOS True-Drive Output
Stage Provides High Current at MOSFET Miller
Thresholds
TTL-/CMOS-Compatible Inputs Independent of
Supply Voltage
20-ns Typical Rise and 15-ns Typical Fall Times
With 1.8-nF Load
Typical Propagation Delay Times of 25 ns With
Input Falling and 35 ns With Input Rising
4.5-V to 15-V Supply Voltage
Dual Outputs can be Paralleled for Higher Drive
Current
Available in Thermally-Enhanced MSOP
PowerPAD™ Package With 4.7°C/W RθJC
Supports Defense, Aerospace, and Medical
Applications
– Controlled Baseline
– One Assembly/Test Site
– One Fabrication Site
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
Using a design that inherently minimizes shootthrough current, this driver delivers 4 A of current
where it is needed most – at the Miller plateau region
during the MOSFET switching transition. A unique
bipolar and MOSFET hybrid output stage in parallel
also allows efficient current sourcing and sinking at
low supply voltages.
The UCC27423 and UCC27424 provide enable
(ENB) functions to better control the operation of the
driver applications. ENBA and ENBB are
implemented on pins 1 and 8, which previously were
left unused in the industry-standard pinout. ENBA and
ENBB are pulled up internally to VDD for active-high
logic and can be left open for standard operation.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC27423-EP
D (8)
3.91 mm × 4.90 mm
UCC27424-EP
DGN (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
Switch-Mode Power Supplies
DC/DC Converters
Motor Controllers
Line Drivers
Class-D Switching Amplifiers
Simplified Schematic
Vsource
Vout
EN
ENBA
IN
INA
ENBB
R1
OUTA
Q1
UCC27424-EP
Cout
GND
VDD
INB
OUTB
4.5V to 16V
C1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27423-EP, UCC27424-EP
SLUS704C – FEBRUARY 2007 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
4
5
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Dissipation Ratings ........................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9
Power Supply Recommendations...................... 18
9.1 Drive Current and Power Requirements ................. 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
10.3 Thermal Considerations ........................................ 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support .......................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2012) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision A (November, 2009) to Revision B
Page
•
Changed minimum supply voltage from 4-V to 4.5-V in Features section ............................................................................. 1
•
Changed Figure 11, Rise Time vs Supply Voltage................................................................................................................. 8
•
Changed Figure 12 Fall Time vs Supply Voltage .................................................................................................................. 8
•
Changed first paragraph of Operational Waveforms and Circuit Layout section ................................................................. 13
•
Changed Figure 25, Current Sinking .................................................................................................................................... 16
•
Changed Figure 26, Current Sourcing.................................................................................................................................. 16
2
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SLUS704C – FEBRUARY 2007 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
D or DGN Package
(Top View)
ENBA
1
8
ENBB
INA
2
7
OUTA
GND
3
6
VDD
INB
4
5
OUTB
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ENBA
1
I
Enable for driver A with logic-compatible threshold and hysteresis. The driver output can be enabled and
disabled with this pin. It is pulled up internally to VDD with a 100-kΩ resistor for active-high operation. When the
device is disabled, the output state is low, regardless of the input state.
ENBB
8
I
Enable for driver B with logic-compatible threshold and hysteresis. The driver output can be enabled and
disabled with this pin. It is pulled up internally to VDD with a 100-kΩ resistor for active-high operation. The output
state when the device is disabled is low, regardless of the input state.
GND
3
—
Common ground. This ground should be connected very closely to the source of the power MOSFET that the
driver is driving.
INA
2
I
Input A. Input signal of the A driver, which has logic-compatible threshold and hysteresis. If not used, this input
should be tied to either VDD or GND. Do not leave floating.
INB
4
I
Input B. Input signal of the A driver, which has logic-compatible threshold and hysteresis. If not used, this input
should be tied to either VDD or GND. Do not leave floating.
OUTA
7
O
Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
OUTB
5
O
Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
VDD
6
I
Supply. Supply voltage and the power input connection for this device.
6 Specifications
6.1 Absolute Maximum Ratings (1)
(2)
over operating free-air temperature range (unless otherwise noted)
MN
VDD
VIN
TJ
Supply voltage
–0.3
Output current
OUTA, OUTB
Input voltage
INA, INB
Enable voltage
ENBA, ENBB
Power dissipation at TA =
25°C
D package
(1)
(2)
(3)
UNIT
16
V
DC, IOUT_DC
0.2
Pulsed (0.5 μs), IOUT_PULSED
4.5
6 or VDD + 0.3 (3)
–0.3
6 or VDD + 0.3 (3)
V
650
mW
3
W
150
°C
300
°C
150
°C
DGN package
Junction operating temperature
–55
Storage temperature
A
–5
Lead temperature (soldering, 10 s)
Tstg
MAX
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.
Whichever is larger
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6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
TJ
Operating junction temperature
MIN
MAX
UNIT
–55
125
°C
6.4 Thermal Information
UCC27423-EP
THERMAL METRIC
(1)
UCC27424-EP
D
DGN
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
111.4
RθJC(top)
Junction-to-case (top) thermal resistance
70.8
RθJB
Junction-to-board thermal resistance
56.6
ψJT
Junction-to-top characterization parameter
10.9
ψJB
Junction-to-board characterization parameter
56.1
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Power Dissipation Ratings
PACKAGE
SUFFIX
RθJC
(°C/W)
RθJA
(°C/W)
POWER RATING
(mW)
TA = 70°C
DERATING FACTOR
ABOVE 70°C (mW/°C)
MSOP-8 PowerPAD (1)
DGN
4.7
50 to 59
1370 (2)
17.1 (2)
SOIC 8
(1)
(2)
(3)
(4)
4
D
42
84 to 160
344 to 655
(3) (4)
6.25 to 11.9 (3) (4)
The PowerPAD package is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate, which is the ground of the device.
150°C operating junction temperature is used for power-rating calculations.
The range of values indicates the effect of PCB. These values are intended to give the system designer an indication of the best- and
worst-case conditions. In general, the system designer should attempt to use larger traces on the PCB where possible, in order to
spread the heat away from the device more effectively. For information on the PowerPAD package, refer to technical brief, PowerPad™
Thermally-Enhanced Package, SLMA002, and application brief, PowerPad™ Made Easy, SLMA004.
125°C operating junction temperature is used for power-rating calculation.
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SLUS704C – FEBRUARY 2007 – REVISED DECEMBER 2014
6.6 Electrical Characteristics
VDD = 4.5 V to 15 V, TA = –55°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCC27423
MIN
UCC27424
TYP MAX
MIN
TYP MAX
UNIT
INPUT (INA, INB)
VIN_H
Logic 1 input threshold
VIN_L
Logic 0 input threshold
Input current
2
2
V
1
0 V ≤ VIN ≤ VDD
–10
0
10
–10
0
1
V
10
μA
OUTPUT (OUTA, OUTB)
Output current
VDD = 14 V (1)
(2)
VOH
High-level output voltage
VOH = VDD – VOUT, IOUT = –10 mA
VOL
Low-level output level
IOUT = 10 mA
Output resistance high
IOUT = –10 mA, VDD = 14 V (3)
Output resistance low
IOUT = –10 mA, VDD = 14 V (3)
Latch-up protection (1)
4
TA = 25°C
25
TA = full range
14
TA = 25°C
TA = full range
1.9
4
A
330
450
330
450
mV
22
40
22
40
mV
30
35
25
30
35
45
18
2.5
1.9
4
1.2
2.2
0.95
500
45
2.2
2.5
4
500
Ω
Ω
mA
SWITCHING TIME
tR
Rise time (OUTA, OUTB)
CLOAD = 1.8 nF (1)
20
40
20
40
ns
tF
Fall time (OUTA, OUTB)
CLOAD = 1.8 nF (1)
15
40
15
40
ns
35
55
35
50
ns
25
60
25
45
ns
tD1
Delay, IN rising (IN to OUT) CLOAD = 1.8 nF
(1)
tD2
Delay, IN falling (IN to
OUT)
(1)
CLOAD = 1.8 nF
ENABLE (ENBA, ENBB)
VIN_H
High-level input voltage
Low-to-high transition
1.7
2.4
3.1
1.7
2.4
2.9
V
VIN_L
Low-level input voltage
High-to-low transition
1.1
1.8
2.3
1.1
1.8
2.2
V
0.13
0.55
1.1
.10
0.55
0.9
V
75
75
Hysteresis
RENBL
Enable impedance
VDD = 14 V, ENBL = GND
100
160
100
140
kΩ
tD3
Propagation delay time (4)
CLOAD = 1.8 nF (1)
30
60
30
60
ns
tD4
Propagation delay time (4)
CLOAD = 1.8 nF (1)
100
150
100
150
ns
INB = 0 V
900 1350
300
450
INB = High
750 1100
750 1100
INB = 0 V
750 1100
750 1100
INB = High
600
900
INB = 0 V
300
450
300
450
INA = High
450
700
450
700
INB = 0 V
450
700
450
700
INB = High
600
900
600
900
OVERALL
Static operating current,
VDD = 15 V,
ENBA =
ENBB = 15 V
INA = 0 V
INA = HIGH
IDD
Disabled,
VDD = 15 V,
ENBA =
ENBB = 0 V
(1)
(2)
(3)
(4)
INA = 0 V
INA = HIGH
1200 1800
μA
Specified by design. Not tested in production.
The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the
combined current from the bipolar and MOSFET transistors.
The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the
MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
See Figure 2.
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(a)
(b)
5V
90%
90%
Input
Input
0V
10%
10%
tD1
tD2
tF
tF
tF
tF
16 V
90%
90%
Output
Output
tD2
10%
0V
A.
90%
tD1
10%
The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
5V
ENBx
VIN_L
VIN_H
0V
tD3
tD4
VDD
90%
OUTx
90%
tR
tF
10%
0V
A.
The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 2. Switching Waveform for Enable to Output
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SLUS704C – FEBRUARY 2007 – REVISED DECEMBER 2014
Years Estimated Life
1000
100
Wirebond Voiding Fail Mode
10
1
100
Electromigration Fail Mode
110
120
130
140
150
160
Continuous Tj (°C)
A.
See data sheet for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
C.
Enhanced plastic product disclaimer applies
Figure 3. UCC27424MDGNREP Operating Life Derating Chart
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100
100
80
80
10 nF
IDD − Supply Current (mA)
IDD − Supply Current (mA)
6.7 Typical Characteristics
10 nF
60
40
4.7 nF
2.2 nF
20
4.7 nF
60
40
2.2 nF
20
1 nF
470 pF
1 nF
0
0
500 K
0
470 pF
1.5 M
2M
1M
0
500 K
ƒ, Frequency (Hz)
1M
1.5 M
2M
ƒ, Frequency (Hz)
Figure 4. Supply Current vs Frequency (VDD = 4.5 V)
Figure 5. Supply Current vs Frequency (VDD = 8 V)
150
200
IDD − Supply Current (mA)
IDD − Supply Current (mA)
150
10 nF
100
4.7 nF
2.2 nF
50
4.7 nF
10 nF
100
2.2 nF
50
1 nF
470 pF
1 nF
470 pF
0
0
0
500 K
1M
1.5 M
0
2M
500 K
1M
1.5 M
2M
ƒ, Frequency (Hz)
ƒ, Frequency (Hz)
Figure 6. Supply Current vs Frequency (VDD = 12 V)
Figure 7. Supply Current vs Frequency (VDD = 15 V)
90
160
80
140
2 MHz
70
IDD − Supply Current (mA)
IDD − Supply Current (mA)
120
60
50
1 MHz
40
30
500 kHz
20
2 MHz
100
80
60
1 MHz
40
500 kHz
200 kHz
10
100 kHz
200 kHz
50 kHz
0
4
6
8
10
12
14
16
20
100 kHz
50 kHz
20 kHz
0
4
9
VDD − Supply Voltage (V)
Figure 8. Supply Current vs Supply Voltage
(CLOAD = 2.2 nF)
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19
VDD − Supply Voltage (V)
Figure 9. Supply Current vs Supply Voltage
(CLOAD = 4.7 nF)
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Typical Characteristics (continued)
0.60
Input = V DD
0.50
tr − Rise Time (ns)
VDD − Supply V oltage (V)
0.55
Input = 0 V
0.45
0.40
0.35
0.30
4
6
8
10
12
VDD − Supply V oltage (V)
14
16
VDD − Supply Voltage (V)
Figure 10. Supply Current vs Supply Voltage
Figure 11. Rise Time vs Supply Voltage
3.0
ENBL − ON
tr − Fall Time (ns)
Enable Threshold and Hysteresis (V)
2.5
2.0
1.5
1.0
ENBL − OFF
0.5
ENBL − HYSTERESIS
0
−50
−25
VDD − Supply Voltage (V)
Figure 12. Fall Time vs Supply Voltage
0
25
50
75
TJ − Temperature (°C)
100
125
Figure 13. Enable Threshold and Hysteresis vs Temperature
150
140
120
110
100
90
80
1 V/div
VDD − Supply V oltage (V)
RENBL − Enable Resistance (W)
130
VDD
OUT
70
0V
60
50
−50
−25
0
25
50
75
100
125
10 nF Between Output and GND
50 µs/div
TJ − Temperature (°C)
IN = GND
Figure 14. Enable Resistance vs Temperature
ENBL = VDD
Figure 15. Output Behavior vs Supply Voltage (Inverting)
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1 V/div
VDD − Supply V oltage (V)
1 V/div
VDD − Supply V oltage (V)
Typical Characteristics (continued)
VDD
OUT
VDD
0V
0V
OUT
10 nF Between Output and GND
50 µs/div
10 nF Between Output and GND
50 µs/div
IN = VDD
ENBL = VDD
Figure 17. Output Behavior vs VDD (Inverting)
VDD − Supply V oltage (V)
VDD − Supply V oltage (V)
Figure 16. Output Behavior vs Supply Voltage (Inverting)
1 V/div
VDD
OUT
ENBL = VDD
1 V/div
IN = GND
VDD
OUT
0V
0V
10 nF Between Output and GND
50 µs/div
ENBL = VDD
IN = VDD
VDD
ENBL = VDD
Figure 19. Output Behavior vs VDD (Noninverting)
VDD
1 V/div
1 V/div
VDD − Supply V oltage − V
Figure 18. Output Behavior vs VDD (Inverting)
VDD − Supply V oltage (V)
IN = VDD
10 nF Between Output and GND
50 µs/div
OUT
OUT
0V
0V
10 nF Between Output and GND
50 µs/div
10 nF Between Output and GND
50 µs/div
IN = VDD
ENBL = VDD
Figure 20. Output Behavior vs VDD (Noninverting)
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IN = GND
ENBL = VDD
Figure 21. Output Behavior vs VDD (Noninverting)
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Typical Characteristics (continued)
OUT
1.9
VDD = 15 V
1.8
1.7
1.6
1.5
VDD = 10 V
VDD = 4.5 V
1.4
1.3
0V
10 nF Between Output and GND
50 µs/div
IN = GND
VON − Input Threshold V oltage (V)
VDD
1 V/div
VDD − Supply V oltage (V)
2.0
1.2
−50
−25
0
25
50
75
100
125
TJ − Temperature (°C)
ENBL = VDD
Figure 22. Output Behavior vs VDD (Noninverting)
Figure 23. Input Threshold vs Temperature
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7 Detailed Description
7.1 Overview
High-frequency power supplies often require high-speed, high-current drivers such as the UCC2742x. A leading
application of the UCC2742x provides a high-power buffer stage between the pulse-duration modulation (PWM)
output of the control IC and the gates of the primary power MOSFET or insulated gate bipolar transistor (IGBT)
switching devices. In other cases, the driver IC is used to drive the power-device gates through a drive
transformer. Synchronous rectification supplies also have the need to simultaneously drive multiple devices,
which can present an extremely-large load to the control circuitry.
Driver ICs are used when it is not feasible to have the primary PWM regulator IC directly drive the switching
devices, for one or more reasons. The PWM IC may not have the brute drive capability required for the intended
switching MOSFET, limiting the switching performance in the application. In other cases, there may be a desire
to minimize the effect of high-frequency switching noise by placing the high-current driver physically close to the
load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at
all. Their PWM outputs are intended to drive only the high-impedance input to drivers such as the UCC2742x.
Finally, the control IC may be under thermal stress due to power dissipation, and an external driver can help by
moving the heat from the controller to an external package.
7.2 Functional Block Diagram
8
ENBB
7
OUTA
6
VDD
5
OUTB
ENBA 1
Inverting
INA 2
VDD
Noninverting
Inverting
GND 3
16
INB 4
Noninverting
UDG−01063
7.3 Feature Description
7.3.1 Input Stage
The input thresholds have a 3.3-V logic sensitivity over the full range of VDD voltages. However, they are equally
compatible with 0 to VDD signals. The inputs of the UCC2742x are designed to withstand 500-mA reverse current
without either damage to the IC or logic upset. The input stage of each driver should be driven by a signal with a
short rise or fall time. This condition is satisfied in typical power-supply applications, where the input signals are
provided by a PWM controller or logic gates with fast transition times (
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