UCC27423PE4

UCC27423, UCC27424, UCC27425 www.ti.com SLUS545D – NOVEMBER 2002 – REVISED MAY 2013 Dual 4-A High Speed Low-Side MOSFET Drivers With Enable Check for Samples: UCC27423, UCC27424, UCC27425 FEATURES DESCRIPTION • • • • The UCC27423/4/5 family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads. Three standard logic options are offered – dual-inverting, dual-noninverting and oneinverting and one-noninverting driver. The thermally enhanced 8-pin PowerPAD™ MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard SOIC-8 (D) or PDIP-8 (P) packages. 1 2 • • • • • • • Industry-Standard Pin-Out Enable Functions for Each Driver High Current Drive Capability of ±4A Unique BiPolar and CMOS True Drive Output Stage Provides High Current at MOSFET Miller Thresholds TTL/CMOS Compatible Inputs Independent of Supply Voltage 20ns Typical Rise and 15ns Typical Fall Times with 1.8nF Load Typical Propagation Delay Times of 25ns with Input Falling and 35ns with Input Rising 4V to 15V Supply Voltage Dual Outputs Can Be Paralleled for Higher Drive Current Available in Thermally Enhanced MSOP PowerPAD™ Package with 4.7°C/W θJC Rated From –40°C to 125°C APPLICATIONS • • • • • Switch Mode Power Supplies DC/DC Converters Motor Controllers Line Drivers Class D Switching Amplifiers Using a design that inherently minimizes shootthrough current, these drivers deliver 4A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. The UCC27423/4/5 provides enable (ENBL) functions to have better control of the operation of the driver applications. ENBA and ENBB are implemented on pins 1 and 8 which were previously left unused in the industry standard pin-out. They are internally pulled up to Vdd for active high logic and can be left open for standard operation. BLOCK DIAGRAM 8 ENBB 7 OUTA 6 VDD 5 OUTB ENBA 1 INVERTING INA 2 VDD NON-INVERTING INVERTING GND 3 INB 4 NON-INVERTING UDG-01063 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2013, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545D – NOVEMBER 2002 – REVISED MAY 2013 www.ti.com ORDERING INFORMATION (1) (2) OUTPUT CONFIGURATION TEMPERATURE RANGE TA = TJ PACKAGED DEVICES SOIC-8 (D) (1) MSOP-8 PowerPAD (DGN) (2) PDIP-8 (P) Dual inverting –40°C to 125°C UCC27423D UCC27423DGN UCC27423P Dual nonInverting –40°C to 125°C UCC27424D UCC27424DGN UCC27424P One inverting, one noninverting –40°C to 125°C UCC27425D UCC27425DGN UCC27425P D (SOIC-8) and DGN (PowerPAD-MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27423DR, UCC27424DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package. The PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. D, DGN, OR P PACKAGE (TOP VIEW) D, DGN, OR P PACKAGE (TOP VIEW) D, DGN, OR P PACKAGE (TOP VIEW) UCC27425 UCC27424 UCC27423 ENBA 1 8 ENBB ENBA 1 8 ENBB ENBA 1 8 ENBB INA 2 7 OUTA INA 2 7 OUTA INA 2 7 OUTA 6 VDD GND 3 GND 3 5 OUTB INB 4 6 VDD INB 4 (DUAL INVERTING) 6 VDD GND 3 5 OUTB 5 OUTB INB 4 (DUAL NON-INVERTING) (ONE INVERTING AND ONE NON-INVERTING) POWER DISSIPATION RATING TABLE (1) (2) (3) PACKAGE SUFFIX θJC (°C/W) θJA (°C/W) POWER RATING (mW) TA = 70°C (1) DERATING FACTOR ABOVE 70°C (mW/°C) (1) SOIC-8 D 42 84 - 160‡ 344–655 (2) 6.25–11.9 (2) PDIP-8 P 49 110 500 9 MSOP PowerPAD-8 (3) DGN 4.7 50 - 59‡ 1370 17.1 125°C operating junction temperature is used for power rating calculations The range of values indicates the effect of pc-board. These values are intended to give the system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the pc-board where possible in order to spread the heat away form the device more effectively. For information on the PowerPAD™ package, refer to Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments (SLMA002) and Application Brief, PowerPad Made Easy, Texas Instruments (SLMA004). The PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. Table 1. Input/Output Table INPUTS (VIN_L, VIN_H) 2 UCC27423 UCC27424 UCC27425 ENBA ENBB INA INB OUTA OUTB OUTA OUTB OUTA H H L L H H L L H L H H L H H L L H H H H H H L L H H L L L H H H H L L H H L H L L X X L L L L L L Submit Documentation Feedback OUTB Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: UCC27423 UCC27424 UCC27425 UCC27423, UCC27424, UCC27425 www.ti.com SLUS545D – NOVEMBER 2002 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT VDD Supply voltage -0.3 to 16 V IOUT_DC Output current (OUTA, OUTB) DC 0.2 A IOUT_PULSED Pulsed, (0.5μs) 4.5 A VIN Input voltage (INA, INB) -5 to 6 or VDD+0.3 (whichever is larger) V Enable voltage (ENBA, ENBB) –0.3 V to 6 V or VDD+0.3 (whichever is larger) DGN package Power dissipation at TA = 25°C 3 D package 650 P package 350 W mW TJ Junction operating temperature –55 to 150 Tstg Storage temperature –65 to 150 Lead temperature (soldering, 10 sec) (1) °C 300 When VDD ≤ 6 V, EN rating max value is 6 V; when VDD > 6 V, EN rating max value is VDD + 0.3 V. ELECTRICAL CHARACTERISTICS VDD = 4.5V to 15V, TA = –40°C to 125°C ,TA = TJ, (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT INPUT (INA, INB) VIN_H Logic 1 input threshold VIN_L Logic 0 input threshold Input current 2 1 0 V ≤ VIN ≤ VDD –10 0 10 V μA OUTPUT (OUTA, OUTB) (1) Output current VDD = 14 V VOH High-level output voltage VOH = VDD – VOUT, IOUT = –10 mA VOL Low-level output level IOUT = 10 mA Output resistance high Output resistance low 4 TA = 25°C, IOUT = –10 mA, VDD = 14 V (2) 25 TA = full range, IOUT = –10 mA, VDD = 14 V (2) 18 TA = 25°C, IOUT = 10 mA, VDD = 14 V (2) TA = full range IOUT = 10 mA, VDD = 14 V (2) Latch-up protection 1.9 A 330 450 22 45 30 35 45 2.2 1.2 2.5 mV Ω 4.0 500 mA SWITCHING TIME tr Rise time (OUTA, OUTB) CLOAD = 1.8 nF 20 40 tf Fall time (OUTA, OUTB) CLOAD = 1.8 nF 15 40 td1 Delay, IN rising (IN to OUT) CLOAD = 1.8 nF 25 40 td2 Delay, IN falling (IN to OUT) CLOAD = 1.8 nF 35 50 (1) (2) ns The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: UCC27423 UCC27424 UCC27425 Submit Documentation Feedback 3 UCC27423, UCC27424, UCC27425 SLUS545D – NOVEMBER 2002 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) VDD = 4.5V to 15 V, TA = –40°C to 125°C,TA = TJ (unless otherwise noted) PARAMETER (1) (2) TEST CONDITION MIN TYP MAX 2.9 UNITS ENABLE (ENBA, ENBB) VIN_H High-level input voltage LO to HI transition 1.7 2.4 VIN_L Low-level input voltage HI to LO transition 1.1 1.8 2.2 0.15 0.55 0.90 75 Hysteresis RENBL Enable impedance VDD = 14 V, ENBL = GND 100 140 tD3 Propagation delay time (see Figure 2) CLOAD = 1.8 nF 30 60 tD4 Propagation delay time (see Figure 2) CLOAD = 1.8 nF 100 150 INA = 0 V, INB = 0 V 900 1350 INA = 0 V, INB = HIGH 750 1100 INA = HIGH, INB = 0 V 750 1100 INA = HIGH, INB = HIGH 600 900 INA = 0 V, INB = 0 V 300 450 INA = 0 V, INB = HIGH 750 1100 INA = HIGH, INB = 0 V 750 1100 1200 1800 600 900 INA = 0 V, INB = HIGH 1050 1600 INA = HIGH, INB = 0 V 450 700 INA = HIGH, INB = HIGH 900 1350 INA = 0 V, INB = 0 V 300 450 INA = 0 V, INB = HIGH 450 700 INA = HIGH, INB = 0 V 450 700 INA = HIGH, INB = HIGH 600 900 V kΩ ns OVERALL UCC27423 Static operating current, VDD = 15 V, ENBA = ENBB = 15 V IDD UCC27424 INA = HIGH, INB = HIGH INA = 0 V, INB = 0 V UCC27425 Disabled, VDD = 15 V, ENBA = ENBB = 0 V IDD (1) (2) All μA μA μA μA The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. (a) (b) +5V 90% 90% INPUT INPUT 10% 10% 0V tD1 tf tD2 tF tF tF 16V 90% 90% 90% tD1 OUTPUT tD2 OUTPUT 10% 10% 0V Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver 4 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: UCC27423 UCC27424 UCC27425 UCC27423, UCC27424, UCC27425 www.ti.com SLUS545D – NOVEMBER 2002 – REVISED MAY 2013 5V ENBx VIN_L VIN_H 0V tD3 tD4 VDD 90% 90% tR OUTx tF 10% 0V NOTE: The 10% and 90% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 2. Switching Waveform for Enable to Output Terminal Functions TERMINAL I/O FUNCTION NO. NAME 1 ENBA I Enable input for the driver A with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100kΩ resistor for active high operation. The output state when the device is disabled will be low regardless of the input state. 2 INA I Input A. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating. (1) 3 GND 4 INB I Input B. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating. 5 OUTB O Driver output B. The output stage is capable of providing 4A drive current to the gate of a power MOSFET. 6 VDD I Supply. Supply voltage and the power input connection for this device. 7 OUTA O Driver output A. The output stage is capable of providing 4A drive current to the gate of a power MOSFET. 8 ENBB I Enable input for the driver B with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100kΩ resistor for active high operation. The output state when the device is disabled will be low regardless of the input state. (1) (1) Common ground. This ground should be connected very closely to the source of the power MOSFET which the driver is driving. Refer to APPLICATION INFORMATION Section for more details. Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: UCC27423 UCC27424 UCC27425 Submit Documentation Feedback 5 UCC27423, UCC27424, UCC27425 SLUS545D – NOVEMBER 2002 – REVISED MAY 2013 www.ti.com APPLICATION INFORMATION General Information High frequency power supplies often require high-speed, high-current drivers such as the UCC27423/4/5 family. A leading application is the need to provide a high power buffer stage between the PWM output of the control IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is utilized to drive the power device gates through a drive transformer. Synchronous rectification supplies also have the need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry. Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to minimize the effect of high frequency switching noise by placing the high current driver physically close to the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC27423/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an external driver can help by moving the heat from the controller to an external package. Input Stage The input thresholds have a 3.3V logic sensitivity over the full range of VDD voltages; yet it is equally compatible with 0 to VDD signals. The inputs of UCC27423/4/5 family of drivers are designed to withstand 500-mA reverse current without either damage to the IC for logic upset. The input stage of each driver should be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (