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Design
UCC27531, UCC27533, UCC27536, UCC27537, UCC27538
SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
UCC2753x 2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver
1 Features
3 Description
•
The UCC2753x single-channel, high-speed gate
drivers can effectively drive MOSFET and IGBT
power switches. Using a design that allows for a
source of up to 2.5 A and 5-A sink through
asymmetrical drive (split outputs), coupled with the
ability to support a negative turn-off bias, rail-to-rail
drive capability, extremely small propagation delay
(17 ns typical), the UCC2753x devices are ideal
solutions for MOSFET and IGBT power switches. The
UCC2753x family of devices can also support enable,
dual input, and inverting and non-inverting input
functionality. The split outputs and strong
asymmetrical drive boost the devices immunity
against parasitic Miller turn-on effect and can help
reduce ground debouncing.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-cost gate driver (offering optimal solution for
driving FET and IGBTs)
Superior replacement to discrete transistor pair
drive (providing easy interface with controller)
TTL and CMOS compatible input logic threshold
(independent of supply voltage)
Split output options allow for tuning of turnon and
turnoff currents
Inverting and noninverting input configurations
Enable with fixed TTL compatible threshold
High 2.5-A source and 2.5-A or 5-A sink peak
drive currents at 18-V VDD
Wide VDD range from 10 V to 35 V
Input and enable pins capable of with standing up
to –5-V DC below ground
Output held low when inputs are floating or during
VDD UVLO
Fast propagation delays (17-ns Typical)
Fast rise and fall times
(15-ns and 7-ns typical with 1800-pF Load)
Undervoltage lockout (UVLO)
Used as a high-side or low-side driver (if designed
with proper bias and signal isolation)
Low-cost, space-saving 5-pin or 6-pin DBV (SOT23) package options
UCC27536 and UCC27537 pin-to-pin compatible
to TPS2828 and TPS2829
Operating temperature range of –40°C to 140°C
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC27531
SOIC (8)
4.90 mm × 3.91 mm
UCC27531
SOT-23 (6)
2.90 mm × 1.60 mm
UCC27533
SOT-23 (5)
2.90 mm × 1.60 mm
UCC27536
SOT-23 (5)
2.90 mm × 1.60 mm
UCC27537
SOT-23 (5)
2.90 mm × 1.60 mm
UCC27538
SOT-23 (6)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Driving IGBT Without Negative Bias
UCC27531
EN
1
IN
2 Applications
•
•
•
•
•
•
•
Switched-mode power supplies
DC-to-DC converters
Solar inverters, motor control, UPS
HEV and EV chargers
Home appliances
Renewable energy power conversion
SiC FET converters
OUTH
6
+
2
OUTL
5
VDD
GND
3
+
–
4
GND
Bouncing Up
to -6.5 V
18 V
ISENSE
Controller
VCE(sense)
VCC
+
–
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27531, UCC27533, UCC27536, UCC27537, UCC27538
SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9
1
1
1
2
4
4
5
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Switching Characteristics .......................................... 8
Timing Diagrams ....................................................... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagrams ..................................... 16
9.3 Feature Description................................................. 18
9.4 Device Functional Modes........................................ 21
10 Applications and Implementation...................... 23
10.1 Application Information.......................................... 23
10.2 Typical Application ................................................ 24
11 Power Supply Recommendations ..................... 32
12 Layout................................................................... 32
12.1 Layout Guidelines ................................................. 32
12.2 Layout Example .................................................... 33
12.3 Thermal Consideration.......................................... 33
13 Device and Documentation Support ................. 34
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
14 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (July 2015) to Revision G
Page
•
Changed to "H" from "L" ...................................................................................................................................................... 21
•
Changed to "L" from "H" ...................................................................................................................................................... 21
Changes from Revision E (July 2014) to Revision F
Page
•
Changed EN for UCC27531 From: Yes To: Yes / No in Device Comparison Table ............................................................ 4
•
Changed OUTPUT for UCC27531 From: Split To: Split / SingleDevice Comparison Table ................................................. 4
•
Added the 8-Pin SOIC package to the Pin Configuration and Functions section .................................................................. 5
•
Added UCC27531D to the Pin Functions table ..................................................................................................................... 6
•
Changed PMOS Symbol in Figure 32 ................................................................................................................................. 16
•
Changed PMOS and Logic Symbol in Figure 33 ................................................................................................................ 16
•
Changed PMOS and Logic Symbols in Figure 34................................................................................................................ 16
•
Changed PMOS and Logic Symbol in Figure 35 ................................................................................................................. 17
•
Changed PMOS Symbol in Figure 36 .................................................................................................................................. 17
•
Added Figure 37 .................................................................................................................................................................. 18
•
Changed PMOS Symbol in Figure 39 ................................................................................................................................. 20
•
Changed Enable Pin Column to Table 3 .............................................................................................................................. 21
•
Added Table 6 ..................................................................................................................................................................... 22
Changes from Revision D (April 2013) to Revision E
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
Changes from Revision C (April 2013) to Revision D
Page
•
Added Startup Current UCC27537 Bias Current Parameters to the ELECTRICAL CHARACTERISTICS............................ 7
•
Added UCC27531 Start-Up Current vs. Temperature TYPICAL CHARACTERISTICS diagram. ...................................... 11
•
Added UCC27537 Start-Up Current vs. Temperature TYPICAL CHARACTERISTICS diagram. ...................................... 11
Changes from Revision B (April 2013) to Revision C
•
Page
Added additional DESCRIPTION information. ..................................................................................................................... 15
Changes from Revision A (December 2012) to Revision B
•
Page
Added UCC27533, UCC27536, UCC27537 and UCC27538 parts to the datasheet............................................................. 1
Changes from Original (December 2012) to Revision A
•
Page
Changed Block Diagram......................................................................................................................................................... 4
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UCC27531, UCC27533, UCC27536, UCC27537, UCC27538
SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
www.ti.com
5 Description (continued)
Leaving the input pin open holds the driver output low. The logic behavior of the driver is shown in the application
diagram, timing diagram, and input and output logic truth table.
Internal circuitry on VDD pin provides an undervoltage lockout function that holds output low until VDD supply
voltage is within operating range.
6 Device Comparison Table
4
UCC27531
UCC27533
UCC27536
UCC27537
UCC27538
ION PEAK
2.5 A
2.5 A
2.5 A
2.5 A
2.5 A
IOFF PEAK
5A
5A
2.5 A
5A
5A
PACKAGE
SOT-23-6 / SOIC-8
SOT-23-5
SOT-23-5
SOT-23-5
SOT-23-6
IN
Single
Dual
Single
Single
Dual
IN LOGIC
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
EN
Yes / No
No
Yes
Yes
No
OUTPUT
Split / Single
Single
Single
Single
Split
INVERTING
No
Inverting/NonInverting
Yes
No
No
MAX VDD
35 V
35 V
35 V
35 V
35 V
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SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
7 Pin Configuration and Functions
5-Pin or 6-Pin SOT-23
DBV Package
Top View
UCC27531
UCC27533
EN
1
6 OUTH VDD
1
IN
2
5 OUTL GND
2
VDD
3
4 GND
UCC27536
5 OUT
IN+ 3
4 IN-
EN
1
GND
2
UCC27537
5 VDD
EN 1
4 OUT
5 VDD
VDD 1
6 OUTH
2
IN1
2
5 IN2
IN+ 3
4 OUT GND
3
4 OUTL
GND
IN- 3
UCC27538
8-Pin SOIC
D Package
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
UCC27531DBV
1
EN
I
Enable (Pull EN to GND to disable output, pull it high or leave open to enable output)
2
IN
I
Driver non-inverting input
3
VDD
I
Bias supply input
4
GND
-
Ground (all signals are referenced to this node)
5
OUTL
O
5-A sink current output of driver
6
OUTH
O
2.5-A Source Current Output of driver
1
VDD
I
Bias supply input
2
GND
-
Ground (All signals are referenced to this node)
3
IN+
I
Driver non-inverting input
4
IN-
I
Driver inverting input
5
OUT
O
2.5-A source and 5-A sink current output of driver
UCC27533DBV
UCC27536DBV
1
EN
I
Enable (pull EN to GND to disable output, pull it high or leave open to enable output)
2
GND
-
Ground (all signals are referenced to this node)
3
IN-
I
Driver inverting input
4
OUT
O
2.5-A source and 2.5-A sink current output of driver
5
VDD
I
Bias supply input
UCC27537DBV
1
EN
I
Enable (Pull EN to GND to disable Output, Pull it high or leave open to enable Output)
2
GND
-
Ground (All signals are referenced to this node)
3
IN+
I
Driver non-inverting input
4
OUT
O
2.5-A source and 5-A sink current output of driver
5
VDD
I
Bias supply input
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SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
www.ti.com
Pin Functions (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
UCC27538DBV
1
VDD
I
Bias supply input
2
IN1
I
Driver non-inverting input
3
GND
-
Ground (all signals are referenced to this node)
4
OUTL
O
5-A sink current output of driver
5
IN2
I
Driver non-inverting input
6
OUTH
O
2.5-A source current output of driver
1
NC
-
No connection
2
IN
I
Driver non-inverting input
3
GND
-
Ground (all signals are referenced to this node)
4
NC
-
No connection
5
NC
-
No connection
6
VDD
I
Bias supply input
7
OUT
O
5-A Sink Current Output of driver and 2.5-A Source Current Output of driver
8
NC
-
No connection
UCC27531D
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX
UNIT
Supply voltage
VDD
–0.3
35
V
Continuous
OUTH, OUTL, OUT
–0.3
VDD +0.3
V
Pulse
OUTH, OUTL, OUT (200 ns)
–2
VDD +0.3
V
–5
27
V
–6.5
27
V
–40
150
°C
Continuous IN, EN, IN+, IN-, IN1, IN2
Pulse IN, EN, IN+, IN–, IN1, IN2 (1.5 µs)
Operating virtual junction temperature, TJ
Lead temperature
Soldering, 10 sec.
300
Reflow
260
Storage temperature, Tstg
(1)
(2)
(3)
–65
150
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Thermal Information of the datasheet for thermal limitations and considerations of packages.
These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD
MIN
NOM
10
18
MAX
UNIT
32
V
–40
140
°C
Input voltage, IN, IN+, IN-, IN1, IN2
–5
25
V
Enable, EN
–5
25
V
Operating junction temperature
8.4 Thermal Information
THERMAL METRIC (1)
(2)
UCC27533,
UCC27536,
UCC27537
UCC27531,
UCC27538
UCC27531
DBV
DBV
SOIC
5 PINS
6 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
178.3
178.3
129.9
RθJC(top)
Junction-to-case (top) thermal resistance (3)
109.7
109.7
79.9
RθJB
Junction-to-board thermal resistance (4)
28.3
28.3
68.1
14.7
14.7
22.7
27.8
27.8
69.8
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
(1)
(2)
(3)
(4)
(5)
(6)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
8.5 Electrical Characteristics
Unless otherwise noted, VDD = 18 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are
positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531/8. Typical condition
specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 7.0, IN, EN=VDD
100
200
300
IN, EN = GND
100
217
300
VDD = 7.0, IN+ = GND, IN- = VDD
100
200
300
IN+ = VDD, IN- = GND
100
217
300
VDD = 7.0, IN- = GND, EN = VDD
100
217
300
IN- = VDD, EN = GND
100
217
300
VDD =7.0, IN+, EN = VDD
100
200
300
IN+, EN = GND
100
217
300
VDD = 7.0, IN1, IN2=VDD
100
200
300
IN1, IN2=GND
100
200
300
8
8.9
9.8
V
7.3
8.2
9.1
V
BIAS CURRENTS
IDDoff
Start-up current (UCC25731)
IDDoff
Start-up current (UCC27533)
IDDoff
Start-up current (UCC27536)
IDDoff
Start-up current (UCC27537)
IDDoff
Start-up Current (UCC27538)
μA
μA
μA
μA
μA
UNDERVOLTAGE LOCKOUT (UVLO)
VON
Supply start threshold
VOFF
Minimum operating voltage
after supply start
VDD_H
Supply voltage hysteresis
0.7
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SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
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Electrical Characteristics (continued)
Unless otherwise noted, VDD = 18 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are
positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531/8. Typical condition
specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT (IN, IN+, IN1, IN2)
VIN_H
Input signal high threshold,
output high
Output High, IN- = LOW, EN=HIGH, IN2 or IN1 =
HIGH (other is INPUT)
1.8
2
2.2
V
VIN_L
Input signal low threshold,
output low
Output Low, IN- = LOW, EN=HIGH, IN2 or IN1 =
HIGH (other is INPUT)
0.8
1
1.2
V
VIN_HYS
Input signal hysteresis
1
V
INPUT (IN-)
VIN_H
Input signal high threshold,
output low
Output low, IN+ = HIGH, EN = High
1.7
1.9
2.1
V
VIN_L
Input signal low threshold,
output high
Output high,, IN+ = HIGH, EN = High
0.8
1
1.2
V
VIN_HYS
Input signal hysteresis
0.9
V
ENABLE (EN)
VEN_H
Enable signal high threshold
Output High
1.7
1.9
2.1
V
VEN_L
Enable signal low threshold
Output Low
0.8
1
1.2
V
VEN_HYS
Enable signal hysteresis
0.9
V
–2.5/+5
A
OUTPUTS (OUTH/OUTL)
ISRC/SNK
Source peak current (OUTH)/
sink peak current (OUTL)
CLOAD = 0.22 µF, f = 1 kHz
VOH
OUTH, high voltage
IOUTH = -10 mA
VOL
OUTL, low voltage
VOL
OUTL, Low Voltage
UCC27536
ROH
OUTH, pull-up resistance
ROL
OUTL, pull-down resistance
ROL
OUTL, pull-down resistance
UCC27536
VDD
–0.2
VDD
–0.12
VDD
–0.07
V
IOUTL = 100 mA
0.065
0.125
V
IOUTL = 100 mA
0.13
0.23
V
11
12
12.5
7
12
20
TA = 25°C, IOUT = –10 mA
TA = –40°C to 140°C, IOUT = –10 mA
TA = 25°C, IOUT = 100 mA
0.45
0.65
0.85
TA = –40°C to 140°C, IOUT = 100 mA
0.3
0.65
1.25
TA = 25°C, IOUT = 100 mA
0.9
1.3
1.7
TA = –40°C to 140°C, IOUT = 100 mA
0.6
1.3
2.3
Ω
Ω
Ω
8.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tR
tF
Rise time
Fall time
TEST CONDITIONS
MIN
TYP
CLOAD = 1.8 nF, See Figure 1,
Figure 2, Figure 3
15
CLOAD = 1.8 nF, See Figure 1,
Figure 2, Figure 3
7
MAX
UNIT
ns
ns
CLOAD (UCC27536DBV) = 1.8 nF,
See Figure 1, Figure 2, Figure 3
10
tD1
Turn-on propagation delay
CLOAD = 1.8 nF, IN, IN+ = 0 V to 5
V, See Figure 1, Figure 2, Figure 3
17
26
ns
tD2
Turn-off propagation delay
CLOAD = 1.8 nF, IN, IN+ = 5 V to 0
V, See Figure 1, Figure 2, Figure 3
17
26
ns
tD3
Inverting turn-off propagation delay
CLOAD = 1.8 nF, IN- = 0 V to 5 V
17
28
ns
tD4
Inverting turn-on propagation delay
CLOAD = 1.8 nF, IN- = 5 V to 0 V
20
28
ns
8
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SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
8.7 Timing Diagrams
Figure 1. UCC27531: (Output = OUTH Tied to OUTL) Input = IN, (EN = VDD), or Input = EN, (IN = VDD)
UCC27537: (Output = OUT) Input = IN+, (EN = VDD), or Input = EN, (IN+ = VDD)
UCC27538: (Output = OUTH Tied to OUTL) Input = IN1, (IN2 = VDD), or Input = IN2, (IN1 = VDD)
High
INPUT
(IN+ pin)
Low
High
IN- pin
Low
90%
OUTPUT
10%
tD1 t r
tD2 tf
Figure 2. UCC27533: (Output = OUT) Input = IN+
UCC27536: (Output = OUT) Input = EN
High
INPUT
(IN- pin)
Low
High
Enable pin
Low
90%
OUTPUT
10%
tD2 tf
tD2 tr
Figure 3. UCC27533: (Output = OUT) Enable = IN+
UCC27536: (Output = OUT) Enable = EN
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8.8 Typical Characteristics
If not specified, INPUT refers to non-inverting input
25
12
10
Fall Time (ns)
Rise Time (ns)
20
15
8
6
10
4
5
2
0
10
20
30
40
Supply Voltage (V)
0
30
CLOAD = 1.8 nF
Figure 4. Rise Time vs. Supply Voltage
Figure 5. Fall Time vs. Supply Voltage
21
Input To Output Propagation Delay (ns)
12
8
4
TurnOn
20
30
TurnOff
19
17
15
0
10
40
C002
CLOAD = 1.8 nF
16
Fall Time UCC27536 (ns)
20
Supply Voltage (V)
20
0
10
C001
0
40
10
20
Supply Voltage (V)
30
40
Supply Voltage (V)
C003
C001
CLOAD = 1.8 nF
Figure 7. Propagation Delay vs. Supply Voltage
Figure 6. UCC27536 Fall Time vs. Supply Voltage
30
OUT RISING, IN- 5V to
0V
OUT FALLING, IN- 0V
to 5V
25
VDD = 10V
VDD = 18V
VDD = 32V
25
23
Supply Current (mA)
IN- Input To Output Propagation Delay (ns)
27
21
19
17
20
15
10
5
15
0
10
20
30
40
Supply Voltage (V)
0
0
100
200
300
400
500
Frequency (kHz)
C001
C001
CLOAD = 1.8 nF
Figure 8. IN- Propagation Delay vs. Supply
10
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Figure 9. Operating Supply Current vs. Frequency
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Typical Characteristics (continued)
If not specified, INPUT refers to non-inverting input
300
300
EN=IN=Vdd
IN- = VDD, IN+ = GND
EN=IN=GND
250
250
Startup Current (µA)
UCC27533 Startup Current (µA)
IN+ = VDD, IN- = GND
200
200
150
150
100
100
-50
0
50
100
-50
150
0
50
100
C005
C002
VDD = 7 V
VDD = 7 V
Figure 10. UCC27533 Start-Up Current vs. Temperature
Figure 11. UCC27531 Start-Up Current vs. Temperature
300
300
IN- = GND, EN = VDD
IN1 = IN2 = VDD
IN- = VDD, EN = GND
IN1 = IN2 = GND
250
UCC27538 Startup Current (µA)
UCC27536 Startup Current (µA)
150
Temperature ( °C)
Temperature ( °C)
200
150
100
250
200
150
100
-50
0
50
100
150
-50
0
50
Temperature ( °C)
100
150
Temperature ( °C)
C004
C005
VDD = 7 V
VDD = 7 V
Figure 12. UCC27536 Start-Up Current vs. Temperature
Figure 13. UCC27538 Start-Up Current vs. Temperature
4.5
300
IN+ = EN = Vdd
4.3
4.1
Idd (mA)
UCC27537 Startup Current (µA)
IN+ = EN = GND
250
200
3.9
150
3.7
3.5
100
-50
0
50
100
150
-50
0
50
100
C006
C003
VDD = 7 V
Figure 14. UCC27537 Start-Up Current vs. Temperature
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150
Temperature ( °C)
Temperature ( °C)
CLOAD = 1.8 nF
VDD = 7 V
fSW = 100 kHz
Figure 15. Operating Supply Current vs. Temperature
(Output Switching)
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Typical Characteristics (continued)
If not specified, INPUT refers to non-inverting input
2.4
9.6
Turn-On
UVLO Rising
UVLO Falling
2
Input Threshold (V)
9.2
Vdd UVLO Threshold (V)
Turn-Off
2.2
8.8
1.8
1.6
1.4
1.2
8.4
1
8
0.8
-50
0
50
100
-50
150
0
7HPSHUDWXUH Û&
50
100
C007
C008
Figure 16. UVLO Threshold Voltage vs. Temperature
Figure 17. Input Threshold vs. Temperature
2.4
2.4
Enable
OUT FALL
2.2
Disable
2.2
OUT RISE
2
2
Enable Threshold (V)
IN- Input Threshold (V)
150
7HPSHUDWXUH Û&
1.8
1.6
1.4
1.8
1.6
1.4
1.2
1.2
1
1
0.8
0.8
-50
0
50
100
150
-50
0
Temperature (Ü&
50
100
150
7HPSHUDWXUH Û&
C002
Figure 18. In- Input Threshold vs. Temperature
C009
Figure 19. Enable Threshold vs. Temperature
1.2
25
ROH
ROL
Output Pull-Down Resistance (Ω)
Output Pull-Up Resistance (Ω)
1
20
15
10
0.8
0.6
0.4
5
0.2
-50
0
50
100
150
Temperature ( °C)
-50
0
50
100
VDD = 18 V
Figure 20. Output Pullup Resistance vs. Temperature
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150
Temperature ( °C)
C010
C011
VDD = 18 V
Figure 21. Output Pulldown Resistance vs. Temperature
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Typical Characteristics (continued)
If not specified, INPUT refers to non-inverting input
0.6
30
IN=HIGH
Turn-On
Turn-Off
0.5
25
Propagation Delay (ns)
Operating Supply Current (mA)
IN=LOW
0.4
0.3
20
15
0.2
10
-50
0
50
100
150
-50
0
Temperature ( °C)
50
100
150
Temperature ( °C)
C012
C013
VDD = 18 V
VDD = 18 V
Figure 22. Operating Supply Current vs. Temperature
(Output In DC On/Off Condition)
Figure 23. Input-To-Output Propagation Delay vs.
Temperature
16
30
OUT RISING, IN- 5V to 0V
OUT FALLING, IN- 0V to 5V
15
Rise Time (ns)
IN- Propagation Delay (ns)
26
22
18
14
13
12
14
11
10
-50
0
50
100
-50
150
0
50
100
150
Temperature ( °C)
Temperature ( °C)
C014
C003
CLOAD = 1.8 nF
VDD = 18 V
VDD = 18 V
Figure 25. Rise Time vs. Temperature
Figure 24. IN– Input-To-Output Propagation Delay vs.
Temperature
9
20
8
Fall Time UCC27536 (ns)
Fall Time (ns)
15
7
6
10
5
5
4
0
-50
0
50
100
150
-50
Temperature ( °C)
0
50
VDD = 18 V
Figure 26. Fall Time vs. Temperature
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150
C003
C015
CLOAD = 1.8 nF
100
Temperature ( °C)
CLOAD = 1.8 nF
VDD = 18 V
Figure 27. UCC27536 Fall Time vs. Temperature
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Typical Characteristics (continued)
10
140
8
120
Rise Time (ns)
Supply Current (mA)
If not specified, INPUT refers to non-inverting input
6
4
100
80
60
2
Cload = 10nF
40
0
0
10
20
30
0
40
10
20
30
40
Supply Voltage (V)
Supply Voltage (V)
C017
C016
CLOAD = 1.8 nF
CLOAD = 1.8 nF
VDD = 18 V
Figure 29. Rise Time vs. Supply Voltage
Figure 28. Operating Supply Current vs. Supply Voltage
(Output Switching)
120
70
60
Fall Time UCC27536 (ns)
100
Fall Time (ns)
50
40
30
80
60
40
20
10
20
0
10
20
30
40
Supply Voltage (V)
0
10
20
14
30
40
Supply Voltage (V)
C018
C002
CLOAD = 1.8 nF
CLOAD = 1.8 nF
Figure 30. Fall Time vs. Supply Voltage
Figure 31. UCC27536 Fall Time vs. Supply Voltage
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9 Detailed Description
9.1 Overview
The UCC2753x family of devices are single-channel, high-speed, gate drivers capable of effectively driving
MOSFET and IGBT power switches by up to 2.5-A source and 5-A sink (asymmetrical drive) peak current.
Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turn-on effect. The
UCC2753x device can also feature a split-output configuration where the gate-drive current is sourced through
the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turnon and turn-off resistors to the OUTH and OUTL pins, respectively, and easily control the switching slew rates.
The driver has rail-to-rail drive capability and extremely small propagation delay, typically 17 ns.
The input threshold of UCC2753x is based on TTL and CMOS compatible low-voltage logic, which is fixed and
independent of VDD supply voltage. The 1-V typical hysteresis offers excellent noise immunity.
The driver has an EN pin with fixed TTL compatible threshold. EN is internally pulled up; pulling EN low disables
the driver, while leaving EN open provides normal operation. The EN pin can be used as an additional input with
the same performance as the IN, IN+, IN1, and IN2 pins.
Table 1. UCC2753x Features and Benefits
FEATURE
BENEFIT
High source and sink current capability, 2.5 A
and 5 A (asymmetrical).
High current capability offers flexibility in employing UCC2753x device to drive a variety of
power switching devices at varying speeds.
Low 17 ns (typ) propagation delay.
Extremely low pulse transmission distortion.
Wide VDD operating range of 10 V to 32 V.
Flexibility in system design.
Can be used in split-rail systems such as driving IGBTs with both positive and
negative(relative to Emitter) supplies.
Optimal for many SiC FETs.
VDD UVLO protection.
Outputs are held Low in UVLO condition, which ensures predictable, glitch-free operation at
power up and power down.
High UVLO of 8.9 V typical ensures that power switch is not on in high-impedance state
which could result in high power dissipation or even failures.
Outputs held low when input pin (INx) in
floating condition.
Safety feature, especially useful in passing abnormal condition tests during safety
certification
Split output structure option (OUTH, OUTL).
Allows independent optimization of turn-on and turn-off speeds using series gate resistors.
Strong sink current (5 A) and low pull-down
impedance (0.65 Ω).
High immunity to high dV/dt Miller turn-on events.
CMOS and TTL compatible input threshold
logic with wide hysteresis.
Enhanced noise immunity, while retaining compatibility with microcontroller logic level input
signals (3.3 V, 5 V) optimized for digital power.
Input capable of withstanding –6.5 V.
Enhanced signal reliability in noisy environments that experience ground bounce on the
gate driver.
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9.2 Functional Block Diagrams
IN
VDD
2
VREF
EN
1
3
VDD
6
OUTH
5
OUTL
VDD
GND
4
UVLO
EN Pull-Up Resistance to VREF = 500 kΩ, VREF = 5.8 V, IN Pull-Down Resistance to GND = 230 kΩ
Figure 32. UCC27531
IN+
VDD
3
VREF
IN-
4
1
VDD
5
OUT
VDD
GND
2
UVLO
IN– Pull-Up Resistance to VREF = 500 kΩ, VREF = 5.8 V, IN+ Pull-Down Resistance to GND = 230 kΩ
Figure 33. UCC27533
EN
VDD
1
VREF
5
VDD
4
OUT
VREF
IN-
3
VDD
GND
2
UVLO
EN Pull-Up Resistance to VREF = 500 kΩ, VREF = 5.8 V, IN- Pull-Up Resistance to VREF = 500 kΩ
Figure 34. UCC27536
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Functional Block Diagrams (continued)
EN
VDD
1
5
VDD
4
OUT
1
VDD
6
OUTH
4
OUTL
VREF
IN+
3
VDD
UVLO
GND
2
EN Pull-Up Resistance to VREF = 500 kΩ, VREF = 5.8 V, IN+ Pull-Down Resistance to GND = 230 kΩ
Figure 35. UCC27537
IN1
IN2
VDD
2
5
VDD
UVLO
GND
3
IN1 Pull-Down Resistance to GND = 230 kΩ, IN2 Pull-Down Resistance to GND = 230 kΩ
Figure 36. UCC27538
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Functional Block Diagrams (continued)
NC
VDD
1
8
NC
7
OUT
6
VDD
5
NC
VREF
IN
2
GND
3
VDD
UVLO
NC
4
IN Pull-Down Resistance to GND = 230 kΩ, VREF = 5.8 V, Pull-Up Resistance to VREF = 500 kΩ
Figure 37. UCC27531D
9.3 Feature Description
9.3.1 VDD Undervoltage Lockout
The UCC2753x device has internal UVLO protection feature on the VDD pin supply circuit blocks. To ensure
acceptable power dissipation in the power switch, this UVLO prevents the operation of the gate driver at low
supply voltages. Whenever the driver is in UVLO condition (when VDD voltage less than VON during power up
and when VDD voltage is less than VOFF during power down), this circuit holds all outputs LOW, regardless of the
status of the inputs. The UVLO is typically 8.9 V with 700-mV typical hysteresis. This hysteresis helps prevent
chatter when low VDD supply voltages have noise from the power supply and also when there are droops in the
VDD bias voltage when the system commences switching and there is a sudden increase in IDD. The capability to
operate at voltage levels such as 10 V to 32 V provides flexibility to drive Si MOSFETs, IGBTs, and emerging
SiC FETs.
VDD Threshold
VDD
IN
OUT
Figure 38. Power Up
18
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Feature Description (continued)
9.3.2 Input Stage
The input pins of UCC2753x device are based on a TTL and CMOS compatible input threshold logic that is
independent of the VDD supply voltage. With typical high threshold = 2 V and typical low threshold = 1 V, the
logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V logic. Wider
hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL logic implementations,
where the hysteresis is typically less than 0.5 V. This device also features tight control of the input pin threshold
voltage levels which eases system design considerations and ensures stable operation across temperature. The
very low input capacitance, typically 20 pF, on these pins reduces loading and increases switching speed.
The device features an important safety function wherein, whenever the input pin is in a floating condition, the
output is held in the low state. This is achieved using pull-up or pull-down resistors on the input pins as shown in
the block diagrams.
The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly varying input signals, especially in situations where the device
is located in a separate daughter board or PCB layout has long input connection traces:
• High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce.
Because the device features just one GND pin which may be referenced to the power ground, this may
interfere with the differential voltage between Input pins and GND and trigger an unintended change of output
state. Because of fast 17 ns propagation delay, this can ultimately result in high-frequency oscillations, which
increases power dissipation and poses risk of damage
• 1-V Input threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
If limiting the rise or fall times to the power device to reduce EMI is necessary, then an external resistance is
highly recommended between the output of the driver and the power device instead of adding delays on the input
signal. This external resistor has the additional benefit of reducing part of the gate charge related power
dissipation in the gate driver device package and transferring it into the external resistor itself.
Finally, because of the unique input structure that allows negative voltage capability on the Input and Enable
pins, caution must be used in the following applications:
• Input or Enable pins are switching to amplitude > 15 V
• Input or Enable pins are switched at dV/dt > 2 V/ns
If both of these conditions occur, it is advised to add a series 150-Ω resistor for the pin(s) being switched to limit
the current through the input structure.
9.3.3 Enable Function
The Enable (EN) pin of the UCC2753x has an internal pull-up resistor to an internal reference voltage so leaving
Enable floating turns on the driver and allows it to send output signals properly. If desired, the Enable can also
be driven by low-voltage logic to enable and disable the driver.
9.3.4 Output Stage
The output stage of the UCC2753x device is illustrated in Figure 39. The UCC2753x device features a unique
architecture on the output stage which delivers the highest peak source current when it is most needed during
the Miller plateau region of the power switch turn-on transition (when the power switch drain/collector voltage
experiences dV/dt). The device output stage features a hybrid pull-up structure using a parallel arrangement of
N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant
when the output changes state from low to high, the gate driver device is able to deliver a brief boost in the peak
sourcing current enabling fast turnon.
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Feature Description (continued)
VDD
ROH
RNMOS ,Pull Up
Anti ShootThrough
Circuitry
Input Signal
OUTH
OUTL
Narrow Pulse at
each Turn On
ROL
Figure 39. UCC27531 Gate Driver Output Stage
Split output depicted in Figure 39. For devices with single OUT pin, OUTH and OUTL are connected internally
and then connected to OUT.
The ROH parameter (see Electrical Table) is a DC measurement and it is representative of the on-resistance of
the P-Channel device only, because the N-Channel device is turned on only during output change of state from
low to high. Thus the effective resistance of the hybrid pull-up stage is much lower than what is represented by
ROH parameter. The pull-down structure is composed of a N-channel MOSFET only. The ROL parameter (see
Electrical Characteristics), which is also a DC measurement, is representative of true impedance of the pull-down
stage in the device. In UCC2753x, the effective resistance of the hybrid pull-up structure is approximately 3 x
ROL.
The UCC2753x can deliver 2.5-A source, and up to 5-A sink at VDD = 18 V. Strong sink capability results in a
very low pull-down impedance in the driver output stage which boosts immunity against the parasitic Miller turnon (high slew rate dV/dt turnon) effect that is seen in both IGBT and FET power switches .
An example of a situation where Miller turnon is a concern is synchronous rectification (SR). In SR application,
the dV/dt occurs on MOSFET drain when the MOSFET is already held in OFF state by the gate driver. The
current charging the CGD Miller capacitance during this high dV/dt is shunted by the pull-down stage of the driver.
If the pull-down impedance is not low enough then a voltage spike can result in the VGS of the MOSFET, which
can result in spurious turnon. This phenomenon is illustrated in Figure 40.
VDS
VIN
Miller Turn -On Spike in V GS
C GD
Gate Driver
RG
COSS
ISNK
CGS
ROL
VTH
VGS of
MOSFET
ON OFF
VIN
VDS of
MOSFET
Figure 40. Low Pull-Down Impedance in UCC2753x
(Output Stage Mitigates Miller Turn-On Effect)
20
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Feature Description (continued)
The driver output voltage swings between VDD and GND providing rail-to-rail operation because of the low
dropout of the output stage. In many cases, the external Schottky diode clamps may be eliminated because the
presence of the MOSFET body diodes offers low impedance to switching overshoots and undershoots.
9.4 Device Functional Modes
The UCC2753x devices operate in normal mode and UVLO mode (see VDD Undervoltage Lockout section for
information on UVLO operation). In normal mode, the output state is dependent on the states of the device, and
the input pins.
The UCC27531 features a single, non-inverting input, but also contains enable and disable functionality through
the EN pin. Setting the EN pin to logic HIGH will enable the non-inverting input to output on the IN pin. The
device uses a split output (OUTH, and OUTL) to allow for separate sourcing and sinking pins, which can help
reduce ground de-bouncing.
The UCC27533 features a dual input. One inverting (IN+), and one non-inverting (IN–). This device does not
contain an enable feature, and has a single output.
The UCC27536 is similar to the UCC27531, but uses an inverting input, and a single output.
The UCC27537 is also similar to the UCC27531, but uses a single output.
The UCC27538 is again similar to the UCC27531, but features dual inputs IN1 and IN2, rather than an enable
and disable feature.
The UCC27531D features a single input and a single output. The device is always enabled.
See Table 2, Table 4, and Table 5 for lists of the output states of the different devices and their inputs:
Table 2. Input/Output Logic Truth Table (For Single Output Driver)
EN PIN
OUTH PIN
OUTL PIN
OUT
(OUTH and OUTL pins
tied together)
L
L
High-Impedance
L
L
L
H
High-Impedance
L
L
H
L
High-Impedance
L
L
H
H
H
High-Impedance
H
H
FLOAT
H
High-Impedance
H
FLOAT
H
High-Impedance
L
L
IN PIN
UCC27531DBV
Table 3. Input/Output Logic Truth Table (For Single Output Driver with Enable Pin)
EN PIN
IN- / IN+ PIN
OUT PIN
L
L
L
L
H
L
H
L
H
H
H
L
H
X
L
L
L
L
L
UCC27536DBV
UCC27537DBV
L
H
H
L
L
H
H
H
H
X
L
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Table 4. Input/Output Logic Truth Table
IN+ PIN
IN- PIN
OUT PIN
L
L
L
L
H
L
H
L
H
H
H
L
FLOAT
X
L
X
FLOAT
L
UCC27533DBV
Table 5. Input/Output Logic Truth Table (For Single Output Driver)
IN2 PIN
OUTH PIN
OUTL PIN
OUT
(OUTH and OUTL pins
tied together)
L
L
High-Impedance
L
L
L
IN1 PIN
UCC27538DBV
L
H
High-Impedance
L
H
L
High-Impedance
L
L
H
H
H
High-Impedance
H
X
FLOAT
High-Impedance
L
L
FLOAT
X
High-Impedance
L
L
Table 6. Input/Output Logic Truth Table (For Single Input/Output Driver)
IN PIN
OUT PIN
L
L
H
H
FLOAT
L
UCC27531D
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
High-current gate driver devices are required in switching power applications for a variety of reasons. To enable
fast switching of power devices and reduce associated switching power losses, a powerful gate driver can be
employed between the PWM output of controllers or signal isolation devices and the gates of the power
semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the
PWM controller directly drive the gates of the switching devices. The situation will be often encountered because
the PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not
capable of effectively turning on a power switch. A level-shifting circuitry is needed to boost the logic-level signal
to the gate-drive voltage in order to fully turn on the power device and minimize conduction losses. Traditional
buffer drive circuits based on NPN/PNP bipolar, (or P- N-channel MOSFET), transistors in totem-pole
arrangement, being emitter follower configurations, prove inadequate for this because they lack level-shifting
capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting, buffer drive
and UVLO functions. Gate drivers also find other needs such as minimizing the effect of switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses into itself.
The UCC2753x is very flexible in this role with a strong current drive capability and wide supply voltage range up
to 32 V. This allows the driver to be used in 12-V Si MOSFET applications, 20-V and -5-V (relative to Source)
SiC FET applications, 15-V and -15-V (relative to Emitter) IGBT applications and many others. As a singlechannel driver, the UCC2753x can be used as a low-side or high-side driver. To use as a low-side driver, the
switch ground is usually the system ground so it can be connected directly to the gate driver. To use as a highside driver with a floating return node however, signal isolation is needed from the controller as well as an
isolated bias to the UCC2753x. Alternatively, in a high-side drive configuration the UCC2753x can be tied directly
to the controller signal and biased with a nonisolated supply. However, in this configuration the outputs of the
UCC2753x must drive a pulse transformer which then drives the power-switch to work properly with the floating
source and emitter of the power switch. Further, having the ability to control turn-on and turn-off speeds
independently with both the OUTH and OUTL pins ensures optimum efficiency while maintaining system
reliability. These requirements coupled with the need for low propagation delays and availability in compact, lowinductance packages with good thermal capability makes gate driver devices such as the UCC2753x extremely
important components in switching power combining benefits of high-performance, low cost, component count
and board space reduction and simplified system design.
Copyright © 2012–2019, Texas Instruments Incorporated
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23
UCC27531, UCC27533, UCC27536, UCC27537, UCC27538
SLUSBA7G – DECEMBER 2012 – REVISED JUNE 2019
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10.2 Typical Application
10.2.1 Driving IGBT Without Negative Bias
UCC27531
EN
OUTH
1
6
IN
OUTL
+
2
5
VDD
GND
3
+
–
4
GND
Bouncing Up
to -6.5 V
18 V
ISENSE
Controller
VCE(sense)
VCC
+
–
Figure 41. Driving IGBT Without Negative Bias
10.2.1.1 Design Requirements
When selecting the proper gate driver device for an end application, some design considerations must be
evaluated first in order to make the most appropriate selection. The following design parameters should be used
when selecting the proper gate driver device for an end application: input-to-output configuration, the input
threshold type, bias supply voltage levels, peak source and sink currents, availability of independent enable and
disable functions, propagation delay, power dissipation, and package type. See the example design parameters
and requirements in Table 7.
Table 7. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
IN-OUT configuration
Noninverting
Input threshold type
CMOS
Bias supply voltage levels
+18 V
Negative output low voltage
N/A
dVDS/dt
(1)
24
(1)
20 V/ns
Enable function
Yes
Disable function
N/A
Propagation delay
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