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UCC28063
SLUSAO7B – SEPTEMBER 2011 – REVISED NOVEMBER 2016
UCC28063 Natural Interleaving™ Transition-Mode PFC Controller With Improved Audible
Noise Immunity
1
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Filter and Output Capacitor Ripple-Current
Cancellation
– Reduced Current Ripple for Higher System
Reliability and Smaller Bulk Capacitor
– Reduced EMI Filter Size
Phase Management Capability
Fail-Safe OVP with Dual Paths Prevents Output
Overvoltage Conditions by Voltage-Sensing
Failures
Sensorless Current-Shaping Simplifies Board
Layout and Improves Efficiency
Advanced Audible Noise Performance
Non-linear Error-Amplifier Gain
Soft Recovery on Overvoltage
Integrated Brownout and Dropout Handling
Reduced Bias Currents
Improved Efficiency and Design Flexibility Over
Traditional Single-Phase Continuous Conduction
Mode (CCM)
Inrush-Safe Current Limiting:
– Prevents MOSFET Conduction During Inrush
– Eliminates reverse Recovery Events in Output
rectifiers
Enables Use of Low-Cost Diodes Without
Extensive Snubber Circuitry
Improved Light-Load Efficiency
Fast, Smooth Transient Response
Expanded System-Level Protections
Typical Application Diagram
EMI
Filter
•
•
1-A Source/1.8-A Sink Gate Drivers
–40°C to 125°C Operating Temperature Range in
a 16-Lead SOIC Package
2 Applications
•
•
•
•
•
•
100-W to 800-W Power Supplies
Gaming
D-to-A Set-Top Boxes
Adapters
LCD, Plasma and DLP™ TVs
Home Audio Systems
3 Description
Optimized for consumer applications concerned with
audible noise elimination, this solution extends the
advantages of transition mode – high efficiency with
low-cost components – to higher power ratings than
previously possible. By utilizing a Natural
Interleaving™ technique, both channels operate as
masters (that is, there is no slave channel)
synchronized to the same frequency. This approach
delivers inherently strong matching, faster responses,
and ensures that each channel operates in transition
mode.
Device Information(1)
PART NUMBER
UCC28063
5
3
VINAC
TSET
ZCDB
1
GDB 11
PWMCNTL
9
VSENSE
2
PHB
4
COMP
5
Power Good to
Down Stream
Converter
Phase Management
15 VREF
HVSEN
AGND
PGND
6
13
Capacitor ripple current (A)
7
ZCDA 16
GDA 14
10 CS
9.90 mm × 3.91 mm
Ripple Current Reduction
+
12 VCC
SOIC (16)
Input Ripple Current Reduction with Interleaving
UCC28063
85 VAC to 265 VAC
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
400 VDC
–
PACKAGE
POUT = 600 W
VOUT = 400 V
4
1-phase TM
3
1-phase CCM
2
2-phase TM Interleave
8
1
70
120
170
220
Input Voltage (V)
270
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28063
SLUSAO7B – SEPTEMBER 2011 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
5
5
5
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 26
9
Applications and Implementation ...................... 27
9.1 Application Information............................................ 27
9.2 Typical Application .................................................. 27
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 35
12 Device and Documentation Support ................. 36
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
38
38
38
38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
Changes from Revision A (December 2014) to Revision B
•
Added GDA, GDB Absolute Maximum ratings. ..................................................................................................................... 4
Changes from Original (September 2011) to Revision A
•
2
Page
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
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SLUSAO7B – SEPTEMBER 2011 – REVISED NOVEMBER 2016
5 Description (Continued)
Expanded system level protections feature input brownout and dropout recovery, output over-voltage, open-loop,
overload, soft-start, phase-fail detection, and thermal shutdown. The additional FailSafe over-voltage protection
(OVP) feature protects against shorts to an intermediate voltage that, if undetected, could lead to catastrophic
device failure. Advanced non-linear gain results in rapid, yet smoother response to line and load transient events.
Reduced bias currents improve stand-by power efficiency. Special line-dropout handling avoids significant current
disruption and minimizes audible-noise generation.
6 Pin Configuration and Functions
D Package
16-Pin SOIC
Top View
ZCDB
1
16
ZCDA
VSENSE
2
15
VREF
TSET
3
14
GDA
PHB
4
13
PGND
COMP
5
12
VCC
AGND
6
11
GDB
VINAC
7
10
CS
HVSEN
8
9
PWMCNTL
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
6
-
Analog Ground
COMP
5
O
Error Amplifier Output
CS
10
I
Current Sense Input
GDA
14
O
GDB
11
O
HVSEN
8
I
High Voltage Output Sense
PHB
4
I
Phase-B Enable/Disable
PWMCNTL
9
O
PWM-Control Output
TSET
3
I
Timing Set
VCC
12
-
Bias Supply Input
Channel A and Channel B Gate Drive Output
VINAC
7
I
Input AC Voltage Sense
VREF
15
O
Voltage Reference Output
VSENSE
2
I
Output DC Voltage Sense
ZCDA
16
I
ZCDB
1
I
Zero Current Detection Inputs
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UCC28063
SLUSAO7B – SEPTEMBER 2011 – REVISED NOVEMBER 2016
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings (1)
All voltages are with respect to GND, −40 °C < TJ = TA < 125 °C, currents are positive into and negative out of the specified
terminal, unless otherwise noted.
Continuous input voltage
range
MIN
MAX
VCC (2)
−0.5
21
PWMCNTL
−0.5
20
COMP (3), PHB, HVSEN (4), VINAC (4), VSENSE (4)
–0.5
7
ZCDA, ZCDB
–0.5
4
CS (5)
–0.5
3
–0.5
VCC+0.3
GDA, GDB
Continuous input current
±5
–30
Output current
VREF
TSOL
Lead Temperature
Tstg
Storage temperature
(5)
(6)
10
CS
Junction Temperature
(3)
(4)
20
PWMCNTL
ZCDA, ZCDB
TJ
(2)
VCC
Peak input current
Continuous gate current
(1)
(6)
GDA, GDB
UNIT
V
mA
–10
(6)
±25
Operating
–40
125
Storage
–65
150
Soldering, 10s
°C
260
–40
125
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
Voltage on VCC is internally clamped. VCC may exceed the continuous absolute maximum input voltage rating if the source is current
limited below the absolute maximum continuous VCC input current level.
In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.
In normal use, VINAC, VSENSE, and HVSEN are connected to high-value resistors and are internally limited in negative-voltage swing.
Although not recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as -10mA from negative
voltage sources, and input currents as high as +0.5mA from positive voltage sources.
In normal use, CS is connected to a series resistor to limit peak input current during brief system line-inrush conditions. In these
situations, negative voltage on CS may exceed the continuous absolute maximum rating.
No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to
damp resonant ringing due to stray inductance.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
All voltages are with respect to GND, −40 °C < TJ = TA < 125 °C, currents are positive into and negative out of the specified
terminal, unless otherwise noted.
MIN
MAX
VCC input voltage from a low-impedance source
14
21
VCC input current from a high-impedance source
8
18
VREF load current
0
–2
VINAC input voltage
ZCDA, ZCDB series resistor
TSET resistor to program PWM on-time
HVSEN input voltage
0
6
20
80
66.5
400
0.8
4.5
UNIT
V
mA
V
kΩ
V
7.4 Thermal Information
UCC28063
THERMAL METRIC (1)
SOIC (D)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance (2)
91.6
RθJC(top)
Junction-to-case (top) thermal resistance (3)
52.1
RθJB
Junction-to-board thermal resistance (4)
48.6
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
(1)
(2)
(3)
(4)
(5)
(6)
°C/W
14.9
48.3
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
7.5 Electrical Characteristics
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R TSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40 °C < TJ = TA < 125 °C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC BIAS SUPPLY
VCCSHUNT
VCC shunt voltage (1)
IVCC = 10 mA
IVCC(ULVO)
VCC current, UVLO
VCC = 11.4 V prior to turn-on
IVCC(stby)
VCC current, disabled
IVCC(on)
VCC current, enabled
22
24
26
95
200
VSENSE = 0 V
100
200
VSENSE = 2 V
5
8
11.5
12.6
13.5
V
µA
mA
UNDERVOLTAGE LOCKOUT (UVLO)
VCCON
VCC turn-on threshold
VCC rising
VCCOFF
VCC turn-off threshold
VCC falling
UVLO Hysteresis
9.5
10.35
11.5
1.85
2.15
2.45
5.82
6.00
6.18
V
REFERENCE
VREF
(1)
VREF output voltage, no load
IVREF = 0 mA
V
Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply.
If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended.
See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.
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Electrical Characteristics (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R TSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40 °C < TJ = TA < 125 °C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VREF change with load
0 mA ≤ IVREF ≤ −2 mA
VREF change with VCC
12 V ≤ VCC ≤ 20 V
MIN
TYP
MAX
−1
−6
2
10
5.85
6
6.15
5.82
6
6.18
50
100
150
1.15
1.25
1.35
0.02
0.07
0.15
4.70
4.95
5.10
0.03
0.125
40
55
70
3.25%
5%
6.75%
−3.25%
−5%
−6.75%
UNIT
mV
ERROR AMPLIFIER
VSENSEreg25 VSENSE input regulation
voltage
VSENSEreg
VSENSE input regulation
voltage
IVSENSE
VSENSE input bias current
VENAB
VSENSE enable threshold,
rising
TA = 25 °C
V
In regulation
VSENSE enable hysteresis
VCOMPCLMP
gM
COMP high voltage, clamped
VSENSE = VSENSEreg – 0.3 V
COMP low voltage, saturated
VSENSE = VSENSEreg + 0.3 V
VSENSE to COMP
transconductance, small signal
0.99(VSENSEreg) < VSENSE <
1.01(VSENSEreg), COMP = 3 V
VSENSE high-going threshold
to enable COMP large signal
gain, percent
Relative to VSENSEreg, COMP = 3 V
VSENSE low-going threshold to Relative to VSENSEreg, COMP = 3 V
enable COMP large signal gain,
percent
V
µS
VSENSE to COMP
transconductance, large signal
VSENSE = VSENSEreg – 0.4 V ,
COMP = 3 V
210
290
370
VSENSE to COMP
transconductance, large signal
VSENSE = VSENSEreg + 0.4 V,
COMP = 3 V
210
290
370
−80
−125
−170
µA
1.6
2
2.4
kΩ
3.2
4
4.8
µA
7%
8%
10%
−1.5%
−2%
−3%
10.5%
11.3%
14%
15
23
30
µS
COMP maximum source current VSENSE = 5 V, COMP = 3 V
RCOMPDCHG
COMP discharge resistance
HVSEN = 5.2 V, COMP = 3 V
IDODCHG
COMP discharge current during
Dropout
VSENSE = 5 V, VINAC = 0.3 V
VLOW_OV
VSENSE over-voltage
threshold, rising
Relative to VSENSEreg
VSENSE over-voltage
hysteresis
Relative to VLOW_OV
VSENSE 2nd over-voltage
threshold, rising
Relative to VSENSEreg
VSSTHR
COMP Soft-Start threshold,
falling
VSENSE = 1.5 V
ISS,FAST
COMP Soft-Start current, fast
SS-state, VENAB < VSENSE < VREF/2
ISS,SLOW
COMP Soft-Start current, slow
SS-state, VREF/2 < VSENSE < 0.88VREF
KEOSS
VSENSE End-of-Soft-Start
threshold factor
Percent of VSENSEreg
VHIGH_OV
nA
SOFT START
−80
−125
−170
−11.5
−16
−20
96.5%
98.3%
99.8%
2.35
2.50
2.65
±0.03
±0.5
11.4
14
mV
µA
OUTPUT MONITORING
VPWMCNTL
HVSEN threshold to PWMCNTL HVSEN rising
IHVSEN
HVSEN input bias current, high
HVSEN = 3 V
IHV_HYS
HVSEN hysteresis bias current,
low
HVSEN = 2 V
6
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9.2
V
µA
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SLUSAO7B – SEPTEMBER 2011 – REVISED NOVEMBER 2016
Electrical Characteristics (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R TSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40 °C < TJ = TA < 125 °C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VHV_OV_FLT
HVSEN threshold to overvoltage fault
HVSEN rising
VHV_OV_CLR
HVSEN threshold to overvoltage clear
HVSEN falling
VCOMP_PHFOFF
Phase Fail monitoring-disable
threshold
COMP falling
VCOMP_PHFHYS
Phase Fail monitoring
hysteresis
COMP rising
PWMCNTL output voltage low
HVSEN = 3 V, IPWMCNTL = 5 mA,
COMP = 0 V
tPHFDLY
Phase Fail filter time to
PWMCNTL high
PHB = 5 V, ZCDA switching,
ZCDB = 0.5 V, COMP = 3 V
IPWMCNTL_LEAK
PWMCNTL leakage current,
high
HVSEN = 2 V, PWMCNTL = 15 V
GDA, GDB output voltage, high
IGDA, IGDB = −100 mA
GDA, GDB on-resistance, high
IGDA, IGDB = −100 mA
GDA, GDB output voltage, low
IGDA, IGDB = 100 mA
GDA, GDB on-resistance, low
IGDA, IGDB = 100 mA
GDA, GDB output voltage high,
clamped
VCC = 20 V, IGDA, IGDB = −5 mA
GDA, GDB output voltage high,
low VCC
VCC = 12 V, IGDA, IGDB = −5 mA
Rise time
Fall time
GDA, GDB output voltage,
UVLO
VCC = 3.0 V, IGDA, IGDB = 2.5 mA
GATE DRIVE
MIN
TYP
MAX
4.64
4.87
5.1
4.45
4.67
4.8
0.21
0.225
0.25
UNIT
V
0.051
0.2
0.5
12
17
ms
±0.03
±0.5
µA
12.4
15
V
8.8
14
Ω
0.18
0.32
V
2
3.2
Ω
12
13.5
15
10
10.5
11.5
1 V to 9 V, CLOAD = 1 nF
18
30
9 V to 1 V, CLOAD = 1 nF
12
25
100
200
7.9
(2)
11.5
V
ns
mV
ZERO CURRENT DETECTOR
ZCDA, ZCDB voltage threshold,
falling
0.8
1
1.2
ZCDA, ZCDB voltage threshold,
rising
1.5
1.7
1.9
ZCDA, ZCDB clamp, high
IZCDA = +2 mA, IZCDB = +2 mA
2.6
3
3.4
ZCDA, ZCDB clamp, low
IZCDA = −2 mA, IZCDB = −2 mA
0
−0.2
−0.4
ZCDA, ZCDB input bias current
ZCDA = 1.4 V, ZCDB = 1.4 V
±0.03
±0.5
ZCDA, ZCDB delay to GDA,
GDB outputs (2)
From ZCDx input falling to 1 V to
respective gate drive output rising 10%
50
100
ZCDA blanking time (3)
From GDA rising and GDA falling
100
ZCDB blanking time (3)
From GDB rising and GDB falling
100
V
µA
ns
CURRENT SENSE
CS input bias current, dualphase
(2)
(3)
At rising threshold
−120
−166
−200
CS current-limit rising threshold, PHB = 5 V
dual-phase
−0.18
−0.2
−0.22
CS current-limit rising threshold, PHB = 0 V
single-phase
−0.149
−0.166
−0.183
CS current-limit reset falling
threshold
−0.003
–0.015
−0.025
µA
V
Refer to Figure 13, Figure 14, Figure 15, and Figure 16 of the Typical Characteristics for typical gate drive waveforms.
ZCD blanking times are ensured by design.
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Electrical Characteristics (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R TSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40 °C < TJ = TA < 125 °C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
CS current-limit response
time (2)
From CS exceeding threshold−0.05 V to
GDx dropping 10%
CS blanking time
From GDx rising and falling edges
IVINAC
VINAC input bias current,
above brownout
VINAC = 2 V
VBODET
VINAC brownout detection
threshold
VINAC falling
tBODLY
VINAC brownout filter time
VINAC below the brownout detection
threshold for the brownout filter time
VBOHYS
VINAC brownout threshold
hysteresis
VINAC rising
IBOHYS
VINAC brownout hysteresis
current
VINAC = 1 V for > tBODLY
VDODET
VINAC dropout detection
threshold
VINAC falling
tDODLY
VINAC dropout filter time
VINAC below the dropout detection
threshold for the dropout filter time
VDOCLR
VINAC dropout clear threshold
VINAC rising
TYP
MAX
60
UNIT
100
ns
100
VINAC INPUT
±0.03
±0.5
µA
1.33
1.39
1.44
V
340
440
540
ms
30
62
75
mV
1.6
2
2.5
µA
0.315
0.35
0.38
V
3.5
5
7
0.67
0.71
0.75
ms
V
PULSE-WIDTH MODULATOR
KT
On-time factor, phases A and B
VSENSE = 5.8 V (4)
3.6
4.0
4.4
KTS
On-time factor, single-phase, A
VSENSE = 5.8 V, PHB = 0 V (4)
7.2
8.0
8.9
Phase B to phase A on-time
matching error
VSENSE = 5.8 V
±2%
±6%
Zero-crossing distortion
correction additional on time
COMP = 0.25 V, VINAC = 1 V
VPHBF
PHB threshold falling, to singlephase operation
To GDB output shutdown, VINAC = 1.5 V
VPHBR
PHB threshold rising, to twophase operation
To GDB output running, VINAC = 1.5 V
TMIN
Minimum switching period
RTSET = 133 kΩ (4)
1.7
2.2
3
TSTART
PWM restart time
ZCDA = ZCDB = 2 V (5)
165
210
265
COMP = 0.25 V, VINAC = 0.1 V
1.2
2
2.8
12.6
20
29
0.7
0.8
0.9
0.9
1
1.1
µs/V
µs
V
µs
THERMAL SHUTDOWN
TJ
TJ
(4)
(5)
(6)
8
Thermal shutdown temperature
Thermal restart temperature
Temperature rising (6)
160
(6)
140
Temperature falling
°C
Gate drive on-time is proportional to (VCOMP – 0.125 V). The on-time proportionality factor, KT, scales linearly with the value of RTSET
and is different in two-phase and single-phase modes. The minimum switching period is proportional to RTSET.
An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart
time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.
Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating
temperature is not specified or assured.
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7.6 Typical Characteristics
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R TSET = 133 kΩ;
all voltages are with respect to GND, all outputs unloaded, TJ = TA = +25 °C, and currents are positive into and
negative out of the specified terminal, unless otherwise noted.
10
10
Enabled
IVCC − Bias Supply Current (mA)
IVCC − Bias Supply Current (mA)
Enabled
1
VCC Turn OFF
VCC Turn ON
0.1
Disabled
0.01
0
2
4
6
8
10
12
14
16
VCC − Bias Supply Voltage (V)
18
1
0.1
Disabled
0.01
−40
20
−20
0
20
40
60
80
TJ − Temperature (°C)
100
G000
Figure 1. Bias Supply Current vs Bias Supply Voltage
120
G001
Figure 2. Bias Supply Current vs Temperature
6.10
150
6.08
125
IVSENSE − Input Bias Current (nA)
VREF Reference Voltage (V)
6.06
6.04
6.02
6.00
5.98
5.96
100
75
50
5.94
25
5.92
5.90
−40
−20
0
20
40
60
80
TJ − Temperature (°C)
100
0
120
0
1
2
3
4
VVSENSE − Input Voltage (V)
5
6
G002
G003
IVREF = 0 to –2 mA
Figure 4. VSENSE Input Bias Current vs Input Voltage
150
300
100
250
LOW_OV
Trigger
Transconduction 54 µS
50
gM − Transconductance (µS)
ICOMP − Output Current (µA)
Figure 3. Reference Voltage vs Temperature
LOW_OV
Clear
0
−50
−100
−150
5.0
200
150
100
50
5.2
5.4
5.6 5.8 6.0 6.2 6.4
VVSENSE − Input Voltage (V)
6.6
6.8
0
5.0
7.0
G004
5.2
5.4
5.6 5.8 6.0 6.2 6.4
VVSENSE − Input Voltage (V)
6.6
6.8
7.0
G005
Soft-Start Completed
Figure 5. Error Amplifier Output Current vs Input Voltage
Figure 6. Error Amplifier Transconductance vs VSENSE
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Typical Characteristics (continued)
60
20
58
15
VVSENSE = 6.2 V
56
ICOMP − Output Current (µA)
gM − Transconductance (µS)
10
54
52
50
48
46
VVSENSE = 6.1 V
5
0
VVSENSE = 5.9 V
−5
VVSENSE = 5.8 V
−10
44
−15
42
40
−40
−20
0
20
40
60
80
TJ − Temperature (°C)
100
−20
120
0
1
2
3
VCOMP − Output Voltage (V)
4
5
G006
G007
5.9 V < VVSENSE < 6.1 V
Figure 7. Error Amplifier Transconductance vs Temperature
9
9
8
RTSET = 266 kΩ
8
KTL
KTL - On-Time Factor (µs/V)
KT - On-Time Factor (µs/V)
Figure 8. Error Amplifier Output Current vs Output Voltage
10
7
6
5
4
3
7
6
5
RTSET = 133 kΩ
4
3
2
2
RTSET = 66 kΩ
1
1
0
0
60
80 100 120 140 160 180 200 220 240 260 280
-40
-20
0
RTSET - Time Setting Resistor (kΩ)
Figure 9. On-Time Factor vs Time Setting Resistor
100
GDA
80
100
120
RTSET = 133 kΩ
Additional On-Time (µs)
104
60
RTSET = 266 kΩ
GDB
RTSET = 133 kW
106
KT/KT0 (%)
RTSET = 266 kW
40
Figure 10. On-Time Factor Phase A and B vs Temperature
110
108
20
TJ - Temperature (°C)
RTSET = 66 kW
102
100
98
96
RTSET = 66 kΩ
10
1
94
92
0.1
90
150
160
170
180
190
200
210
Phase Shift of GDA Relative to GDB (Degrees)
0
0.5
1.0
1.5
2.0
2.5
3.0
VVINAC - Input AC Voltage Sense (V)
KTO = 2(KTA × KTB) / KTA + KTB
Figure 11. On-Time Factor vs Phase Error
10
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Figure 12. Additional On Time vs VINAC
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3.0
14
3.0
12
2.5
12
2.5
2.0
GD Source Current:
VCC = 20 V
VCC = 12 V
6
1.5
1.0
4
0.5
2
0
0
-2
0
50
100
150
200
250
300
10
2.0
GD Sink Current:
VCC = 20 V
VCC = 12 V
8
6
1.0
4
0.5
2
-0.5
0
-1.0
-2
0
GD Voltage:
VCC = 20 V
VCC = 12 V
-0.5
-1.0
350
0
20
40
60
Time (ns)
80
100
120
140
Time (ns)
CLOAD = 4.7 nF
CLOAD = 4.7 nF
Figure 13. Gate Drive Rising vs Time
Figure 14. Gate Drive Falling vs Time
500
14
6
12
400
12
10
300
10
200
8
GD Output:
TJ = –40°C
TJ = +25°C
TJ = +125°C
4
8
3
6
2
4
1
2
0
Current Sense Input (mV)
14
Gate Drive Output (V)
7
5
ZCD Input (V)
1.5
CS Input
Voltage
100
6
GD Output:
TJ = -40°C
TJ = +25°C
TJ = +125°C
0
4
-100
2
0
-200
0
-2
-300
Gate Drive Output - V
8
GD Voltage:
VCC = 20 V
VCC = 12 V
Gate Drive Output (V)
Gate Drive Output (V)
10
Gate Drive Source Current (A)
14
Gate Drive Source Current (A)
Typical Characteristics (continued)
ZCD Input Voltage
-1
-25 0
50
100
150
200
250
-2
-25 0
300
50
100
150
200
250
300
Time (ns)
Time (ns)
CLOAD = 4.7 nF
CLOAD = 4.7 nF
Figure 15. Gate Drive Rising and Delay From ZCD Input vs
Time
Figure 16. Gate Drive Falling and Delay From CS Input vs
Time
15
15
14
TJ = –40°C
13
13
TJ = +125°C
12
TJ = +25°C
11
10
Gate Drive Voltage (V)
Gate Drive Voltage (V)
14
Clamped VCC ≥ 15 V
12
11
Unclamped VCC = 12 V
10
9
8
7
9
6
5
8
10
11
12
13
14
15
16
17
18
19
-40
20
VCC - Bias Supply Voltage (V)
-20
0
20
40
60
60
100
120
TJ - Temperature (°C)
RLOAD = 2.7 kΩ
RLOAD = 2.7 kΩ
Figure 17. Gate Drive Output High vs VCC
Figure 18. Gate Drive High Voltage vs Temperature
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Typical Characteristics (continued)
320
2.5
Load = 10 mA
280
Load = 5 mA
2.0
VOL − Gate Drive Voltage (V)
VOL − Gate Drive Voltage (mV)
240
200
160
120
80
1.5
1.0
Load = 2.5 mA
Load = 1.0 mA
0.5
40
0
−40
−20
0
20
40
60
80
TJ − Temperature (°C)
100
0.0
120
0
1
2
3
VCC − Bias Supply Voltage (V)
4
G008
G009
Load = 100 mA
Figure 19. Gate Drive Low Voltage vs Temperature
Figure 20. Gate Drive Low Voltage in UVLO vs Bias Supply
Voltage
1000
3.5
3.0
Brownout Filter Delay
2.5
VZCD − Clamp Voltage (V)
Delay Time (ms)
100
Phase−Fail Filter Delay
10
Dropout Filter Delay
2.0
1.5
1.0
1
0.5
Restart Time Delay
0.1
−40
−20
0
20
40
60
80
TJ − Temperature (°C)
0.0
100
−0.5
120
−5
−4
−3
−2
−1
0
1
2
IZCD − Input Current (mA)
3
4
G010
Figure 21. Various Delay Times vs Temperature
5
G011
Figure 22. Zero Current Detect Clamp Voltage vs Input
Current
−150
0
−155
ICS − Input Current (µA)
ICS − Input Bias Current (µA)
−50
−160
−165
−170
−175
−100
−150
Single−Phase Mode
Dual−Phase Mode
−180
−200
−185
−190
−40
−20
0
20
40
60
80
TJ − Temperature (°C)
100
120
−250
−300
G012
−250
−200
−150
−100
VCS − Input Voltage (mV)
−50
0
G013
VCS = –195 mV
Figure 23. Current Sense Input Bias Current vs Temperature
12
Figure 24. Current Sense Input Bias Current vs Input
Voltage
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8 Detailed Description
8.1 Overview
Transition Mode Control is the most popular choice for the Boost Power Factor Correction topology at lower
power levels because of its lower complexity in achieving high power factor while at the same time not placing
demanding requirements on the power component specifications. A lower cost boost diode with higher reverse
recovery current specification may be used, for instance, in the Transition Mode Boost. Interleaved Transition
Mode Control retains this benefit and generally extends the applicability up to much higher power levels while
simultaneously conferring the interleaving benefits of reduced input and output ripple, phase management for
light load efficiency enhancement, redundancy, system thermal optimization and low profile or planar solutions.
The UCC28063 enables a very cost effective solution with a particular focus on ruggedness, fault management,
fault recovery, efficiency and higher end performance in areas such as acoustic management and fast transient
response. It may be regarded as an enhanced and new generation UCC28061.
Interleaving control and phase management facilitates 80+ and Energy Star designs with reduced input and
output ripple. The Natural Interleaving method allows TM operation and achieves 180 degrees between the
phases by On-time management and does not rely on tight tolerance requirements on the inductors. The
Crossover Notch Reduction block implements a non-linear current shaping characteristic on the instantaneous
voltage sense (VINAC) in order to reduce distortion and increase Power Factor. Negative current sensing is
implemented on the total input current instead of just the MOSFET current which prevents MOSFET switching
during inrush surges or in any mode where the inductor current may become substantially continuous (CCM).
This prevents reverse recovery conduction events between the MOSFET and output rectifier. Downstream power
stage management is facilitated by the PWMCNTL signal. This open drain signal provides an enable with
hysteresis for a downstream converter when the PFC stage voltage is above an operating threshold, FailSafe OV
protection is not in operation and there is no PhaseFail fault.
Independent output voltage sense chains with their separate fault management behaviors provide a high degree
of redundancy against PFC stage overvoltage. Brown-Out, HVSENSE OV, UVLO, Open/ Fault detect on TSET,
Open on CS and IC Overtemperature will all cause a complete Soft-Start cycle. Other faults such as short
duration AC Drop-Out, minor overvoltage or cycle-by-cycle overcurrent cause a live recovery process to initiate
by pulling down on the COMP pin or by terminating the pulses early.
In general IC operation is designed to ensure smooth and acoustic noise free start-up, good transient response
behavior and well behaved recovery from faults. The Error amplifier transconductance is designed to allow
smaller compensation components and optimum transient response for larger deviations. The Soft-Start process
is carefully optimized. A complete Soft Start is implemented on recovery from every fault, for consistency. The
Soft Start speed is dependent on the output voltage sense to speed up start-up from low AC line and to minimize
the effect of excessive "COMP" during start-up into no-load. This complete discharge of COMP aids with
preventing excessive currents on recovery from an AC Brown-Out event.
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8.2 Functional Block Diagram
Overcurrent
+
100ns
Blanking
Open
Detection
CS_OPEN
VINAC
BROWNOUT
HVSEN_OV
UVLO
EN
OC
TSET_FLT
CS_OPEN
TSD
Brownout Detection
7
440ms Delay
50mV
Q
STOP_GDA
S
Q
STOP_GDB
OC
HIGH _OV
PHASE_B_OFF
12 VCC
UVLO
12.6V /
10.35V
+
BROWNOUT
+
1.4V
COMP_DSCHG
R
6.00V
Reg.
-0.200 V /
-0.015V
CS 10
DSCHG _RST
1-PHASE
VGD
Reg.
-0.167 V /
-0.015V
24V
Thermal ShutDown
5ms Delay
PHASE_B_OFF
TSET_FLT
100ns
Blanking
Crossover
Notch
Reduction
+
+
20mV
VCC
Phase B
On-Time Control
HIGH_OV
6.67V
+
ZCA
LOW_OV
120mV
6.48V
EA Gain Control
for Soft-Start
and Dropout
EN
50mV
+
1.25V
TON Modulation
DIS_EA
DIS_High_Gain
ZCB
+
272mV /
222 mV
gM
50μS /
250μS
100nA
1.0V /
0.8V
11 GDB
STOP_GDB
+
8
HVSEN
9
PWMCNTL
4.87V /
4.67V
+
2.5V
12μA
2
VREF
13.5V
HVSEN_OV
PhaseFail
VSENSE
PGND
13 PGND
LOW_OV
COMP_DSCHG
2k
4μA
+
14 GDA
Interleave
Control
Trigger
DROPOUT
DSCHG_RST
STOP_GDA
ZCB
100ns
Blanking
TON Basis
1
Clamping
ZCDB
VREF
ZCA
VINAC
1.7V /
1.0V
TON Modulation
Trigger
+
15 VREF
UVLO
EN
PWMB
1.7V /
1.0V
13.5V
13.5V
Phase A
On-Time Control
Phase Fail Detector
and
12ms Filter
ZCDA 16
Open/Short
Detection
1-PHASE
3
Clamping
TSET
TJ
160°C /
140 °C
DROPOUT
+
TON Basis
0.70V /
0.35V
+
TSD
PWMA
Dropout Detection
2μA
+
+
PHASE_B_OFF
4.95V
6
5
4
AGND
COMP
PHB
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8.3 Feature Description
8.3.1 Principles of Operation
The UCC28063 contains the control circuits for two parallel-connected boost pulse-width modulated (PWM)
power converters. The boost PWM power converters ramp current in the boost inductors for a time period
proportional to the voltage on the error amplifier output. Each power converter then turns off the power MOSFET
until current in the boost inductor decays to zero, as sensed on the zero current detection inputs (ZCDA and
ZCDB). Once the inductor is demagnetized, the power converter starts another cycle. This on/off cycling
produces a triangle wave of current, with peak current set by the on-time and instantaneous power mains input
voltage, VIN(t), as shown in Equation 1.
14
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Feature Description (continued)
IPEAK (t) =
VIN (t) ´ TON
L
(1)
The average line current is exactly equal to half of the peak line current, as shown in Equation 2.
V (t) ´ TON
IAVG (t) = IN
2´L
(2)
With TON and L being essentially constant during an AC-line period, the resulting triangular current waveform
during each switching cycle will have an average value proportional to the instantaneous value of the rectified
AC-line voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a
near-unity power factor.
8.3.2 Natural Interleaving
Under normal operating conditions, the UCC28063 regulates the relative phasing of the channel A and channel B
inductor currents to be very close to 180°. This greatly reduces the switching-frequency ripple currents seen at
the line-filter and output capacitors, compared to the ripple current of each individual converter. This design
allows a reduction in the size and cost of input and output filtering. The phase-control function differentially
modulates the on-times of the A and B channels based on their phase and frequency relationship. The Natural
Interleaving method allows the converter to achieve 180° phase-shift and transition-mode operation for both
phases without tight requirements on boost inductor tolerance.
Ideally, the best current-sharing is achieved when both inductors are exactly the same value. Typically the
inductances are not the same, so the current-sharing of the A and B channels is proportional to the inductor
tolerance. Also, switching delays and resonances of each channel typically differ slightly, and the controller
allows some necessary phase-error deviation from 180° to maintain equal switching frequencies. Optimal phase
balance occurs if the individual power stages and the on-times are well matched. Mismatches in inductor values
do not affect the phase relationship.
8.3.3 On-Time Control, Maximum Frequency Limiting, and Restart Timer
Gate-drive on-time varies proportionately with the error-amplifier output voltage by a factor called KT (in units of
μs/V), as shown in Equation 3.
TON = K T (VCOMP - 125mV )
(3)
Where:
• VCOMP is the output voltage of the error amplifier and 125 mV is a modulator offset voltage.
The maximum output of the error amplifier is limited to 4.95 V. This value, minus the 125-mV modulator offset,
limits maximum on-time as determined by Equation 4.
TON(max) = K T ´ 4.825 V
(4)
This on-time limit sets the maximum power that can be delivered by the converter at a given input voltage.
At lower power, one boost channel (phase) may be turned off to achieve efficiency benefits (see Phase
Management section, below). To provide a smooth transition between two-phase and single-phase operation, KT
increases by a factor of two in single-phase mode:
K TS = 2 ´ K T ; active during single-phase operation
(5)
The maximum switching frequency of each phase is limited by minimum-period timers. If inductor current decays
to zero before the minimum-period timer elapses, the next turn-on will be delayed, resulting in discontinuous
phase current.
A restart timer ensures starting under all circumstances by restarting both phases if the ZCD input of either
phase has not transitioned from high-to-low within approximately 200 µs. To prevent the circuit from operating in
continuous conduction mode (CCM), the restart timer does not trigger turn-on until both phase-currents return to
zero.
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Feature Description (continued)
The on-time factors (KT, KTS) and the minimum switching period, T(MIN), are proportional to the time-setting
resistor RTSET (the resistor from the TSET pin to ground), and these factors can be calculated by Equation 5,
Equation 6 and Equation 7:
R
ms
K T = TSET ´ 4.0
133kW
volt
(6)
RTSET
T(MIN) =
´ 2.2 ms ; Minimum Switching Period
133kW
(7)
The proper value of RTSET will result in the clamped maximum on-time, TON(max), required by the converter
operating at the minimum input line voltage and maximum load.
8.3.4 Distortion Reduction
Due to the parasitic resonance between the drain-source capacitance of the switching MOSFET and the boost
inductor, conventional transition-mode PFC circuits may not be able to absorb power from the input line when the
input voltage is near zero. This limitation increases total harmonic distortion as a result of ac-line current
waveform distortion in the form of flat spots. To help reduce line-current distortion, the UCC28063 increases
switching MOSFET on-time when the input voltage is near 0 V to improve the power absorption capability and
compensate for this effect.
Figure 12 in the Typical Characteristics section shows the increase in on-time with respect to VINAC voltage.
Excessive filtering of the VINAC signal will nullify this function.
8.3.5 Zero-Current Detection and Valley Switching
In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current reaches zero. Because of
the resonance between the boost inductor and the parasitic capacitance at the MOSFET drain node, part of the
energy stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore,
when the rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET
junction capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate
delay, the MOSFET can be turned on at the valley of its resonating drain voltage (valley-switching). In this way,
the energy recovery can be maximized and switching loss is minimized.
The optimal time delay is generally derived empirically, but a good starting point is a value equal to 25% of the
resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 25, but
the delay time increases slightly as the input voltage nears the output voltage. Because the ZCD pin is internally
clamped, a more accurate delay can also be realized by using the circuit shown in Figure 26.
ZCD
R
CT
C
Figure 25. Simple RC Delay Circuit
ZCD
R1
CT
C
R2
Figure 26. More Accurate Time Delay Circuit
16
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Feature Description (continued)
8.3.6 Phase Management and Light-Load Operation
Under light-load conditions, switching losses may dominate over conduction losses and efficiency may be
improved if one phase (channel) is turned off. At a certain power level, the reduction of switching losses is
greater than the increase in conduction losses. Turning off one phase at light load is especially valuable for
meeting light-load efficiency standards. This is one of the major benefits of interleaved PFC and it is especially
valuable for meeting 80+ design requirements.
The PHB input can be used to force the UCC28063 to operate in single-phase mode. When PHB is driven below
0.8 V, channel B will stop switching and channel A on-time will automatically double to compensate. The device
will resume dual-phase mode when PHB is raised above 1.0 V. For customized phase management, an external
circuit can detect the conditions for switching to single-phase operation and drive PHB accordingly. To operate
continuously in two-phase mode (normal mode) when phase management is not desired, simply connect PHB to
VREF.
As load current decreases, the error amplifier commands less ac-line input current by lowering COMP voltage. In
applications where the ac-line is limited to the low-voltage range only, it may be advantageous to connect PHB
directly to COMP to allow automatic selection of single-phase operation without additional external circuitry.
8.3.7 External Disable
The UCC28063 can be externally disabled by purposefully grounding the VSENSE pin with an open-drain or
open-collector driver. When disabled, the device supply current drops significantly and COMP is actively pulled
low. This disable method forces the device into standby mode and minimizes its power consumption. This is
particularly useful when standby power is a key design aspect. When VSENSE is released, the device enters
soft-start mode.
8.3.8 Improved Error Amplifier
The voltage-error amplifier is a transconductance amplifier. Voltage-loop compensation is connected from the
error amplifier output, COMP, to analog ground, AGND. The recommended Type-II compensation network is
shown in Figure 27. For loop-stability purposes, the compensation network values are calculated based on smallsignal perturbations of the output voltage using the nominal transconductance (gain) of 55 μS.
VREF
+
COMP
gM
VSENSE
CZ
CP
4.95V
RZ
Figure 27. Transconductance Error Amplifier With Typical Compensation Network
To improve the transient response to large perturbations, the error amplifier gain increases by a factor of ~5X
when the error amp input deviates more than ±5% from the nominal regulation voltage, VSENSEreg. This
increase allows faster charging and discharging of the compensation components following sudden load-current
increases or decreases (also refer to Figure 5 in the Typical Characteristics).
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Feature Description (continued)
IEA
VSENSE
VREF
Basic voltage-error amplifier transconductance curve showing small-signal and large-signal gain sections, with
maximum current limitations.
Figure 28. Basic Voltage-Error Amplifier Transconductance Curve
8.3.9 Soft Start
Soft-start is a process for boosting the output voltage of the PFC converter from the peak of the ac-line input
voltage to the desired regulation voltage under controlled conditions. Instead of a dedicated soft-start pin, the
UCC28063 uses the voltage error amplifier as a controlled current source to increase the PWM duty-cycle by
way of increasing the COMP voltage. To avoid excessive start-up time-delay when the ac-line voltage is low, a
higher current is applied until VSENSE exceeds 3 V at which point the current is reduced to minimize the
tendency for excess COMP voltage at no-load start-up.
The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to
AGND charges from zero to near its final value. This process implements a soft-start, with timing set by the
output current of the error amplifier and the value of the compensation capacitors. In the event of a HVSEN
FailSafe OVP, brownout, external-disable, UVLO fault, or other protection faults, COMP is actively discharged
and the UCC28063 will soft-start after the triggering event is cleared. Even if a fault event happens very briefly,
the fault is latched into the soft-start state and soft-start is delayed until COMP is fully discharged to 20 mV and
the fault is cleared. See Figure 29 for details on the COMP current. See Figure 30 which illustrates an example
of typical system behavior during soft-start.
ICOMP
OVP1 trigger. 2k pull -down
applied to COMP .
+63μA
+15μA
OVP1 reset. 2k pull -down
removed from COMP .
1.0
2.0
3.0
4.0
5.0
-15μA
6.0
7.0
VSENSE
COMP current limit
during Soft -Start only
(high-gain disabled )
-111 μA
Expanded COMP output current curve including voltage-error amplifier transconductance and modifications applicable
to soft-start and overvoltage conditions.
Figure 29. Expanded Comp Output Current Curve
18
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Feature Description (continued)
OVERSHOOT
V
VSENSEREG
VENDofSS
VSENSE
VCOMPCLMP
COMP
VSSTHR
t
I AC-LINE
ICOMP
ISS,SLOW
ISS,FAST
HIGH GAIN ENABLED
SOFTSTART
Figure 30. Soft-Start Timing With Illustrative System Behavior
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Feature Description (continued)
8.3.10 Brownout Protection
As the power line RMS voltage decreases, RMS input current must increase to maintain a constant output
voltage for a specific load. Brownout protection helps prevent excess system thermal stress (due to the higher
RMS input current) from exceeding a safe operating level. Power-line voltage is sensed at VINAC. When the
VINAC fails to exceed the brownout threshold for the brownout filter time, a brownout condition is detected and
both gate drive outputs are turned off. During brownout, COMP is actively pulled low and a soft-start condition is
initiated. Hysteresis is built into the brownout detection circuit to avoid chatter around the threshold. When VINAC
rises above the brownout threshold, the power stage soft-starts as COMP rises with controlled current.
The brownout detection threshold and its hysteresis are set by the voltage-divider ratio and resistor values.
Brownout protection is based on VINAC peak voltage; the threshold and hysteresis are also based on the line
peak voltage. Major hysteresis is provided by a 2-μA current-sink (IBOHYS) enabled whenever VINAC falls below
the brownout detection threshold. Minor hysteresis is also present in the form of a 50-mV offset (VBOHYS)
between the VINAC detection and clear thresholds. The peak VINAC voltage can be easily translated into an
RMS value. Example resistor values for the voltage divider are 8.61 MΩ ±1% from the rectified input voltage to
VINAC and 133 kΩ ±1% from VINAC to ground. These resistors set the typical thresholds for RMS line voltages,
as shown in Table 1.
Table 1. Brownout Thresholds (For Conditions Stated in the Text)
THRESHOLD
AC-LINE VOLTAGE (RMS)
Falling
66 V
Rising
78 V
Equation 8 and Equation 9 can be used to calculate the VINAC divider-resistor values based on desired
brownout detection and brownout clear voltage levels. VAC_OK is the desired RMS turn-on voltage, VAC_BO is the
desired RMS turn-off brownout voltage, and VLOSS is total series voltage drop due to wiring, EMI-filter, and
bridge-rectifier impedances at VAC_BO. VBODET, VBOHYS and IBOHYS are found in the data-tables of this datasheet.
æ
2(VAC _ OK - VAC _ BO ) - VBOHYS ö÷ æ VBOHYS ö
ç 1+
÷
ç
֏
IBOHYS
VBODET ø
RA = ç
è
RB =
ø
(8)
RA
æ 2VAC _ BO - VLOSS
ö
ç
- 1÷
ç
÷
VBODET
è
ø
(9)
Once standard values for the VINAC divider-resistors RA and RB are selected, the actual turn-on and brownout
threshold RMS voltages for the ac-line can be back-calculated with Equation 10 and Equation 11:
æ R öV
V
VAC _ BO = ç 1 + A ÷ BODET + LOSS
RB ø
2
2
è
(10)
R AIBOHYS
VBOHYS
+
VAC _ OK = VAC _ BO +
æ V
ö
2
2 ç 1+ BOHYS ÷
ç V
÷
BODET ø
è
(11)
An example of the timing for the brownout function is illustrated in Figure 31.
For a quick estimation of the turn-on and brownout voltages, simplify the foregoing equations by setting the VLOSS
and VBOHYS terms to zero.
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8.3.11 Dropout Detection
It is often the case that the ac-line voltage momentarily drops to zero or nearly zero, due to transient abnormal
events affecting the local ac power distribution network. Referred to as ac-line dropouts (or sometimes as linedips) the duration of such events usually extends to only 1 or 2 line cycles. During a dropout, the down-stream
power conversion stages depend on sufficient energy storage in the PFC output capacitance, which is sized to
provide the ride-through energy for a specified hold-up time. Typically while the PFC output voltage is falling, the
voltage-loop error amplifier output rises in an attempt to maintain regulation. As a consequence, excess dutycycle is commanded when the ac-line voltage returns and high peak current surges may saturate the boost
inductors with possible overstress and audible noise.
The UCC28063 incorporates a dropout detection feature which suspends the action of the error amplifier for the
duration of the dropout. If the VINAC voltage falls below 0.35 V for longer than 5 ms, a dropout condition is
detected and the error amplifier output is turned off. In addition, a 4-μA pull-down current is applied to COMP to
gently discharge the compensation network capacitors. In this way, when the ac-line voltage returns, the COMP
voltage (and corresponding duty-cycle setting) remains very near or even slightly below the level it was before
the dropout occurred. Current surges due to excess duty-cycle, and their undesired attendant effects, are
avoided. The dropout condition is cancelled and the error amplifier resumes normal operation when VINAC rises
above 0.71 V.
Based on the VINAC divider-resistor values calculated for brownout in the previous section, the input RMS
voltage thresholds for dropout detection VAC_DO and dropout clearing VDO_CLR can be determined using
Equation 12 and Equation 13, below.
æR
ö
VDODET ç A + 1÷ + VLOSS
è RB
ø
VAC _ DO =
2
(12)
æR
ö
VDOCLR ç A + 1÷ + VLOSS
R
è B
ø
VDO _ CLR =
2
(13)
Avoid excessive filtering of the VINAC signal, or dropout detection may be delayed or defeated. An RC timeconstant of ≤ 100-μs should provide good performance. An example of the timing for the dropout function is
illustrated in Figure 32.
VSENSE
COMP
IBOHYS
ON
VINAC
VBOCLR
VBODET
0V
t
BROWNOUT
DETECT
BROWNOUT
t BODLY
Figure 31. AC-Line Brownout Timing With Illustrative System Behavior
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VSENSE
VINAC
COMP
VDOCLR
VDODET
0V
t
DROPOUT
tDODLY
Figure 32. AC-Line Dropout Timing With Illustrative System Behavior
8.3.12 VREF
VREF is an output which supplies a well-regulated reference voltage to circuits within the device as well as
serving as a limited source for external circuits. This output must be bypassed to GND with a low-impedance 0.1μF or larger capacitor placed as close to the VREF and GND pins as possible. Current draw by external circuits
should not exceed a few milli-amperes and should not be pulsing.
The VREF output is disabled under the following conditions: when VCC is in UVLO, or when VSENSE is below
the Enable threshold. This output can only source current and is unable to accept current into the pin.
8.3.13 VCC
VCC is usually connected to a bias supply of between 13 V and 21 V. To minimize switching ripple voltage on
VCC, it should be by-passed with a low-impedance capacitor as close to the VCC and GND pins as possible.
The capacitance should be sized to adequately decouple the peak currents due to gate-drive switching at the
highest operating frequency. When powered from a poorly-regulated low-impedance supply, an external zener
diode is recommended to prevent excessive current into VCC.
The undervoltage-lockout (UVLO) condition is when VCC voltage has not yet reached the turn-on threshold or
has fallen below the turn-off threshold, having already been turned on. While in UVLO, the VREF output and
most circuits within the device are disabled and VCC current falls significantly below the normal operating level.
The same situation applies when VSENSE is below its Enable threshold. This helps minimize power loss during
pre-powerup and standby conditions.
8.3.14 Control of Downstream Converter
In the UCC28063, the PWMCNTL pin can be used to coordinate the PFC stage with a downstream converter.
Through the HVSEN pin, the PFC output voltage is monitored. A 12-μA current source (IHV_HYS) is enabled as
long as the output voltage remains below a programmed threshold. When the output voltage exceeds that
threshold, PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. At
the same time the current source is disabled, providing hysteresis for a lower threshold at which the downstream
converter should be turned off. The enable/disable hysteresis is adjusted through the HVSEN voltage-divider
ratio and resistor values. The HVSEN pin is also used for the FailSafe over-voltage protection (OVP). When
designing the voltage divider, make sure this FailSafe OVP level is set above normal VSENSE OVP levels.
Because there are two thresholds associated with the HVSEN input detected through a single resistor divider,
the PWMCNTL turn-off voltage, VPWM-OFF, is linked to the FailSafe OVP voltage, VFLSF_OV, as shown by
Equation 14:
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VPWM-OFF VFLSF _ OV
=
2.5 V
4.87 V
(14)
Choosing either one first arbitrarily determines the other, so a trade-off may be necessary. The PWMCNTL turnon voltage, VPWM-ON, is programmed by choosing the upper divider resistor value in consideration with the
HVSEN hysteresis current, as shown in Equation 15 and Equation 16. The lower divider resistor is then
calculated as shown in Equation 17.
VPWM-ON = VPWM-OFF + IHV _ HYSRHV _ UPPER
(15)
V
- VPWM-OFF
RHV _ UPPER = PWM-ON
IHV _ HYS
RHV _ LOWER =
8.3.15
(16)
RHV _ UPPER
æ VPWM-OFF
ö
- 1÷
ç
è 2.5 V
ø
(17)
System Level Protections
8.3.15.1 Failsafe OVP - Output Overvoltage Protection
FailSafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths
for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is
implemented through two independent paths: VSENSE and HVSEN. The converter shuts down if either input
senses a severe over-voltage condition. The output voltage can still remain below a safe limit if either sense path
fails. The device is re-enabled when both sense inputs fall back into their normal ranges. At that time, the gate
drive outputs will resume switching under PWM control. A low-level over-voltage on VSENSE does not trigger
soft-start, but the COMP pin is discharged by an internal 2-kΩ resistance until the output voltage falls below the
2% hysteresis OV-clear threshold. A higher-level over-voltage on VSENSE additionally shuts off the gate-drive
outputs until the OV clears, but still does not trigger a soft-start. However, an overvoltage detected on HVSEN
does trigger a full soft-start and the COMP pin is fully discharged to 20 mV before the soft-start can begin.
8.3.15.2 Overcurrent Protection
Under certain conditions (such as inrush, brownout-recovery, and output over-load) the PFC power stage sees
large currents. It is critical that the power devices be protected from switching during these conditions.
The conventional current-sensing method uses a shunt resistor in series with each MOSFET source leg to sense
the converter currents, resulting in multiple ground points and high power dissipation. Furthermore, since no
current information is available when the MOSFETs are off, the source-resistor current-sensing method results in
repeated turn-on of the MOSFETs during overcurrent (OC) conditions. Consequently, the converter may
temporarily operate in continuous conduction mode (CCM) and may experience failures induced by excessive
reverse-recovery currents in the boost diodes or other abnormal stresses.
The UCC28063 uses a single resistor to continuously sense the combined total inductor (input) current. This
way, turn-on of the MOSFETs is completely avoided when the inductor currents are excessive. The gate drive to
the MOSFETs is inhibited until total inductor current drops to near zero, precluding reverse-recovery-induced
failures (these failures are most likely to occur when the ac-line recovers from a brownout condition).
The nominal OC threshold voltage during two-phase operation is -200 mV, which helps minimize losses. This
threshold is automatically reduced to -166 mV during single-phase operation, either by detection of a phase
failure or because PHB is driven below 0.8 V. Note that the single-phase threshold is not simply 1/2 of the dualphase threshold, because the ratio of the single-phase peak current to the interleaved peak current is higher than
1/2.
An OC condition immediately turns off both gate-drive outputs, but does not trigger a soft-start and does not
modify the error amplifier operation. The over-current condition is cleared when the total inductor current-sense
voltage falls below the OC-clear threshold (-15 mV).
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Following an over-current condition, both MOSFETs are turned on simultaneously once the input current drops to
near zero. Because the two phase currents are temporarily operating in-phase, the current-sense resistance
should be chosen so that OC protection is not triggered with twice the maximum current peak value of either
phase in order to allow quick return to normal operation after an over-current event. Automatic phase-shift control
will re-establish interleaving within a few switching cycles.
8.3.15.3 Open-Loop Protection
If the feedback loop is disconnected from the device, a 100-nA current source internal to the UCC28063 pulls the
VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device becomes disabled. When
disabled, the bias supply current decreases, both gate-drive outputs and COMP are actively pulled low, and a
soft-start condition is initiated. The device is re-enabled when VSENSE rises above 1.25 V. At that time, the gate
drive outputs will begin switching under soft-start PWM control.
If the feedback loop is disconnected from ground, the VSENSE voltage will be pulled high. When VSENSE rises
above the 2nd-level over-voltage protection threshold, both gate drive outputs are shut off and COMP is actively
pulled low. The device is re-enabled when VSENSE falls below the OV-clear threshold. The VSENSE input can
tolerate a limited amount of current into the device under abnormally high input voltage conditions. Refer to the
Absolute Maximum Ratings table near the beginning of this datasheet for details.
8.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection
VCC must rise above the turn-on threshold for the PWM to begin functioning. If VCC drops below the UVLO
threshold during operation, both gate-drive outputs are actively pulled low, COMP is actively pulled low, and a
soft-start condition is triggered. VCC must again rise above the turn-on threshold for the PWM function to restart
in soft-start mode.
8.3.15.5 Phase-Fail Protection
The UCC28063 detects failure of either of the phases by monitoring the sequence of ZCD pulses. During normal
two-phase operation, if one ZCD input remains idle for longer than approximately 12 ms while the other ZCD
input switches normally, the over-current threshold is reduced and PWMCNTL goes to a high-impedance state,
indicating that the PFC power stage is not operating correctly. During normal single-phase operation (PHB < 0.8
V), phase failure is not monitored. Also on the UCC28063, phase failure is not monitored when COMP is below
approximately 222 mV.
8.3.15.6 CS-Open, TSET-Open and -Short Protection
In the event that the CS input becomes open-circuited, the UCC28063 detects this condition and will shutdown
the outputs and trigger a full-soft-start condition. In the event that the TSET input becomes either open-circuited
or short-circuited to GND, the UCC28063 detects these conditions and will shutdown the outputs and trigger a
full-soft-start condition. Normal operation will resume (with a soft-start) when the fault clears.
8.3.15.7 Thermal Shutdown Protection
Overloading of the gate-drive outputs, VREF, or both can dissipate excess power within the device which may
raise the internal temperature of the circuits beyond a safe level. Even normal power dissipation can generate
excess heat if the thermal impedance is too high or the ambient temperature is too high. When the UCC28063
detects an internal over-temperature condition it will shutdown the outputs and trigger a full soft-start condition.
When the internal device junction temperature has cooled below the thermal hysteresis temperature, operation
will resume under soft-start control.
8.3.15.8 AC-Line Brownout and Dropout Protections
See specific discussions for each topic in previous sections of this data sheet.
8.3.15.9 Fault Logic Diagram
Figure 33 depicts the fault-handling logic involving VSENSE, COMP, and several internal states.
24
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PHASE_B_OFF
STOP GDB
OC
STOP GDA
HIGH _OV
BROWNOUT
HVSEN_OV
UVLO
EN
TSET_FLT
CS_OPEN
TSD
HIGH_OV Latch
S Q
6.67V
COMP Discharge Latch
S Q
+
R
R
Q
Q
LOW _OV Latch
S Q
6.48V
+
+
20mV
6.36V
R
+
Q
OV-Clear
COMP
4μA
2kΩ
1.25V
EN
+
LOW_OV
DIS _EA
DROPOUT
Gain -Disable Latch
S Q
VCC
DIS _High_Gain
+
R
5.9V
VSENSE
Q
+
3.0V
Figure 33. Fault Logic With VSENSE Detections and Error Amplifier Control
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8.4 Device Functional Modes
The controller is primarily intended for set up as a dual phase interleaved PFC which utilizes inductor
demagnetization information based on inductor sense winding voltages which are routed to ZCDA and ZCDB to
trigger the start of a switching cycle.
The functionality may be extended in a couple of ways:
• Phase-B Enable and Disable: Phase-B may be shed by explicit user control or it may be set up as an
automatic light load efficiency management feature. When the voltage applied to the PHB pin is below
VPHBF threshold, Phase B and the Phase Fail Detector will be disabled. The commanded On-time for
Phase-A will be doubled to minimize the output voltage transient which would otherwise occur. When the
voltage on the PHB pin is greater than the VPHBR threshold, two phase mode is continuously enabled. Tie
PHB to VREF pin for this mode. Alternatively PHB may be tied to the COMP pin for automatic phase
shedding at light load.
• PFC Stage Enable and Disable Control: Controller operation is enabled when VSENSE voltage exceeds
the 1.25-V enable threshold. The primary disable method should be by pulling VSENSE low by an open drain
or open collector logic output. This will disable the outputs and significantly reduce VCC current. Releasing
VSENSE will initiate a Soft-Start. Avoid any PCB traces which would couple any noise into this node.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This control IC is generally applicable to the control of AC-DC power supplies which require Active Power Factor
Correction off Universal AC line. Applications using this IC will generally meet the Class D equipment input
current harmonics standards per EN61000-3-2. This standard applies to equipment with rated Powers higher
than 75W. The IC brings two phase interleaved control capability to the Transition Mode Boost and hence will be
generally a very good choice for cost optimized applications in the 150W to 800W space, or to even lower
powers that wish to exploit the interleaving benefits of reduced filtering component size, lower profile solutions
and distributed thermal management.
The UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator User's Guide (SLUU512) describes an EVM
design for a 300W Application.
This EVM has an associated Excel file to help automate calculations for its component choices available at
SLUC292.
9.2 Typical Application
An example of the UCC28063 PFC controller in a two-phase interleaved, transition-mode PFC pre-regulator is
shown in Figure 34.
Bridge
+
D3
CIN
–
RS
12V
CA
R
100
F1
RZA
2.2uF
CF1
1 nF
RP
50 k
VCC
CB
2.2uF
Q1
5
UCC28063
VREF
RB
RG1
RZB
VINAC
CF2
VOUT
GDA
PWMCNTL
PWMCNTL
D1
ZCDA
22pF
CS
RA
L1
20 k
CF4
RLOAD
20 k
CF5
D2
ZCDB
PHB
COMP
COUT
L2
22pF
RG2
Q2
GDB
5
RC
RE
RD
RF
HVSEN
RZ
TSET
VSENSE
CP
RT
CZ
CF3
AGND
PGND
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Figure 34. Typical Interleaved Transition-Mode PFC Pre-Regulator
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Typical Application (continued)
9.2.1 Design Requirements
The specifications for this design were chosen based on the power requirements of a typical 300-W LCD TV.
These specifications are shown in Table 2.
Table 2. Design Specifications
DESIGN PARAMETER
MIN
TYP
VIN
RMS input voltage
VOUT
Output voltage
fLINE
AC-line frequency
PF
Power factor at maximum load
0.90
η
Full-load efficiency
92%
fMIN
Minimum switching frequency
MAX
85
(VIN_MIN)
UNIT
265
(VIN_MAX)
390
47
POUT
45
VRMS
V
63
Hz
300
W
kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The boost inductor is selected based on the inductor ripple current requirements at the peak of low line.
Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (DPEAK_LOW_LINE),
as shown in Equation 18.
DPEAK _ LOW _ LINE =
VOUT - VIN_MIN 2
VOUT
=
390 V - 85 V 2
» 0.69
390 V
(18)
The minimum switching frequency of the converter (fMIN) under low line conditions occurs at the peak of low line
and is set between 25 kHz and 50 kHz to avoid audible noise. For this design example, fMIN is set to 45 kHz. For
a 2-phase interleaved design, L1 and L2 are determined as shown in Equation 19.
L1 = L2 =
h ´ VIN _ MIN2 ´ DPEAK _ LOW _ LINE
POUT ´ fMIN
=
0.92(85 V)2 0.69
» 340 mH
300 W ´ 45kHz
(19)
The inductor for this design would have a peak current (ILPEAK) of 5.4 A, as shown in Equation 20, and an RMS
current (ILRMS) of 2.2 A, as shown in Equation 21.
ILPEAK =
ILRMS =
POUT 2
300 W 2
=
» 5.4 Apk
VIN _ MIN ´ h 85 V ´ 0.92
ILPEAK
6
5.4 A
=
6
(20)
» 2.2 Arms
(21)
This converter uses constant on time (TON) and zero-current detection (ZCD) to set up the converter timing.
Auxiliary windings on L1 and L2 detect when the inductor currents are zero. Selecting the turns ratio using
Equation 22 ensures that there will be at least 2 V at the peak of high line to reset the ZCD comparator after
every switching cycle.
The turns-ratio of each auxiliary winding is:
NP VOUT - VIN_MAX 2 390 V - 265 V 2
=
=
»8
Ns
2V
2V
(22)
9.2.2.2 ZCD Resistor Selection (RZA, RZB)
The minimum value of the ZCD resistors is selected based on the internal clamps maximum current ratings of 3
mA, as shown in Equation 23.
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R ZA = R ZB ³
VOUTNS
390 V
=
» 16.3kW
NP ´ 3mA 8 ´ 3mA
(23)
In this design the ZCD resistors are set to 20 kΩ, as shown in Equation 24.
R ZA = R ZB = 20kW
(24)
9.2.2.3 HVSEN
The HVSEN pin programs the PWMCNTL output of the UCC28063. The PWMCNTL open-drain output can be
used to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts high
impedance and pulls to ground when HVSEN increases above 2.5 V. Setting the point where PWMCNTL
becomes active requires a voltage divider from the boost voltage to the HVSEN pin to ground. Equation 25 to
Equation 30 show how to set the PWMCNTL pin to activate when the output voltage is within 90% of its nominal
value.
VOUT _ OK = VOUT ´ 0.90 » 351 V
(25)
Resistor RE sets up the high side of the voltage divider and programs the hysteresis of the PWMCNTL signal.
For this example, RE was selected to provide 99 V of hysteresis, as shown in Equation 26. Three resistors in
series were used to meet voltage requirements.
Hysteresis
99 V
RE =
=
= 8.25MW » 3 ´ 2.74MW
12 mA
12 mA
(26)
Resistor RF is used to program the PWMCNTL active threshold, as shown in Equation 27.
2.5 V
2.5 V
RF =
=
= 82.25kW
VOUT _ OK - 2.5 V
351V - 2.5 V
- 12 mA
- 12 mA
8.22MW
RE
(27)
Select a standard resistor value for RF.
RF = 82.5kW
(28)
This PWMCNTL output will remain active until a minimum output voltage (VOUT_MIN) is reached, as shown in
Equation 29.
VOUT _ MIN =
2.5 V (RE + RF ) 2.5 V (8.22MW + 82.5kW )
=
» 252 V
RF
82.5kW
(29)
According to these resistor values, the FailSafe OVP threshold will be set according to Equation 30
VOV _ FAILSAFE =
9.2.2.4
4.87 V (RE + RF ) 4.87 V (8.22MW + 82.5kW )
=
» 490 V
RF
82.5kW
(30)
Output Capacitor Selection
The output capacitor (COUT) is selected based on holdup requirements, as shown in Equation 31.
POUT 1
300 W 1
2
h fLINE
0.92 47Hz
³
=
» 156 mF
2
2
VOUT - (VOUT _ MIN )
390 V 2 - (252 V)2
2
COUT
(31)
Two 100-μF capacitors were used in parallel for the output capacitor.
COUT = 200 mF
(32)
For this size capacitor, the low-frequency peak-to-peak output voltage ripple (VRIPPLE) is approximately 14 V, as
shown in Equation 33:
2 ´ POUT
1
2 ´ 300 W
VRIPPLE =
=
» 14 Vppk
VOUT ´ 4p ´ fLINE ´ COUT 0.92 ´ 390 V ´ 4p ´ 47Hz ´ 200 mF
h
(33)
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In addition to holdup requirements, a capacitor must be selected so that it can withstand the low-frequency RMS
current (ICOUT_100Hz) and the high-frequency RMS current (ICOUT_HF); see Equation 34 to Equation 36. Highvoltage electrolytic capacitors generally have both a low- and a high-frequency RMS current ratings on the
product data sheets.
POUT
300 W
ICOUT _100Hz =
=
= 0.591 Arms
VOUT ´ h ´ 2 390 V ´ 0.92 ´ 2
(34)
ICOUT _ HF
æ
POUT 2 2
= ç
çç 2 ´ h ´ VIN _ MIN
è
æ 300 W ´ 2 2
ICOUT _ HF = ç
ç 2 ´ 0.92 ´ 85 V
è
2
4 2VIN _ MIN ö
÷ - I
COUT _100Hz
9pVOUT ÷÷
ø
(
)
2
(35)
2
4 2 ´ 85 V ö
÷ - (0.591A )2 » 0.966 Arms
9p ´ 390 V ÷
ø
(36)
9.2.2.5 Selecting (RS) For Peak Current Limiting
The UCC28063 peak limit comparator senses the total input current and is used to protect the MOSFETs during
inrush and over-load conditions. For reliability, the peak current limit (IPEAK) threshold in this design is set for
120% of the nominal maximum current that will be observed during power up, as shown in Equation 37.
IPEAK =
2POUT 2(1.2) 2 ´ 300 W 2 ´ 1.2
=
» 13 A
h ´ VIN _ MIN
0.92 ´ 85 V
(37)
A standard 15-mΩ metal-film current-sense resistor will be used for current sensing, as shown in Equation 38.
The estimated power loss of the current-sense resistor (PRS) is less than 0.25 W during normal operation, as
shown in Equation 39.
RS =
200mV 200mV
=
» 15mΩ
IPEAK
13 A
2
(38)
2
æ POUT ö
æ 300 W ö
PRS = ç
RS = ç
÷
÷ ´ 15mW » 0.22 W
çV
÷
´
h
85
V
´
0.92
è
ø
IN_MIN
è
ø
(39)
The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to
withstand a short-circuit current larger than the current required to open the fuse (F1). I2t (ampere-squaredseconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I2t is equal
to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I2t of 14 A2s was
chosen to protect the design from a short-circuit condition. To ensure the current-sense resistor has high-enough
surge protection, a 15-mΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a 2.5-W
surge rating for 5 seconds. This result translates into 833 A2s and has a high-enough I2t rating to survive a shortcircuit before the fuse opens, as described in Equation 40.
2.5 W
I2 t =
´ 5s = 833 A 2 s
0.015 W
(40)
9.2.2.6 Power Semiconductor Selection (Q1, Q2, D1, D2)
The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application Note
SLUU138, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator, explains how to
select power semiconductor components for transition-mode PFC pre-regulators.
The MOSFET (Q1, Q2) pulsed-drain maximum current is shown in Equation 41:
IDM ³ IPEAK = 13 A
(41)
The MOSFET (Q1, Q2) RMS current calculation is shown in Equation 42:
30
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IPEAK
2
1 4 2 VIN _ MIN 13 A
=
6
9p ´ VOUT
2
1 4 2 ´ 85 V
» 2.3 A
6 9p ´ 390 V
(42)
To meet the power requirements of the design, IRFB11N50A 500-V MOSFETs were chosen for Q1 and Q2.
The boost diode (D1, D2) RMS current is shown in Equation 43:
4 2 ´ VIN _ MIN
I
ID = PEAK
2
9p ´ VOUT
=
13 A
2
4 2 ´ 85 V
» 1.4 A
9p ´ 390 V
(43)
To meet the power requirements of the design, MURS360T3, 600-V diodes were chosen for D1 and D2.
9.2.2.7 Brownout Protection
Resistor RA and RB are selected to activate brownout protection at ~75% of the specified minimum-operating
input voltage. Resistor RA programs the brownout hysteresis comparator, which is selected to provide 17 V (~12
VRMS) of hysteresis. Calculations for RA and RB are shown in Equation 44 through Equation 47.
Hysteresis 17 V
RA =
=
= 8.5MW
2 mA
2 mA
(44)
To meet voltage requirements, three 2.87-MΩ resistors were used in series for RA.
R A = 3 ´ 2.87MW = 8.61MW
RB =
1.4 V ´ R A
VIN _ MIN ´ 0.75 2 - 1.4 V
=
1.4 V ´ 8.61MW
85 V ´ 0.75 2 - 1.4 V
(45)
= 135.8kW
(46)
Select a standard value for RB.
RB = 133kW
(47)
In this design example, brownout becomes active (shuts down PFC) when the input drops below 66 VRMS for
longer than 440 ms and deactivates (restarts with a full soft start) when the input reaches 78 VRMS.
9.2.2.8 Converter Timing
The maximum on-time TON depends on fMIN as determined by Equation 48. To ensure proper operation, the
timing must be set based on the highest boost inductance (L1MAX) and output power (POUT). In this design
example, the boost inductor could be as high as 390 µH. Calculate the timing resistor RT as shown in
Equation 49.
(
VIN _ MIN ´ 2 ö
æ
ö
÷ 0.92 ´ (85 V )2 ç 1 - 85 V ´ 2 ÷
÷
ç
VOUT
390 V ÷ø
è
ø=
è
= 39.2kHz
POUT ´ L1MAX
300 W ´ 390 mH
h ´ VIN _ MIN
fMIN =
2æ
) çç1 -
æ
VIN _ MIN ´ 2 ö
æ
ö
÷ 133kW ç 1 - 85 V ´ 2 ÷
133kW ç 1 ç
÷
ç
÷
Vout
390 V ø
è
ø=
è
RT =
» 121kW
4 ms
4 ms
4.85 V ´
4.85 V ´
´ fMIN
´ 39.2kHz
V
V
(48)
(49)
This result sets the maximum frequency clamp (fMAX), as shown in Equation 50, which improves efficiency at light
load.
133kW
133kW
fMAX =
=
» 550kHz
2 ms ´ RT 2 ms ´ 121kW
(50)
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9.2.2.9 Programming VOUT
Resistor RC is selected to minimize loading on the power line when the PFC is disabled. Construct resistor RC
from two or more resistors in series to meet high-voltage requirements. Resistor RD is then calculated based on
RC, the reference voltage, VREF, and the required output voltage, VOUT. Based on the values shown in
Equation 51 to Equation 54, the primary output over-voltage protection threshold should be as shown in
Equation 55:
RC = 2.74MW + 2.74MW + 3.01MW = 8.49MW
(51)
VREF = 6 V
(52)
VREF ´ RC
6 V ´ 8.49MW
RD =
=
= 132.7kW
VOUT - VREF
390 V - 6 V
(53)
Select a standard value for RD.
RD = 133kW
(54)
R + RD
8.49MW + 133kW
VOVP = 6.48 V C
= 6.48 V
= 420.1V
RD
133kW
(55)
9.2.2.10 Voltage Loop Compensation
Resistor RZ is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This
value ensures good power factor and low harmonic distortion on the input current.
The transconductance amplifier small-signal gain is shown in Equation 56:
gm = 50 mS
(56)
The voltage-divider feedback gain is shown in Equation 57:
V
6V
H = REF =
» 0.015
VOUT 390 V
(57)
The value of RZ is calculated as shown in Equation 58:
100mV
100mV
RZ =
=
= 9.52 kW
VRIPPLE ´ H ´ gm 14 V ´ 0.015 ´ 50 mS
(58)
CZ is then set to add 45° phase margin at 1/5th of the line frequency, as shown in Equation 59:
1
1
CZ =
=
= 1.78 mF
fLINE
47Hz
´ 9.52kW
2p ´
´ R Z 2p ´
5
5
(59)
CP is sized to attenuate high-frequency switching noise, as shown in Equation 60:
1
1
Cp =
=
= 770pF
fMIN
45kHz
´ 9.52kW
2p ´
´ R Z 2p ´
2
2
(60)
Standard values should be chosen for RZ, CZ and CP, as shown in Equation 61 to Equation 63.
R Z = 9.53kW
(61)
32
CZ = 2.2 mF
(62)
CP = 820pF
(63)
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9.2.3 Application Curves
Refer to UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator EVM User's Guide, SLUU512, for more
implementation details and application curves.
9.2.3.1 Input Ripple Current Cancellation with Natural Interleaving
Figure 35 through Figure 37 show the input current (M1= IL1 + IL2), Inductor Ripple Currents (IL1, IL2) versus
rectified line voltage. From these graphs, it can be observed that natural interleaving reduces the overall
magnitude of input (and output) ripple current caused by the individual inductor current ripples.
Figure 35. Inductor and Input Ripple Current at 85 VRMS at
Peak of Line Voltage
Figure 36. Inductor and Input Ripple Current at 265 VRMS
Input at Peak Line Voltage
Figure 37. Inductor and Input Ripple Current at VIN = 85 VRMS, POUT = 300 W
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9.2.3.2 Brownout Protection
The UCC28063 has a brownout protection that shuts down both gate drives (GDA and GDB) when the VINAC
pin detects that the RMS input voltage is too low. This EVM was designed to go into a brownout state when the
line drops below 64 VRMS. Once the UCC28063 control device has determined that the input is in a brownout
condition, a 400-ms timer starts to allow the line to recover before shutting down the gate drivers. After 400 ms of
brownout, both gate drivers turn off, as shown in Figure 38.
Figure 38. UCC28063A Response to a Line Brownout Event at 265 VRMS
10 Power Supply Recommendations
The IC receives all of its power through the VCC pin. This voltage should be as well regulated as possible
through all of the operating conditions of the PFC stage. Consider creating the steady state bias for this stage
from a downstream DC:DC stage which will in general be able to provide a bias winding with very well regulated
voltage. This strategy will enhance the overall efficiency of the bias generation. A lower efficiency alternative will
be to consider a series connected Fixed Positive Voltage Regulator such as the UA78L15A.
For all normal and abnormal operating conditions it is critically important that VCC remains within its
Recommended Operating Range for both Voltage and Input Current. VCC overvoltage may cause excessive
power dissipation in the internal voltage clamp and undervoltage may cause inadequate drive levels for power
MOSFETs, UVLO events (causing interrupted PFC operation) or inadequate headroom for the various on-chip
linear regulators and references.
Note also that the high RMS and peak currents required for the MOSFET gate drives are provided through the IC
13.5-V linear regulator, which does not have provision for the addition of external decoupling capacitance. For
higher Powers, very high QG power MOSFETs or high switching frequencies, consider using external driver
transistors, local to the power MOSFETs. These will reduce the IC operating temperature and ensure that the
VCC maximum input current rating is not exceeded.
Use decoupling capacitances between VREF and AGND and between VCC and PGND which are as local as
possible to the IC. These should have some ceramic capacitance which will provide very low ESR. PGND and
AGND should ideally be star connected at the control IC so that there is negligible DC or high frequency AC
voltage difference between PGND and AGND. Use values for decoupling capacitors similar to or a little larger
than those used in the EVM.
Pay close attention to start-up and shutdown VCC bias bootstrap arrangements so that these provide adequate
regulated bias power as early as possible during power application and as late as possible during power
removal. Ensure that these start-up bias bootstrap circuits do not cause unnecessary steady-state power drain.
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11 Layout
11.1 Layout Guidelines
Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,
allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input
and output filter capacitors should be located after the two phase currents are combined together. Similar to
other power management devices, when laying out the printed circuit board (PCB) it is important to use star
grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the
interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in
(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath
magnetic elements. Because of the precise timing requirement, timing-setting resistor RT should be placed as
close as possible to the TSET pin and returned to the analog ground pin with the shortest possible path. See
Figure 39 for a recommended component placement and layout.
11.2 Layout Example
VOUT
PHB and VREF pins are connected by a jumper on the back of the board.
Figure 39. Recommended PCB Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Related Parts
Table 3 lists several TI parts that have characteristics similar to the UCC28063.
Table 3. TI Related Parts
DEVICE
DESCRIPTION
UCC28050/51
Transition-mode PFC controller for low to medium power applications
UCC28019
8-pin continuous-conduction-mode (ccm) pfc controller (with slew-rate correction current)
UCC28019A
8-pin continuous-conduction-mode (ccm) pfc controller (with 2-level voltage-error gain)
UCC28060
Two-phase interleaved transition-mode pfc controller (with input voltage range gain change)
UCC28061
Two-phase interleaved transition-mode pfc controller (with no input voltage gain change)
UCC28070
Two-phase interleaved ccm (average current mode) pfc controller
12.1.2 Device Nomenclature
12.1.2.1 Detailed Pin Description
Analog Ground: Connect analog signal bypass capacitors, compensation components, and analog signal
returns to this pin. Connect the analog and power grounds at a single point to isolate high-current noise signals
of the power components from interference with the low-current analog circuits.
Error Amplifier Output: The error amplifier is a transconductance amplifier, so this output is a high-impedance
current source. Connect voltage-regulation loop-compensation components from this pin to AGND. The on-time
seen at the gate-drive outputs is proportional to the voltage at this pin minus an offset of approximately 125 mV.
During normal operation, the error amplifier maintains a transconductance of 55 μS for small-signal disturbances
on VSENSE, and shifts to ~290 μS when VSENSE deviates more than ±5% from VSENSEreg. During an AC-line
Dropout condition, the error amplifier output is disabled and an internal 4-μA source discharges COMP for the
duration of the Dropout condition. During a VSENSE-based OV event, an internal 2-kΩ resistor is applied from
COMP to GND until the OV condition clears. During soft-start triggering events (UVLO, Disable, Brownout,
HVSEN over-voltage, TSET-Fault, CS open-circuit, or Thermal Shutdown), the error-amp output is disabled and
COMP is pulled low by an internal 2-kΩ resistor. The soft-start condition begins only after the triggering event
clears and COMP has been discharged below 20 mV, ensuring that the circuit restarts with a low COMP voltage
and a short on-time. (Do not connect COMP to a low-impedance source that would interfere with COMP falling
below 20 mV.) During Soft-Start, the error amplifier high transconductance is enabled and COMP current is -125
μA as long as VSENSE < VREF/2. Once VSENSE exceeds VREF/2, the high gain is disabled and only the
small-signal gain capability is available with a maximum COMP current of approximately –16 μA. Normal
operation resumes once VSENSE > 0.983VREF (~5.9 V).
Current Sense Input: Connect the current-sense resistor and the negative terminal of the diode bridge to this
pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As input current
increases, the voltage on CS will go more negative. This cycle-by-cycle over-current protection limits input
current by turning off both gate driver outputs (GDx) when CS is more negative than the CS rising threshold
(approximately -200 mV in two-phase operation and approximately -167 mV in single-phase and phase-fail
condition). The gate drive outputs will remain low until CS falls to the CS falling threshold (approx. -15 mV).
Current sense is blanked for approximately 100 ns following the rising and falling edge of either GDx output. This
filters noise that may occur from gate-drive current or when inductor current switches from a power FET to a
boost diode. In most cases, no additional current sense filtering is required. If external filtering is deemed
necessary, or to prevent excessive negative voltage on the CS pin during AC-inrush conditions, a series resistor
is recommended to connect the current sensing resistor to the CS pin. Due to the CS bias current, this external
resistor should be less than 100 Ω to maintain accuracy. If the CS pin becomes open-circuited, the voltage on
CS floats up to about +1.5 V. This condition is detected and treated as a soft-start-triggering fault condition (CS
open-circuit).
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Channel A and Channel B Gate Drive Output: Connect these pins to the gate of the power FET for each
phase through the shortest connection practicable. If it is necessary to use a trace longer than 0.5 inch (12.6
mm) for this connection, some ringing may occur due to trace series inductance. This ringing can be damped by
adding a low-value resistor in series with GDA and GDB.
High Voltage Output Sense: The UCC28063 incorporates FailSafe OVP so that any single failure does not
allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and HVSEN but
their actions are different if either pin exceeds their respective over-voltage thresholds. Using two pins to monitor
for over-voltage provides redundant protection and fault tolerance. When HVSEN exceeds its over-voltage
threshold, it triggers a full soft-start of the controller. HVSEN can also be used to enable a downstream power
converter when the voltage on HVSEN is within the operating region. When HVSEN is greater than 2.5 V, the
PWMCNTL output may be driven Low (provided no other fault exists). When HVSEN falls below 2.5 V, the
PWMCNTL output becomes high-impedance. Select the HVSEN divider ratio for the desired over-voltage and
power-good thresholds. Select the HVSEN divider impedance for the desired power-good hysteresis based on
the hysteresis current. During operation, HVSEN must never fall below 0.8 V. Dropping HVSEN below 0.8 V puts
the UCC28063 into a special test mode, used only for factory testing. A bypass capacitor from HVSEN to AGND
is recommended to filter noise and avoid false over-voltage shutdown.
Phase-B Enable/Disable: When the voltage applied to this pin is below the Phase-B enable threshold, Phase B
of the boost converter and the Phase Fail detector are disabled. The commanded on-time for Phase A is
immediately doubled when Phase B is disabled, which helps keep COMP voltage constant during the phasemanagement transient. The PHB pin allows the user to add external phase-management control circuitry, if
desired. To disable phase-management, connect the PHB pin to the VREF pin.
PWM-Control Output: This open-drain output goes low when HVSEN is within the HVSEN-good region (HVSEN
> 2.5 V), there is no FailSafe OV, and there is no Phase-Fail condition when operating in two-phase mode (see
PHB pin). Otherwise, PWMCNTL is high-impedance.
Timing Set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the on-time versus
COMP voltage and the minimum switching period at the gate-drive outputs. Protection circuits prevent the
controller from operating if the TSET input is in an open-circuit or short-circuit condition. As long as this pin is
open-circuited, it triggers a full soft-start condition. If this pin becomes shorted to GND, its current is limited and
also triggers a soft-start condition.
Bias Supply Input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect a 0.1μF or larger ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. This bias
supply powers all circuits within the device and must be capable of delivering the steady-state dc current plus the
transient power-MOSFET gate-charging current. Input bias current is very low during undervoltage-lockout
(UVLO) or stand-by conditions (VSENSE < 1.25 V).
Input AC Voltage Sense: For normal operation, connect this pin to a voltage divider across the rectified input
power mains. When the voltage on VINAC remains below the brownout threshold for longer than the brownout
filter time, the device enters a brownout mode, both output drivers are disabled and a full soft-start is triggered.
Select the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the
desired brownout hysteresis based on the hysteresis current. A dropout condition is triggered when VINAC
remains below the dropout threshold for longer than the dropout filter time. The error amplifier is disabled and an
internal 4-μA current source discharges COMP for the duration of the dropout condition. The dropout condition is
immediately cleared and normal operation resumes when VINAC exceeds the dropout-clear threshold.
Voltage Reference Output: Connect a 0.1-μF or larger ceramic bypass capacitor from this pin to AGND. VREF
turns off during UVLO and VSENSE-disable to save bias current and increase stand-by efficiency. This reference
output can be used to bias other circuits requiring less than a few milliamperes of non-pulsing total supply
current.
Output DC Voltage Sense: Connect this pin to a voltage divider across the output of the power converter. In a
closed-loop system, the voltage at VSENSE is regulated to the error amplifier reference voltage. Select the
output voltage divider ratio for the desired output voltage. Connect the ground side of this divider to analog
ground (AGND) through a separate short trace for best output regulation accuracy and noise immunity. Controller
operation may be enabled when VSENSE voltage exceeds the 1.25-V enable threshold. VSENSE can be pulled
low by an open-drain logic output, or >6-V logic output in series with a low-leakage diode, to disable the outputs
and reduce VCC current. Two levels of output overvoltage are detected at this input. If VSENSE exceeds the
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first-level overvoltage protection threshold VLOW_OV, an internal 2-kΩ resistor is applied to COMP to quickly
reduce gate-drive on-time. If VSENSE continues to rise past the second-level threshold VHIGH_OV, GDA and GDB
are immediately latched off. This latch is cleared when VSENSE falls below the OV-clear threshold. If VSENSE
becomes disconnected, open-loop protection provides an internal current source to pull VSENSE low, which
disables the controller and triggers a soft-start condition.
Zero Current Detection Inputs: These inputs are used to detect a negative-going edge when the boost inductor
current in each respective phase goes to zero. The inputs are clamped between 0 V and 3 V. Connect each pin
through a current limiting resistor to the zero-crossing detection (ZCD) winding of the corresponding boost
inductor. The resistor value should be chosen to limit the clamping currents to less than ±3 mA. The inductor
winding polarity must be arranged so that this ZCD voltage falls when the inductor current decays to zero. When
the inductor current falls to zero, the ZCD input must drop below the falling threshold (approximately 1 V) to
cause the gate drive output to rise. Subsequently, when the power-MOSFET turns off, the ZCD input must rise
above the rising threshold (approximately 1.7 V) to arm the logic for another falling ZCD edge.
12.2 Documentation Support
12.2.1 Related Documentation
These references, design tools, and links to additional references, including design software, may be found at
www.power.ti.com.
• Evaluation Module, UCC28063EVM 300W Interleaved PFC Pre-regulator (SLUU512)
• Application Note, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator
(SLUU138)
12.3 Trademarks
DLP, Natural Interleaving are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC28063D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28063
UCC28063DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28063
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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