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UCC28250
SLUSA29D – APRIL 2010 – REVISED AUGUST 2015
UCC28250 Advanced PWM Controller With Prebias Operation
1 Features
3 Description
•
•
The UCC28250 PWM controller is designed for high
power density applications that may have stringent
prebiased start-up requirements. The integrated
synchronous rectifier control outputs target highefficiency and high-performance topologies such as
half-bridge, full-bridge, interleaved forward, and pushpull. The UCC27200 half-bridge drivers and
UCC2732X MOSFET drivers used in conjunction with
the UCC28250 provide a complete power converter
solution.
1
•
•
•
•
•
•
•
Prebiased Start-up
Synchronous Rectifier Control Outputs With
Programmable Delays (Including Zero Delay
Support)
Voltage Mode Control With Input Voltage FeedForward or Current Mode Control
Primary or Secondary-Side Control
3.3-V, 1.5% Accurate Reference Output
1-MHz Capable Switching Frequency
1% Accurate Cycle-by-Cycle Overcurrent
Protection with Matched Duty Cycle Outputs
Programmable Soft-Start and Hiccup Restart
Timer
Thermally Enhanced 4-mm × 4-mm QFN-20
Package and 20-pin TSSOP Package
Externally
programmable
soft-start,
used
in
conjunction with an internal prebiased start-up circuit,
allows the controller to gradually reach a steady-state
operating point under all output conditions. The
UCC28250 can be configured for primary or
secondary-side control and either voltage or current
mode control can be implemented.
The oscillator operates at frequencies up to 2 MHz,
and can be synchronized to an external clock. Input
voltage feedforward, cycle-by-cycle current limit, and
a programmable hiccup timer allow the system to
stay within a safe operation range. Input voltage,
output voltage and temperature protection can be
implemented. Dead time between primary-side switch
and secondary-side synchronous rectifiers can be
independently programmed.
2 Applications
•
•
•
•
•
Half-Bridge, Full-Bridge, Interleaved Forward, and
Push-Pull Isolated Converters
Telecom and Data-com Power
Wireless Base Station Power
Server Power
Industrial Power Systems
Device Information(1)
PART NUMBER
UCC28250
PACKAGE
BODY SIZE (NOM)
TSSOP (20)
6.50 mm × 4.40 mm
VQFN (20)
4.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
VIN (36 V ~ 75 V)
VIN (36 V ~ 75 V)
UCC28250
UCC27200
OVP
OUTA
HI
HI
RAMP
OUTB
LO
LO
RT
SRA
SS
SRB
Isolation
COMP
VOUT
UCC2732x
Feedback and Isolation
GND
Not Shown: PS, SP, HICC, VDD, EA+, EA-, VREF, EN, ILIM, AND VSENSE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28250
SLUSA29D – APRIL 2010 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 28
8
Applications and Implementation ...................... 29
8.1 Application Information............................................ 29
8.2 Typical Applications ................................................ 36
9 Power Supply Recommendations...................... 45
10 Layout................................................................... 45
10.1 Layout Guidelines ................................................. 45
10.2 Layout Example .................................................... 46
10.3 Thermal Protection................................................ 46
11 Device and Documentation Support ................. 47
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
47
47
47
47
47
12 Mechanical, Packaging, and Orderable
Information ........................................................... 47
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2011) to Revision D
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision B (October 2010) to Revision C
Page
•
Changed Operating junction temperature range from (-40 to 125) to (125 to 150). .............................................................. 4
•
Changed Functional Block Diagram ..................................................................................................................................... 12
Changes from Revision A (April, 2010) to Revision B
•
2
Page
Added note, "The minimum value for RPS/RSP is 5 kΩ and the maximum value is 250 kΩ." in two places. ........................ 17
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SLUSA29D – APRIL 2010 – REVISED AUGUST 2015
5 Pin Configuration and Functions
RGB Package
20-Pin VQFN
Top View
PW Package
20-Pin TSSOP
Top View
RT
VSENSE
SS
SP
PS
15
14
13
12
11
RAMP/CS 16
VSENSE
1
20 SS
RT
2
19 SP
RAMP/CS
3
18 PS
ILIM
4
17 HICC
EN
5
16 OUTA
OVP/OTP
6
15 OUTB
VREF
7
14 SRA
REF/EA+
8
13 SRB
FB/EA-
9
12 VDD
COMP 10
11 GND
10 HICC
ILIM 17
9
OUTA
EN 18
8
OUTB
OVP/OTP 19
7
SRA
VREF 20
6
SRB
1
2
3
REF/EA+ FB/EA- COMP
4
5
GND
VDD
Pin Functions
PIN
I/O
DESCRIPTION
NAME
QFN
PW
COMP
3
10
I/O
EN
18
5
I
Device enable and disable
FB/EA-
2
9
I
Error amplifier inverting input
GND
4
11
I
Ground
HICC
10
17
I
Cycle-by-cycle current limit time delay and Hiccup time setting
ILIM
17
4
I
Current sense for cycle-by-cycle overcurrent protection
OUTA
9
16
O
0.2-A sink/source primary switching output
OUTB
8
15
O
0.2-A sink/source primary switching output
OVP/OTP
19
6
I
Overvoltage and overtemperature protection pin
PS
11
18
I
Primary off to synchronous rectifier on dead-time set
RAMP/CS
16
3
I
PWM ramp input (for voltage mode control) or current sense input (for current
mode control)
REF/EA+
1
8
I
Error amplifier noninverting input
RT
15
2
I
Oscillator frequency set or synchronous clock input
SP
12
19
I
Synchronous rectifier off to primary on dead-time set
SRA
7
14
O
0.2-A sink/source synchronous rectifier output
SRB
6
13
O
0.2-A sink/source synchronous rectifier output
SS
13
20
I/O
Soft-start programming
VDD
5
12
I
Bias supply input
VREF
20
7
O
3.3-V reference output
VSENSE
14
1
I
Output voltage sensing for prebias control
Error amplifier output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (1) (2) (unless otherwise noted)
VDD (3)
Tstg
(1)
(2)
(3)
MIN
MAX
UNIT
Input supply voltage
–0.3
20
V
OUTA, OUTB, SRA and SRB
–0.3
VDD + 0.3
V
COMP
–0.3
VREF + 0.3
V
Input voltages on SS and EN
–0.3
5.5
V
Input voltages on RT, PS, SP, ILIM, OVP, HICC, VSENSE, EA+ and EA-
–0.3
3.6
V
Input voltage on RAMP/CS
–0.3
4.3
V
Output voltage on VREF
–0.3
3.6
V
Lead temperature (soldering 10 sec) PW package
300
Storage temperature
–65
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Mechanical, Packaging, and Orderable Information of the data sheet for thermal limitations and considerations of packages.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±3000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±2000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
4.7
12
17
Supply voltage, VDD
Supply bypass capacitor, CVDD
1
VREF bypass capacitor
Error amplifier input common-mode (REF/EA+, FB/EA-)
VSENSE input voltage
RT resistor
UNIT
V
µF
0.5
2
µF
0
3
V
0
3.3
V
12.5
200
kΩ
5
250
kΩ
PS, SP resistor
RAMP/CS voltage
Operating junction temperature
0
2.7
V
–40
150
°C
6.4 Thermal Information
UCC28250
THERMAL METRIC
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case(top) thermal resistance
RθJB
Junction-to-board thermal resistance
RθJC(bot)
Junction-to-case(bottom) thermal resistance
4
RGB (VQFN)
PW (TSSOP)
20 PINS
20 PINS
126 with hot spot,
104 without hot spot
60.3 with hot spot,
39.3 without hot spot
°C/W
31.5
°C/W
55.8
°C/W
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0.8
UNIT
°C/W
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6.5 Electrical Characteristics
VDD = 12 V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = –40°C to 125°C, RT = 75 kΩ connected to ground to set
FSW = 200 kHz (unless otherwise noted). (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IDD(off)
Start-up current
VDD = 3.6 V
IDD
Operating supply current
100-pF capacitor on OUTA, OUTB, SRA and SRB
IDD(dis)
Standby current
EN = 0 V
150
275
µA
2
2.7
3.4
mA
250
425
600
µA
4
4.3
4.6
V
3.8
4.1
4.4
V
0.15
0.2
0.25
V
25
27
29
µA
3.3
3.6
4
V
2.25
V
UNDERVOLTAGE LOCKOUT
VUVLOR
Start threshold
VUVLOF
Minimum operating voltage
after start
Hysteresis
SOFT START
ISS
Soft-start charge current
VSS(max)
Clamp voltage
VSS = 0 V
ENABLE (2)
Trigger threshold
Minimum pulse width for
pulse enable
3
µs
ERROR AMPLIFIER
High-level COMP voltage
2.8
Low-level COMP voltage
3
0.3
Input offset
-12
Open loop gain
V
0.4
V
12
mV
70
100
ICOMP(snk)
COMP sink current
3
6.5
9
mA
dB
ICOMP(src)
COMP source current
2
4.5
8
mA
185
200
215
kHz
OSCILLATOR
FSW(nom)
Nominal switching frequency
at OUTA or OUTB set by RT
resistor
FSW(min_sync)
Minimum switching frequency
at OUTA or OUTB set by
fRT/SYNC = 100 kHz
external sync frequency
FSW(max_sync)
Maximum switching
frequency at OUTA or OUTB
set by external sync
frequency
RT/SYNC = 75 kΩ, RSP = 20 kΩ
fRT/SYNC = 2.5 MHz
External synchronization
signal high
85
kHz
1.15
MHz
1
V
External synchronization
signal low
0.2
V
VOLTAGE REFERENCE
VVREF
Output voltage
Short circuit current
(1)
(2)
VDD = from 7 V to 17 V, IVREF = 2 mA
3.22
3.3
3.38
0 < IREF < 10 mA
3.22
3.3
3.38
12
25
40
VREF = 3 V, TJ = 25°C
V
mA
Typical values for TA = 25°C.
Refer to EN pin description in .
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Electrical Characteristics (continued)
VDD = 12 V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = –40°C to 125°C, RT = 75 kΩ connected to ground to set
FSW = 200 kHz (unless otherwise noted). (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.495
0.502
0.509
V
15
25
36
ns
40
60
90
ns
CURRENT SENSE, CYCLE-BY-CYCLE CURRENT LIMIT WITH HICCUP
VILIM
ILIM cycle-by-cycle threshold
TPDILIM
Propagation delay from ILIM
to OUTA and OUTB outputs
TBLANK
leading edge blanking
Current limit shutdown delay
timing program current
Measured at HICC pin
55
75
95
µA
Hiccup timing program
current
Measured at HICC pin
2
2.7
3.5
µA
0.55
0.6
0.65
V
2.3
2.4
2.5
V
0.25
0.3
0.35
V
3.5
4
4.5
V
0.66
0.7
0.74
V
8.5
11
13.5
µA
VHICC_SD
Current limit shutdown delay
timer threshold at HICC
VHICC_PU
HICC pullup threshold
VHICC_RST
Hiccup restart threshold
VCS(max)
Exclude leading edge blanking
RAMP/CS clamp voltage
10-V ramp charging voltage source with 40-kΩ
current limiting resistor
OVP/OTP COMPARATOR
VOVP
Internal reference
IOVP
Internal current
PRIMARY OUTPUTS
Rise/fall time
CLOAD = 100 pF
RSRC
Output source resistance
IOUT = 20 mA
12
20
8
35
ns
Ω
RSNK
Output sink resistance
IOUT = 20 mA
4
12
30
Ω
IOUT = 20 mA, VDD = 12 V
12
20
35
IOUT = 20 mA, VDD = 5 V
15
25
45
SYNCHRONOUS RECTIFIER OUTPUTS
Rise/fall time
RSRC
Output source resistance
RSNK
Output sink resistance
TDPS
TDSP
6
Primary off to secondary on
dead time
Secondary off to primary on
dead time
CLOAD = 100 pF
IOUT = 20 mA, VDD = 12 V
8
ns
4
12
30
PS = VREF
-5
0
7.5
PS = 27 kΩ
27
40
50
PS = 27 kΩ, 25°C
37
40
43
SP = VREF
-5
0
7.5
SP = 20 kΩ
30
40
50
SP = 20 kΩ, 25°C
37
40
43
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Ω
Ω
ns
ns
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6.6 Typical Characteristics
240
465
VDD = 3.6 V
VDD = 12 V
450
IDD(dis) - Stand-by Current - mA
IDD(off) - Start-Up Current - mA
220
200
180
160
140
420
405
390
120
100
375
-45
-15
15
45
75
135
105
-45
-15
15
45
75
105
135
TJ - Temperature - °C
TJ - Temperature - °C
Figure 1. Start-up Current vs
Temperature
Figure 2. Stand-by Current vs Temperature
4.41
UVLO - Under Voltage Lockout Hysteresis - V
0.225
4.33
Turn On
UVLO Thresholds - V
435
4.25
4.17
Turn Off
4.09
4.01
3.93
0.220
0.215
0.210
0.205
0.200
0.195
0.190
-45
-15
15
45
75
105
135
-45
-15
TJ - Temperature - °C
15
45
75
105
135
TJ - Temperature - °C
Figure 3. UVLO Thresholds vs
Temperature
Figure 4. UVLO Voltage Lockout Hysteresis
2.85
27.4
27.3
2.80
ISS - Soft-Start Current - mA
IDD - Operating Supply Current - mA
FSW = 200 kHz
2.75
2.70
2.65
27.2
27.1
27.0
26.9
2.60
26.8
-45
-15
15
45
75
105
135
-45
TJ - Temperature - °C
-15
15
45
75
105
135
TJ - Temperature - °C
Figure 5. Operating Supply Current vs
Temperature
Figure 6. Soft-start Current vs Temperature
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Typical Characteristics (continued)
5.0
500.4
500.2
500.0
499.8
499.6
499.4
-45
-15
15
75
45
105
135
VHICC_PU / VCS(max) - RAMP/CS Clamp Voltage and Hiccup
Pull-Up Threshold - V
IILIM - Cycle-by-Cycle Current Limit Threshold - mV
500.6
4.5
4.0
VCS(max)
3.5
3.0
2.5
VHICC_PU
2.0
1.5
-45
-15
TBLANK
50
TPD_ILIM
10
-45
-15
15
75
45
105
135
105
135
Figure 8. RAMP/CS Clamp Voltage and Hiccup Pullup
Threshold vs Temperature
VHICC_SD / VHICC_RST - Current Limit Shutdown Delay Timer
and Hiccup Restart - V
TPD_ILIM / TBLANK - Propagation Delay from ILIM to Outputs
and Leading Edge Blanking - ns
90
30
75
TJ - Temperature - °C
Figure 7. Cycle-by-Cycle Current Limit vs Temperature
70
45
15
TJ - Temperature - °C
0.7
0.6
VHICC_SD
0.5
0.4
VHICC_RST
0.3
0.2
-15
-45
45
15
TJ - Temperature - °C
75
105
135
TJ - Temperature - °C
Figure 9. Propagation Delay and Leading Edge Blanking vs
Temperature
Figure 10. Current Limit Shutdown Delay Timer and Hiccup
Restart vs Temperature
3.306
VDD = 12 V
ILOAD = 1 mA
3.305
3.295
3.302
VREF - Reference Voltage - V
VREF - Reference Voltage - V
ILOAD = 10 mA
ILOAD = 1 mA
ILOAD = 10 mA
3.285
3.275
VDD = 7 V
3.298
VDD = 17 V
3.290
-55
-35
-15
5
25
45
65
85
105
125
-55
TJ - Temperature - °C
-35
-15
5
25
45
65
85
105
125
TJ - Temperature - °C
Figure 11. Reference Voltage vs Temperature
8
VDD = 12 V
3.294
Figure 12. Reference Voltage vs Temperature
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Typical Characteristics (continued)
11.20
0.7015
11.15
IOVP - OVP Internal Currente - mA
VOVP - OVP Internal Reference - V
0.7010
0.7005
0.7000
0.6995
0.6990
11.10
11.05
11.00
10.95
10.90
10.85
-45
-15
15
45
75
105
135
-45
-15
TJ - Temperature - °C
Figure 13. OVP Internal Reference vs Temperature
75
105
135
1.153
85.2
85.0
84.8
84.6
84.4
84.2
84.0
-45
-15
15
45
75
105
135
FSYN(max) - Maximum Synchronization Frequency - MHz
FSYN(min) - Minimum Synchronization - kHz
45
Figure 14. OVP Internal Current vs Temperature
85.4
1.151
1.149
1.147
1.145
1.143
-45
-15
TJ - Temperature - °C
15
45
75
105
135
TJ - Temperature - °C
Figure 15. Minimum Synchronization Frequency vs
Temperature
Figure 16. Maximum Synchronization Frequency vs
Temperature
201.0
42.5
42.0
200.6
TDPS at RPS = 27 kW
41.5
TDSP/TDPS - Dead Time- ns
FSW(nom) - Nominal Switching Frequency - kHz
15
TJ - Temperature - °C
200.2
199.8
199.4
41.0
40.5
40.0
TDSP at RSP = 20 kW
39.5
39.0
38.5
199.0
38.0
-45
-15
15
45
75
105
135
TJ - Temperature - °C
-45
-15
15
45
75
105
135
TJ - Temperature - °C
Figure 17. Nominal Switching Frequency vs Temperature
Figure 18. Dead Time vs Temperature
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12
VDD = 12 V
TR / TF - Output Rise/Fall Time - ns
11
TR
10
9
TF
8
7
6
-45
-15
15
45
75
105
135
RSRC / RSNK - Output Source Resistance/Sink Resistance - W
Typical Characteristics (continued)
TJ - Temperature - °C
30
RSRC
25
RSNK
20
15
10
-45
-15
15
45
75
105
135
TJ - Temperature - °C
Figure 19. Output Rise/Fall Time vs Temperature
10
35
Figure 20. Output Source Resistance/Sink Resistance vs
Temperature
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7 Detailed Description
7.1 Overview
The UCC28250 is a high-performance PWM controller with advanced synchronous rectifier outputs and is ideally
suited for regulated half-bridge, full-bridge and push-pull converters. A dedicated internal prebiased start-up
control loop working in conjunction with a primary-side voltage loop achieves prebiased start-up for either
primary-side or secondary-side control applications. The UCC28250 architecture allows either voltage mode or
current mode control.
Input voltage feedforward can be implemented, allowing PWM ramp generator to improve the converter line
transient response. Advanced cycle-by-cycle current limit achieves volt-second balancing even during fault
conditions. The hiccup timer helps the system to stay within a safe operation range under over load conditions.
With a multifunction OVP/OTP pin, combinations of input voltage protection, output voltage protection and
overtemperature protection can be implemented. The UCC28250 allows individual programming of dead time
between primary-side switch and secondary-side SRs, to allow optimal power stage design. Dead time can also
be reduced to zero, and this allows optimal system configuration considering the delays on the gate driver stage.
The UCC28250 also provides complete system level protection functions, including UVLO, thermal shut down
and overvoltage, overcurrent protection.
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UCC28250
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Over
temperature
OUTB
SRA
SRB
9
8
7
6
OTP
+
4.1V/4.3V
OUTA
7.2 Functional Block Diagram
UVLO
VDD 5
Vref OK
COMP
2
FB/EA-
1
REF/EA+
13
SS
16
RAMP/CS
14
VSENSE
4
GND
EN_INT
Switching Logic
LDO
OP
+
+
OCP
VREF 20
3
Vref ready
+
Enable detection
Level&pulse
EN 18
+
Cycle by cycle
current limit
& duty cycle match
+
0.5V
BLANK
SR_RAMP
ILIM 17
Enable
OCP delay
timer
550mV
HICC 10
SR_RAMP
generator
gm
+
+
11uA
Hiccup
timer
OVP/OTP 19
+
0.7V
OVP
RT 15
CLK
Oscillator
SP 12
PS 11
70ns
leading edge blanking
BLANK
Deadtime
NOTE: Pin numbers are used for RGP package. PW package has different pin numbers.
7.3 Feature Description
7.3.1 VDD (5/12)
The UCC28250 can be powered up by a wide supply range from 4.3 V (UVLO rising typical) to 20 V (absolute
maximum), making it suitable for primary-side control or secondary-side control. When the voltage at the VDD
pin is lower than 4.1 V (typical), the controller is in stand-by mode and consumes 150 µA (typical) at 3.6 V VDD.
In stand-by mode, VREF continues to be regulated to 3.3 V or follows VDD if VDD is lower than 3.3 V. Refer to
the VREF description VREF (Reference Generator) (20/7) for more detailed information. A minimum 1-µF bypass
capacitor is required from VDD to ground. Keep the bypass capacitor as close to the device as possible.
7.3.2 VREF (Reference Generator) (20/7)
The VREF pin is regulated at 3.3 V. An external ceramic capacitor must be placed as close as possible to the
VREF and GND pins for noise filtering and to provide compensation to the regulator. The capacitance range
must be limited from 0.5 µF to 2 µF for stability. This reference is used to power the controller’s internal circuits,
and can also be used to bias an opto-coupler transistor, an external house-keeping microcontroller, or other
peripheral circuits. This reference can also be used to generate the reference for an external error amplifier. This
regulator output is internally current limited to 25 mA (typical).
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Feature Description (continued)
7.3.3 EN (Enable Pin) (18/5)
The following conditions must be met before the controller allows start-up:
1. VDD voltage is above the rising UVLO threshold 4.3 V (typical).
2. The 3.3-V reference voltage output at the VREF pin is available and above 2.4 V (typical).
3. Junction temperature is below the thermal shutdown threshold 130°C (minimum).
4. The voltage at OVP is below 0.7 V (typical).
If all these conditions are met, the signal driving the EN pin is able to initiate the soft start process. When the
device is enabled, the 27-µA internal charging current at the SS pin is turned on and begins to charge the softstart capacitor. The EN pin can accept both level-enable and pulse-enable signals.
For level-enable, the voltage level on the EN pin must be continuously higher than 2.25 V to allow continuous
operation. When the EN pin falls below 2.25 V, the device is disabled (see Figure 21).
UVLO
EN
0.3V
SS
CLK
Figure 21. Level Enable at EN pin
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Feature Description (continued)
A pulse signal may also be applied to the EN pin. Pulse-enable operation is shown on Figure 22. As long as the
EN falling edge happens before the SS voltage reaches 0.3 V, the enable signal at EN pin is considered as a
pulse. In this case, the next rising edge at EN pin disables the controller. As long as the falling edge of the first
pulse at EN pin happens after SS rises to 0.3 V, the UCC28250 interprets the pulse enable as a level enable,
and an external solution as shown on Figure 23 (a) can be used to reduce the pulse width. In this circuit, R2 is
used to limit the current (especially the negative current) through the internal ESD cell. Figure 23 (b) illustrates
the waveforms based on this solution. To prevent false trigger by noises, the pulse at the EN pin must be at least
2.25 V (minimum) high and 3 µs wide to be considered valid.
Choose the R1, R2, and C values based on the following equations:
Choose R2 based on the current limit requirement from the device.
R2 > 10kW
(1)
Choose R1 arbitrarily but much smaller than R2 and choose C1 according to the time constant requirement to
generate longer than 3-µs pulse.
C1 =
6 ms
R1
(2)
In the case that the UCC28250 is enabled with a level EN signal and the SS is discharged internally when the
OCP is triggered, pulling the EN pin down before SS rises to 0.3 V cannot disable the part because the controller
interprets it to be a pulse enable. In this case, the next rising edge at the EN pin disables the controller. If the
designer wants to disable UCC28250 with a level signal during an over current condition, the recommended
solution is to pull down the SS pin rather than the EN pin. If the enable function is not used, pull the EN pin to the
VREF pin.
UVLO
EN
SS
0.3V
CLK
Figure 22. Pulse Enable at EN Pin
(a)
(b)
UCC28250
Enable
Signal
C1
R2
EN
Enable
Signal
R1
EN
Figure 23. An External Solution to Generate Enable Pulses for Pulse Enable
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Feature Description (continued)
7.3.4 RT (Oscillator Frequency Set and Synchronization) (15/2)
The UCC28250 oscillator frequency is set by an external resistor connected between the RT pin and ground.
Switching frequency selection is a trade-off between efficiency and component size. Based on the selected
switching frequency, the programming resistor value can be calculated as:
1
- Td(SP )
2 ´ fSW
RT =
33.2pF
(3)
In this equation, fSW is the switching frequency and TD(sp) is the dead time between synchronous rectifier turnoff
to primary switch turnon. TD(sp) is set by an external resistor between the SP pin and ground (refer to SP
(Synchronous Rectifier Turnoff to Primary Output Turnon Dead Time Programming) (13/19)).
Each output (OUTA, OUTB, SRA, SRB) switches at half the oscillator frequency (fSW = ½ x fOSC). Figure 24
shows the relationship between RT and fOSC at certain TD(sp) and can be used to program oscillator frequency
accordingly.
OSCILLATOR FREQUENCY
vs
RT RESISTOR
2000
TD(ps) = 40 ns
1800
FOSC - Oscillator Frequency - kHz
1600
1400
1200
1000
800
600
400
TD(ps) = 100 ns
200
0
0
20
40
60
80
100 120 140 160 180 200
RT Resistor - kW
Figure 24. Oscillator Frequency FOSC vs External Resistance of RT at TD(ps) = 40 ns and 100 ns
The UCC28250 can be synchronized to an external clock by applying an external clock source to the RT pin.
Synchronization helps with parallel operation and/or preventing beat frequency noise. The UCC28250
synchronizes its internal oscillator to an external frequency source ranging from 170 kHz to 2.3 MHz, which is
equivalent to an 85-kHz to 1.15-MHz switching frequency. The internal oscillator frequency is clamped to 170
kHz during synchronization if the external source frequency drops below 170 kHz.
The UCC28250 aligns the turnon of primary outputs OUTA and OUTB to the falling edge of the synchronizing
signal, as shown in Figure 25. If the frequency source is from the gate outputs of another half bridge controller,
interleaving can be achieved. The interleaving angle is determined by the frequency source’s duty cycle. When a
50% duty cycle is applied, optimal interleaving is achieved, and EMI filters can be minimized.
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Feature Description (continued)
Frequency
Source
OUTA
OUTB
Figure 25. Timing Diagram for Synchronization
CLK
OUTA
SRA
Td(SP)
Td(PS)
OUTB
SRB
Td(SP)
Td(PS)
Figure 26. UCC28250 Outputs Timing Waveforms
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Feature Description (continued)
7.3.5 SP (Synchronous Rectifier Turnoff to Primary Output Turnon Dead Time Programming) (13/19)
The dead time TD(sp) between synchronous rectifier turnoff to primary output turnon is programmed by an
external resistor, RSP, connected between the SP pin and ground. The value of RSP can be determined by
Figure 27. Zero dead time can be achieved by tying the SP pin to VREF. The falling edge of synchronous
rectifier SRA/SRB is aligned with the raising edge of the primary output OUTA/OUTB.
NOTE
The minimum value for RPS/RSP is 5 kΩ and the maximum value is 250 kΩ.
SP DEAD TIME
vs
SP RESISTOR
400
350
DSP - SP Dead Time - ns
300
250
200
150
100
50
0
0
20 40 60 80 100 120 140 160 180 200 220 240
RSP - SP Resistor - kW
Figure 27. Dead Time TD(sp) vs. External Resistor RSP at SP Pin
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Feature Description (continued)
7.3.6 PS (Primary Output Turnoff to Synchronous Rectifier Turnon Dead Time Programming) (11/18)
The dead time TD(ps) between primary output turnoff to synchronous rectifier turnon is set by external resistor,
RPS, connected between PS pin and ground. The value of is RPS is defined by Figure 28. Zero dead time can be
achieved by tying the SP pin to VREF.
NOTE
The minimum value for RPS/RSP is 5 kΩ and the maximum value is 250 kΩ.
PS DEAD TIME
vs
PS RESISTOR
400
350
DPS - PS Dead Time - ns
300
250
200
150
100
50
0
0
20 40 60 80 100 120 140 160 180 200 220 240
RPS - PS Resistor - kW
Figure 28. Dead Time TD(ps) vs. External Resistor RPS at PS Pin
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Feature Description (continued)
7.3.7 RAMP/CS (PWM Ramp Input or Current Sense Input) (16/3)
The UCC28250 can be controlled using either voltage mode or current mode. RAMP/CS is a multi-function pin
used either to generate the ramp signal for voltage mode control or to sense current for current mode control.The
following sections describe the RAMP/CS functionality for voltage mode and current mode control.
7.3.7.1 RAMP: Voltage Mode Control With Feed-Forward Operation
For voltage mode control, a resistor RCS and a capacitor CCS must be connected to the RAMP/CS pin as shown
in Figure 29. The internal pulldown switch has approximately 40-Ω on-resistance. The RAMP/CS pin is clamped
internally to 4 V for internal device protection. The CCS value must be small enough to discharge the RAMP/CS
pin from its peak voltage to ground within the pulse width of the BLANK signal (TD(sp) + 70 ns). The following
formula derives a CCS value.
æ 4 V / 2 ö Td(SP) + 70ns
CCS < ç
÷´
4V
è 40 W ø
(4)
A CCS value less than 650 pF works for most applications. To minimize the impacts of parasitic capacitance
caused by the PCB layout and routing, a minimum of 100 pF is recommended for CCS. Once CCS is determined,
RCS can be calculated according to the desired ramp peak amplitude.
RCS =
1
æ VCHARGE
ö
2 ´ ln ç
÷ ´ CCS ´ fSW
è VCHARGE - VPK ø
(5)
In this equation, the VCHARGE is the voltage used to generate the ramp, VPK is the desired ramp amplitude and
the fSW is the switching frequency.
Choose the ramp amplitude to accommodate the voltage range of the COMP pin and the maximum duty cycle
required by the power stage. Use the following equation to select VPK, in the equation, DMAX is the maximum duty
cycle for primary outputs.
VPK =
1.4 V
DMAX
(6)
UCC28250
UCC28250
VIN 36 V to 75 V
VREF
RCS
RCS
RAMP/CS
CCS
RAMP/CS
BLANK
CCS
GND
BLANK
GND
Figure 29. Fixed Ramp Generation/Ramp Generation With Input Voltage Feedforward
Voltage feed-forward can be achieved by driving RCS from line input VIN. The peak of RAMP/CS is proportional
to VIN and output has have much faster line transient response. When the UCC28250 is used for the primaryside control, RAMP parameters are critical for the optimal prebiased start-up performance. Refer to the RAMP:
Voltage Mode Control With Feed-Forward Operation for a detailed design procedure of choosing RCS.
If the line input cannot be easily accessed due to limited board area or other limitation, a RAMP signal with fixed
peak voltage can be implemented by simply driving RCS from 3.3-V VREF (Figure 29).
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Feature Description (continued)
7.3.7.2 CS: Current Mode Control
For current mode control, the RAMP/CS pin is driven by a signal representative of the transformer primary-side
current. The current signal must have compatible input range of the COMP pin. As shown in Figure 30, the
COMP pin voltage is used as the reference for peak current. The primary-side signals OUTA and OUTB are
turned on by the internal clock signal and turned off when sensed peak current reaches the COMP pin voltage.
Choose the current sense transformer turns ratio (1:n) and the burden resistor value (RB) based on the peak
current at maximum load IMAX.
RB =
3V
IMAX / n
(7)
COMP
CS
OUTA
OUTB
Figure 30. Peak Current Mode Control and PWM Generation
7.3.8 REF/EA+ (1/8)
REF/EA+ is the noninverting input of the UCC28250’s internal error amplifier.
When the UCC28250 is configured for secondary-side control, the internal error amplifier is used as the control
loop error amplifier. Connect REF/EA+ directly to the VREF pin to provide the reference voltage for the feedback
loop.
When the UCC28250 is configured for primary-side control, the error amplifier is connected as a voltage follower.
Connect REF/EA+ to the opto-coupler output.
The voltage range on REF/EA+ pin is 0 V to 3.7 V.
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Feature Description (continued)
7.3.9 FB/EA- (2/9)
FB/EA- is the inverting input of the UCC28250’s internal error amplifier.
When the UCC28250 is configured for secondary-side control, connect the output voltage sensing divider to this
pin. The voltage divider can be selected according to the voltage on REF/EA+ pin. Referring to Figure 32, pick
the lower resistor RO1 value arbitrarily, and choose the upper resistor RO2 value as:
æ VO
ö
RO2 = ç
- 1÷ ´ RO1
è VREF / EA +
ø
(8)
Because the control loop gain is affected by voltage divider resistor values, choose an appropriate RO1 value so
that the voltage loop DC gain is larger than 40 dB to prevent interference between the primary-side control loop
and the SR control loop during start-up.
When the UCC28250 is sitting on the primary side, the error amplifier is connected as a voltage follower.
Connect FB/EA- directly with COMP pin.
The maximum voltage allowed on FB/EA- pin is 3.7 V.
7.3.10 COMP (3/10)
The COMP pin is the internal error amplifier’s output and also the input signal for PWM comparator. The
maximum input common voltage of the PWM comparator is 2.8 V. It is suggested to program the peak value of
RAMP to be lower than 2.3 V. Otherwise, the voltage of COMP pin should be clamped to be lower than 2.8 V by
external circuit to make the internal PWM comparator work properly. Figure 31 shows tan external circuit that is
recommended for voltage clamp function. Both the primary-side switches’ duty cycle and secondary-side SRs’
duty cycle is controlled by the COMP pin voltage. At steady state, a higher COMP pin voltage results in a larger
duty cycle for the primary-side switches and a smaller duty cycle on the SRs.
When the UCC28250 controller is set up for secondary-side control, connect the compensation network from the
FB/EA- pin to the COMP pin.
For primary-side control, the error amplifier is connected as a voltage follower. Directly connect the COMP pin to
the FB/EA- pin.
UCC28250
REF
R CS
COMP
C CS
GND
Figure 31. Comp Clamp Circuit
7.3.11 VSENSE (14/1)
The VSENSE pin is used to directly sense the output voltage and to feed it into a transconductance error
amplifier. The measured voltage allows the UCC28250 to achieve optimal prebiased start-up performance.
When configured as a secondary-side controller, the output voltage is sensed and fed into the FB/EA- pin. The
UCC28250 uses a conventional error amplifier approach to allow type III compensation. Therefore, the FB/EApin voltage always follows the REF/EA+ voltage. The FB/EA- pin does not reflect the true output voltage and
therefore this dedicated VSENSE pin is required. The voltage divider connected to VSENSE is discussed in the
Prebiased Start-Up Section.
When UCC28250 is set up as primary-side control, connect VSENSE pin to VREF.
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Feature Description (continued)
7.3.12 SS (Soft Start Programming Pin) (13/20)
The soft-start circuit gradually increases the converter’s output voltage until steady state operation is reached.
This reduces start-up stresses and current surge.
When the UCC28250 reaches its valid operating threshold, the SS pin capacitor is charged with a 27-µA current
source. The UCC28250’s internal error amplifier noninverting terminal follows the SS pin voltage on REF/EA+ pin
voltage depending on which one is lower. Hence, during soft start, the SS pin voltage is lower than REF/EA+.
The internal error amplifier then uses the SS pin as its reference voltage, until the SS pin voltage rises above the
REF/EA+ level. Once the SS pin voltage is above REF/EA+ voltage, soft-start time is considered finished.
The soft-start implementation scheme and timing is different, depending on the location of the UCC28250 with
respect to the isolation barrier.
For secondary-side control, the internal error amplifier is used to achieve the voltage regulation. The REF/EA+ is
connected to an external reference voltage, FB/EA- is connected to the voltage sensing divider, and the error
amplifier’s output pin (COMP) is connected through a compensation filter back to the FB/EA- pin (Figure 32). In
this case, the primary output’s start-up is a closed loop soft start (soft-start input reference of error amplifier). The
output soft-start time is determined by the external capacitor connected at SS pin based on the internal 27-µA
charging current and the voltage set at REF/EA+ pin.
Based on the soft-start time TSS, choose soft start capacitor CSS value as:
CSS =
27 mA ´ TSS
VREF / EA +
(9)
VOUT
UCC28250
VSENSE
CP1
RO2
VREF
RZ3
RS2
RZ2
CZ2
COMP
CZ3
FB/EA-
REF/EA+
+
+
RS1
RO1
SS
CSS
Figure 32. Error Amplifier EAMP Connections for Secondary-Side Control
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Feature Description (continued)
For primary-side control, the internal error amplifier is connected as a buffer stage. In other words, the COMP pin
is shorted to the FB/EA- pin, and the output of an external error amplifier is connected to the REF/EA+ pin
through an optical coupler (Figure 33). In this case, the output start-up is an open loop soft start because the
COMP follows the soft-start voltage instead of the voltage loop output. The soft-start time is still determined by
external capacitor CSS and the 27-µA internal charge current. The voltage depends on the value of final COMP
voltage which corresponds to the regulated primary output duty cycle. According to the desired soft start time and
COMP pin voltage level at steady state, the SS pin capacitor can be calculated as:
CSS =
27 mA ´ TSS
VCOMP _ final
(10)
After soft start, the voltage at SS pin is eventually clamped at around 4 V. Under fault conditions (UVLO, internal
thermal shut down, OVP/OTP, hiccup mode), or when externally disabled, SS pin is pulled down to ground
quickly by an internal switch with 2 kΩ on resistance to prepare for re-start. Pulling SS pin to ground externally
shuts down the controller as well.
VOUT
UCC28250
RO2
CP1
VSENSE
RZ3
CZ2
RZ2
VREF
COMP
CZ3
FB/EA-
+
REF/EA+
+
+
RO1
SS
External
Reference
CSS
Figure 33. Error Amplifier EAMP Connections for Primary-Side Control
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Feature Description (continued)
7.3.13 ILIM (Current Limit for Cycle-By-Cycle Overcurrent Protection) (17/4)
Cycle-by-cycle current limit is accomplished using the ILIM pin for current mode control or for voltage mode
control. The input to the ILIM pin represents the primary current information. If the voltage sensed at ILIM pin
exceeds 0.5 V, the current sense comparator terminates the pulse of output OUTA or OUTB. If the high current
condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the
current sense comparator instead of the PWM comparator. ILIM pin is pulled down by an internal switch at the
rising edge of every clock cycle. This internal switch remains on for an additional 70 ns after OUTA or OUTB
goes high to blank leading edge transient noise in the current sensing loop. This reduces the filtering
requirements at the ILIM pin and improves the current sense response time.
Transformer Primary
Side Current
UCC28250
ILIM
CT
RS
HICC
CS
1:n
CHICC
Figure 34. Current Limit Circuit
Once the over current protection level IPK is selected, the current transformer turns ratio and the burden resistor
value can be decided as:
RS =
0.5 V ´ n
IPK
(11)
In this equation, current transformer turns ratio is 1:n and RS is the burden resistor value.
Some filtering capacitance is required to reduce the sensing noise. Choose the RC constant at about 100 ns,
and calculate the capacitor value as:
CS =
100ns
RS
(12)
The cycle-by-cycle current limit operation time before all four outputs shut down can be programmed by external
capacitor CHICC at HICC pin. (See HICC pin description)
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Feature Description (continued)
7.3.14 HICC (10/17)
The cycle-by-cycle current limit operation time before all four outputs shut down can be programmed by an
external capacitor CHICC from HICC pin to ground, as shown in Figure 34. Once all four outputs are shutdown,
controller goes into hiccup cycle which is about 100 times of the cycle-by-cycle current limit shut-down delay
time. A 1-mA internal current source charges HICC pin up to 2.4 V, then the HICC pin is discharged by a 2.7-µA
internal current source to generate long hiccup restart time until HICC reaches 0.3 V. Based on the system
requirement, once the cycle-by-cycle current limit delay time TOC(delay) is selected, the HICC pin capacitor CHICC
can be selected based on the equation
TOC(delay ) ´ 75 mA
CHICC =
0.6 V
(13)
TOCdealy
THICC
HICC
2.4V
0.6V
0.3V
t
SS
4V
t
OUTA
OUTB
Normal
OC
Normal
OC
Hiccup
Soft Start
Figure 35. Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer
As shown in Figure 35, cycle-by-cycle current limiting shut-down delay time is:
TOC(delay ) = CHICC ´
0.6 V
75 mA
(14)
And hiccup-restart-time THICC is equal to:
THICC = CHICC ´
2.4 V - 0.3 V
2.7 mA
(15)
As soon as the outputs are shut-down, the SS pin is pulled to ground internally until the hiccup restart timer is
reset after time duration THICC.
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Feature Description (continued)
7.3.15 OVP/OTP (19/6)
The OVP/OTP pin provides multiple fault protection functions. If the voltage on the OVP/OTP pin exceeds 0.7 V,
a fault shutdown occurs. All outputs stop switching and stay off (low) during the shutdown, and the SS pin is
pulled to ground internally. Once the fault condition is cleared (that is, OVP/OTP voltage drops below 0.7 V), the
UCC28250 enters hiccup mode. A soft-start cycle begins after the hiccup cycle is finished. An internal 11-µA
switched current source is used to create hysteresis.
If the external resistor divider runs from line voltage VIN, a line overvoltage protection is implemented.
If the external resistor divider runs from the output voltage, output overvoltage fault protection is achieved.
Figure 36 shows the overvoltage protection external configuration at the OVP/OTP pin.
According to the protection threshold VR and recovery threshold VF, choose an arbitrary R2 value. To ensure a
realistic solution, R2 must meet the following:
R2 <
0.7 V ´ (VR - VF )
11mA ´ (VR - 0.7 V )
(16)
The other two resistors, R1 and R3 can be calculated.
R1 =
R3 =
VR - 0.7 V
´ R2
0.7 V
0.7 V ´ (VR - VF ) - 11mA ´ R2 ´ (VR - 0.7 V )
(17)
11mA ´ VR
(18)
If the external resistor divider runs from 3.3-V VREF, and replaces R2 with a positive temperature coefficient
(PTC) thermistor, an overtemperature fault protection with programmable hysteresis is accomplished (Figure 37).
Choose an arbitrary PTC value, which has a resistance as RPTC1 at protection temperature and resistance as
RPTC2 at recovery temperature. Because of its positive temperature coefficient, RPTC1 is larger than RPTC2. To
ensure an available solution, RPTC1 and RPTC2 need to meet the criteria.
0.7 V ´ (RPTC1 - RPTC2 ) - 11mA ´ RPTC1 ´ RPTC2 ³ 0
(19)
And resistors R1 and R3 can be calculated as:
R1 = 3.7 ´ RPTC1
R3 =
(20)
2.6 V ´ ëé0.7 V ´ (RPTC1 - RPTC2 ) - 11mA ´ RPTC1 ´ RPTC2 ûù
11mA ´ (2.6 V ´ RPTC1 + 0.7 V ´ RPTC2 )
(21)
UCC28250
VREF
VIN or VOUT
11 mA
R1
R3
OVP
+
R2
0.7 V
Figure 36. Overvoltage Protection
26
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Feature Description (continued)
UCC28250
VREF
R1
11 mA
R3
OVP
+
0.7 V
PTC
Figure 37. Overtemperature Protection
Figure 38 shows an external configuration using the OVP/OTP pin to achieve both overvoltage and
overtemperature protection. Follow the same design procedure for the OVP setting to choose R1, R2, and R3.
Choose an NTC value at protection temperature much smaller than R1 and with the resistance at protection
temperature as RNTC1, and recover temperature as RNTC2. The R4 value can be calculated as:
R4 =
0.7 V
´ RNTC1
3.3 V - 0.7 V
(22)
Because of the interaction between the two voltage dividers, overtemperature protection thresholds move slightly
with the different input voltages.
UCC28250
VREF
VIN or VOUT
NTC
R1
11 mA
R3
OVP
+
R4
R2
0.7 V
Figure 38. Overvoltage and Overtemperature Protection With Single OVP Pin
7.3.16 OUTA (9/16) and OUTB (8/15)
OUTA and OUTB are the primary-side switch control signals. With the 0.2-A peak current capability, an external
gate driver is required.
7.3.17 SRA (7/14) and SRB (6/13)
SRA and SRB are the synchronous rectifier control signals. With the 0.2-A peak current capability, an external
gate driver is required.
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Feature Description (continued)
7.3.18 GND (4/11)
GND pin is the ground reference for the whole device. Tie all the signal returns to this pin.
7.4 Device Functional Modes
The UCC28250 can be controlled using either voltage mode or current mode. RAMP/CS is a multi-function pin
used either to generate the ramp signal for voltage mode control or to sense current for current mode control.
Refer to RAMP/CS (PWM Ramp Input or Current Sense Input) (16/3) for the details.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC28250 is a high-performance PWM controller with advanced synchronous rectifier outputs and is ideally
suited for regulated half-bridge, full-bridge and push-pull converters. A dedicated internal prebiased start-up
control loop working in conjunction with a primary-side voltage loop achieves monotonic prebiased start-up for
either primary-side or secondary-side control applications. The UCC28250 architecture allows either voltage
mode or current mode control.
Input voltage feedforward can be implemented, allowing PWM ramp generator to improve the converter line
transient response. Advanced cycle-by-cycle current limit achieves volt-second balancing even during fault
conditions. The hiccup timer helps the system to stay within a safe operation range under over load conditions.
With a multifunction OVP/OTP pin, combinations of input voltage protection, output voltage protection and
overtemperature protection can be implemented. The UCC28250 allows individual programming of dead time
between primary-side switch and secondary-side SRs, To allow optimal power stage design. Dead time can also
be reduced to zero, and this allows optimal system configuration considering the delays on the gate driver stage.
The UCC28250 also provides complete system level protection functions, including UVLO, thermal shut down
and overvoltage, overcurrent protection.
8.1.1 Error Amplifier and PWM Generation
The UCC28250 includes a high-performance internal error amplifier with low input offset, high source/sink current
capability and high gain bandwidth (typical 3.5 MHz). The reference of the error amplifier (REF/EA+ pin) is set
externally to support flexible trimming of the voltage loop, and to make the controller flexible for both primary
side, as well as secondary-side control. The extra positive input for the error amplifier is the SS pin which is used
to externally program the soft-start time of the converter’s output.
During steady state operation, the primary switch duty cycle, D, is generated based on the external ramp on
RAMP/CS pin and the COMP pin voltage. A higher COMP pin voltage results in a larger duty cycle. The
secondary-side SR duty cycle is SR_D = (1-D), complementary to the primary-side duty cycle, without
considering the dead time between primary-side switch and secondary-side SR. The primary outputs begin to
switch when COMP pin voltage is above the 350 mV internal offset. The synchronous rectifier outputs only switch
after COMP pin voltage is above 550 mV internal offset. According to the internal logic, the minimum pulse width
for the primary-side OUTA and OUTB is typically 100 ns.
During soft start, the primary-side switch duty cycle is generated based on the external ramp on RAMP/CS pin
and the COMP pin voltage. However, the duty cycle of secondary-side SR is generated based on an internal
ramp and the COMP pin voltage. When the converter is controlled on the primary side, an internal ramp is a
fixed ramp with 3-V peak voltage. When the converter is controlled on secondary side, an internal ramp is
generated based on the internal prebiased start-up loop. An internal prebiased start-up loop modifies the SR duty
cycle during soft start to achieve the optimal prebiased start-up performance.
After the SS pin reaches 2.9 V, the prebiased start-up control loop is disabled. The secondary-side SR
instantaneously changes into its steady state value as complementary to the primary-side duty cycle.
8.1.2 Prebiased Start-Up
With the internal error amplifier, UCC28250 supports both primary-side control and secondary-side control. For
different control methods, the controller is configured accordingly and so is the prebiased start-up control. During
soft start, both the primary-side switches’ duty cycle and secondary-side SRs’ duty cycle are increased. This
gradually increases the output voltage until steady state operation is reached, thereby reducing surge current.
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Application Information (continued)
8.1.2.1 Secondary-Side Control
For secondary-side control, the UCC28250 implements close-loop control of both the primary-side switches and
secondary-side synchronous rectifiers’ duty cycles. This makes it easy to achieve optimal start-up performance.
The internal error amplifier is set up as the control loop error amplifier. Connect REF/EA+, FB/EA-, COMP and
VSENSE as shown in Figure 39. To achieve optimal prebiased start-up performance, the output voltage must be
directly measured. The UCC28250 uses the VSENSE pin to directly sense this output voltage. Choose the
voltage dividers on VSENSE slightly different to the FB/EA- voltage divider so that the voltage on VSENSE pin is
roughly 10% to 15% more than FB/EA- pin voltages. Select RO1 equal to RS1, and RS2 about 10% to 15% smaller
than RO2.
VOUT
UCC28250
VSENSE
CP1
RO2
VREF
RZ3
RS2
RZ2
CZ2
COMP
CZ3
FB/EA-
REF/EA+
+
+
RS1
RO1
SS
CSS
Figure 39. Error Amplifier Set Up for Secondary-Side Control
The error amplifier uses the lower voltage between the SS pin and the REF/EA+ pin to be the reference voltage
for the feedback loop. In this method, the control loop is said to be ‘closed’ during the entire start-up process, as
it is always based on the true output voltage.
During soft start, the primary-side switch duty cycle is controlled by the COMP pin voltage and ramp voltage
generated on the RAMP/CS pin. A higher COMP pin voltage results in larger duty cycle. However, to improve
start-up performance, the secondary-side synchronous rectifier duty cycle is controlled by a separate, internal
ramp signal (generated by a dedicated prebiased start-up loop) and by the COMP pin voltage. This dedicated
prebiased loop is much faster than the regular voltage loop to avoid interaction between the two loops. The startup loop reads the output voltage through a transconductance error amplifier connected to the VSENSE pin.
When the output voltage is higher than the reference, the prebiased start-up loop increases the SR duty cycle to
reduce the output voltage. Conversely, when the output voltage is lower than the reference, the SR duty cycle is
decreased to help maintain higher output voltage. To speed up the start-up time, the minimum duty cycle of the
synchronous rectifier is 50%.
Once the soft start is finished, the prebiased loop is disabled and the duty cycle of the synchronous rectifiers
becomes the complimentary of primary switches’ duty cycle, with some dead time inserted in between.
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Application Information (continued)
8.1.2.2 Primary-Side Control
When the UCC28250 is sitting on the primary side, the internal error amplifier is connected as a voltage follower
and an extra error amplifier is needed on the secondary side for closed loop control. The error amplifier
implementation is shown in Figure 40.
VOUT
UCC28250
RO2
CP1
VSENSE
RZ3
CZ2
RZ2
VREF
COMP
CZ3
FB/EA-
+
REF/EA+
+
+
RO1
SS
External
Reference
CSS
Figure 40. Error Amplifier Setup for Primary-Side Control
In the above configuration, the UCC28250 can only see the control loop feedback voltage, and cannot directly
access the output voltage. The design of the soft-start time is critical to achieve optimal prebiased start-up
performance. Some trial and error approaches are needed to achieve optimal performance. It is also important to
choose the appropriate ramp amplitude. Refer to RAMP/CS (PWM Ramp Input or Current Sense Input) (16/3)
discussion on the detailed design procedure for choosing ramp generation components.
During soft start, regardless of the prebiased condition, the output voltage is always lower than the regulation
voltage, so that the feedback loop is always saturated. When the internal error amplifier is connected as a
voltage follower, the COMP voltage follows the lower of the voltage on the RER/EA+ pin and the SS pin.
Because the feedback loop is saturated, the COMP pin always follows the SS pin voltage, until the output
voltage becomes regulated and the feedback voltage takes over. In this control method, the output voltage
control loop is always saturated, and the controller soft starts the COMP pin voltage. Therefore, it is called open
loop soft start.
The primary-side switch duty cycle is controlled by the COMP pin voltage and by the RAMP/CS pin voltage.
During soft start, the COMP pin voltage follows the SS pin as it is rising, so the primary-side switch duty cycle
keeps increasing. When the output voltage becomes regulated, the feedback voltage becomes less than the SS
pin voltage and the primary-side switch comes controlled by the control loop.
For the primary-side control setup, because output voltage is not directly accessible, the internal prebiased startup loop is disabled by connecting VSENSE to VREF. Instead, the internal ramp used to generate the
synchronous rectifier duty cycle is fixed, with the peak voltage of 3 V. The duty cycle of the synchronous rectifier
increases as the SS pin voltage increases. When the SS pin voltage reaches 2.9 V, the soft start is considered
finished and the synchronous rectifier duty cycle becomes the complementary of the primary-side switch duty
cycle, minus the programmed dead time. Because of different COMP pin voltages at different line voltages, the
SR duty cycle generated by the internal ramp might be different than the complementary of the primary-side
switch duty cycle (1-D). If the duty cycle is too large, the internal logic is able to limit the duty cycle to (1-D).
However, if the duty cycle is too small, when the soft start is finished, the SR duty cycle has a sudden change,
which will cause output voltage disturbance. To optimize the prebiased start-up performance, TI recommends
that the duty cycle change at the end of soft start be as small as possible.
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Application Information (continued)
8.1.2.3 Voltage Mode Control and Input Voltage Feed-Forward
For voltage mode control, a resistor RCS and a capacitor CCS are connected externally at RAMP/CS pin as
shown in Figure 41. A ramp signal is generated on the RAMP/CS pin, at a rate of two times that of the switching
frequency. The generated ramp signal is used to control the duty cycle for both the primary-side switches and
secondary-side synchronous rectifiers. The ramp amplitude can be fixed or variable with the input voltage (input
voltage feedforward).
To realize a fixed amplitude ramp, connect RCS to the VREF pin, so that the ramp capacitor charging voltage is
fixed regardless of line and load condition. The RAMP/CS pin is clamped internally to 4 V for internal device
protection. Because the internal pulldown switch has about 40-Ω on-resistance, the CCS value must be small
enough to discharge RAMP/CS from the peak to ground within TD(sp) + 70 ns (that is, the pulse width of BLANK
signal).
To achieve the input voltage feedforward, the slope of the ramp must be proportional to the input voltage. Tie
RCS to the input line voltage. Because the ramp voltage is much lower than the input voltage, the ramp capacitor
charging current is considered to be proportional to the input voltage. With input voltage feedforward, the COMP
pin voltage should only move slightly even with large input voltage variation. This will provide much better line
transient response for the converter.
UCC28250
UCC28250
VIN 36 V to 75 V
VREF
RCS
RCS
RAMP/CS
CCS
RAMP/CS
BLANK
CCS
GND
BLANK
GND
Figure 41. External Configuration of RAMP/CS Pin With/Without Feed-Forward Operation
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Application Information (continued)
The input voltage feedforward also helps on prebiased start-up. When doing primary-side control to prebiased
start-up, three conditions need to be considered:
8.1.2.3.1 Condition 1
At initial start-up, the primary side must provide enough energy to prevent output voltage dip;
8.1.2.3.2 Condition 2
At the end of soft start, it is required to keep the SR duty cycle change to be as small as possible. With input
voltage feedforward, the COMP pin voltage is virtually fixed for different input voltages. Therefore, before the end
of soft start, the duty cycle is the same for different input voltages. Choose the RCS and CCS following the
procedure.
Considering initial start-up, the RAMP peak voltage should be:
VRAMP
VIN
- VPRE -BIAS
= 2´n
´ VSR(ramp)
2 ´ VPRE -BIAS
(23)
In this equation, VIN is the input voltage because of the feedforward any input voltage should be fine; VPRE-BIAS is
the highest prebias start-up voltage required by the system; n is the tranformer primary to secondary turns ratio
and VSR(ramp) is the internal SR ramp peak voltage 3 V.
Another consideration is at the end of soft start, the SR duty cycle changes from controlled by the soft start, to
complimentary to the primary-side duty cycle. The design should keep the transition as smooth as possible.
Considering this, based on the output voltage and input voltage range, as well as the transformer turns ratio,
calculate the SR duty cycle at different line voltages.
Next, based on the maximum duty cycle on the SR_DMAX, and the internal fixed ramp amplitude 3 V, the COMP
voltage at regulation can be chosen as:
VCOMP( final) = (SR _ DMAX - 0.5 )´ 3 V ´ 2
(24)
8.1.2.3.3 Condition 3
Use the calculated COMP pin voltage to derive the external ramp amplitude
VRAMP =
VCOMP( final)
(1 - SR _ DMAX )´ 2
(25)
According to the calculated ramp voltage from Equation 23 and Equation 25 some trade off is required to pick up
the appropriate ramp voltage. Based on the selected ramp capacitor CCS value, choose the ramp resistor RCS
value:
RCS =
VIN(max) ´ 2
VRAMP ´ CCS ´ fsw
(26)
In this equation, VIN(max) is the maximum input voltage, fSW is the switching frequency.
Because these calculations ignore the dead time and the non-linearity of the ramp, slight modification is expected
to achieve the optimal design. When the input voltage feed forward is not used, refer to RAMP/CS (PWM Ramp
Input or Current Sense Input) (16/3) for RC calculation.
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Application Information (continued)
8.1.2.4 Peak Current Mode Control
For peak current mode control, RAMP/CS pin is connected directly with the current signal generated from a
current transformer. The current signal must be compatible with the input range of the COMP pin. External slope
compensation is required to prevent sub-harmonic oscillation and to maintain flux-balance. The slope
compensation can be implemented by using OUTA and OUTB to charge external capacitors and use the voltage
follower to add into the sensed the current signal, as shown in Figure 42. Follow the peak current mode control
theory to select compensation slope or refer to Modeling, Analysis and Compensation of the Current-Mode
Converter, (SLUA101).
OUTA
OUTB
UCC28250
VREF
Transformer Primary
Side Current
RAMP/CS
CT
BLANK
RS
CS
1:n
Figure 42. UCC28250 Set Up for Peak Current Mode Control
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Application Information (continued)
8.1.2.5 Cycle-by-Cycle Current Limit and Hiccup Mode Protection
Cycle-by-cycle current limit is accomplished using the ILIM pin for both current mode control and voltage mode
control. The input to the ILIM pin represents the primary current information. If the voltage sensed at ILIM pin
exceeds 0.5 V, the current sense comparator terminates the pulse of output OUTA or OUTB. If the high current
condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the
current sense comparator instead of the PWM comparator. ILIM pin is pulled down by an internal switch at the
rising edge of each clock cycle. This internal switch remains on for an additional 70 ns after OUTA or OUTB
goes high to blank leading edge transient noise in the current sensing loop. This reduces the filtering
requirements at the ILIM pin and improves the current sense response time.
UCC28250 makes it possible to maintain flux balance during cycle-by-cycle current limit operation. The duty
cycles of primary switches are always matched. If one switch duty cycle is terminated earlier because of current
limiting, a matched duty cycle is applied to the other switch for the next half switching cycle, regardless of the
current condition, as shown in Figure 43. This matched duty cycle helps to maintain volt-second balancing on the
transformer and prevents the transformer saturation.
CLK
70ns
0.5V
ILIM
OUTA
OUTB
Figure 43. Cycle-by-Cycle Current Limit Duty Cycle Matching
Once the current limit is triggered, the 75-µA internal current source begins to charge the capacitor on HICC pin.
If the current limit condition went away before HICC pin reaches 0.6 V, the device stops charge HICC capacitor
and begins to discharge it with 2.7-µA current source. If the cycle-by-cycle current limit condition continues, HICC
pin reachs 0.6 V, and all four outputs are shut down. The UCC28250 then enters hiccup mode. During hiccup
mode, all four outputs keep low; SS pin is pulled to ground internally; a 2.7-µA current source continuously
discharge HICC pin capacitor; until HICC pin voltage reaches 0.3 V. After that, HICC pin is discharged internally
to get ready for the next HICC event. The whole converter starts with soft start after hiccup mode.
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Application Information (continued)
The cycle-by-cycle current limit operation time before all four outputs shut down is programmed by external
capacitor CHICC at HICC pin. The delay time can be calculated as:
TOC(delay ) = CHICC ´
0.6 V
75 mA
(27)
The hiccup timer keeps all outputs being zero until the timer expires. The hiccup time THICC is calculated as:
THICC = CHICC ´
2.4 V - 0.3 V
2.7 mA
(28)
As soon as the outputs are shut-down, SS pin is pulled down internally until the hiccup restart timer is reset after
time duration THICC. The detailed illustration of HICCUP mode is shown in Figure 44.
TOCdealy
THICC
HICC
2.4V
0.6V
0.3V
t
SS
4V
t
OUTA
OUTB
Normal
OC
Normal
OC
Hiccup
Soft Start
Figure 44. Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer
8.2 Typical Applications
8.2.1 Design Example
The example provided shows how to design a symmetrical half bridge converter of voltage mode control with
UCC28250 on primary side.
Figure 45 is the circuit diagram to be used in this design example. This design example shows how to determine
the values in the circuit associated to UCC28250 programming.
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+
Figure 45. Circuit Diagram in Design Example
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8.2.1.1 Design Requirements
Table 1 shows the specifications for the design example.
Table 1. Specifications for the Design Example
PARAMETER
MIN
TYP
MAX
UNIT
36
48
72
VDC
VIN
Input voltage
VOUT
Output voltage
POUT
Output power
75
IOUT
Output load current
23
A
COUT
Load capacitance
5000
µF
fSW
Switching frequency
PLIMIT
Over-power limit
η
Efficiancy at full load
3.3
VDC
150
W
kHz
150%
90%
Isolation
1500
V
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Step 1, Power Stage Design
The power stage design in this example is standard and the same as that for symmetrical half bridge converter of
voltage mode control. From the standard design, these components are determined. This includes Q1 through
Q4, C1, C2, CT1, D1 and D2, D3, T1, T2 and T3, and U6. Their design is standard. Also, design associated to
current sensing and protection is also standard. This includes CT1, D1, D2, R5 and C5.
8.2.1.2.2 Step 2, Feedback Loop Design
D3 (TLV431) with U6, R6, R9, R10, R12, R13, C11 and C12 are composed of standard type 3 feedback loop
compensation network and output voltage set point. Their design is also standard.
Table 2. Specifications for the Design Example
PARAMETER
MIN
TYP
MAX
UNIT
36
48
72
VDC
VIN
Input voltage
VOUT
Output voltage
POUT
Output power
75
IOUT
Output load current
23
A
COUT
Load capacitance
5000
µF
fSW
Switching frequency
PLIMIT
Over-power limit
η
Efficiency at full load
3.3
150
W
kHz
150%
90%
Isolation
38
VDC
1500
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8.2.1.2.3 Step 3, Programming the Device
8.2.1.2.3.1 Step 3-1
Equation 3 is used to determine RT based on switching frequency, 300 kHz and assumes the dead time of 150
ns.
1
1
- Td(SP )
- 150ns
2 ´ fSW
2 ´ 150kHz
RT =
=
= 94.9kW Þ R4 = 100kW
33.2pF
33.2pF
(29)
8.2.1.2.3.2 Step 3-2, Determine RAMP Resistance and Capacitance
There are two-fold considerations to determine RAMP resistance and capacitance. Equation 23 provides RAMP
consideration for SR initial start-up with prebias. The corresponding RAMP peak voltage is determined with input
voltage low line and maximum prebias output voltage. In the following, T1 turns ratio n = 4.
VRAMP
VIN
36 V
- Vpre -bias
- 3.0 V
= 2´n
´ VSR _ RAMP = 2 ´ 4
´ 3.0 V = 0.750 V
2 ´ Vpre -bias
2 ´ 3.0 V
(30)
Equation 24 and Equation 25 provides RAMP consideration for soft start completion to make duty cycle match
(1-D) = SR_D.
1. Calculate OUTA or OUTB duty cycle at 75-V input voltage, 3.3-V output.
D=
n ´ VO 1 4 ´ 3.3 V 1
´ =
´ = 0.176
VIN
2 75 V / 2 2
2
(31)
2. Calculate SRA or SRB duty cycle.
SR _ D = 1 - D = 1 - 0.176 = 0.82
(32)
3. Calculate the COMP voltage value in steady state (Equation 24).
VCOMP = (SR _ D - 0.5) ´ 3.0 V ´ 2 = (0.824 - 0.5) ´ 3.0 V ´ 2 = 1.944 V
(33)
4. Calculate the RAMP peak value (Equation 25).
VRAMP =
VCOMP
1.944 V
=
= 5.523 V
(D ´ 2) (0.176 ´ 2)
(34)
5. Arbitrary select CRAMP 470 pF, then C3 = 470 pF.
6. Calculate RRAMP.
RRAMP _ 1 =
1
æ
ö
VCHARGE
2 ´ ln ç
÷ ´ CRAMP ´ fsw
è VCHARGE - VRAMP ø
=
1
36 V
2 ´ ln(
) ´ 470pF ´ 150kHz
36 V - 0.750 V
= 336.9kW
(35)
RRAMP _ 2 =
1
æ
ö
VCHARGE
2 ´ ln ç
÷ ´ CRAMP ´ fsw
è VCHARGE - VRAMP ø
=
1
= 92.7kW
75 V
2 ´ ln(
) ´ 470pF ´ 150kHz
75 V - 5.523 V
(36)
As different RAMP resistor values are obtained, at this stage, we may take their average value for initial design.
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8.2.1.2.4 Step 3-3, Determine Soft-Start Capacitance
Determine soft-start capacitance with soft-start time 15 ms.
CSS =
27 mA ´ TSS 27 mA ´ 15ms
=
= 0.101mF Þ C8 = 0.1mF
VCOMP( final)
4.0 V
(37)
8.2.1.2.5 Step 3-4, Determine Dead-Time Resistance
Assuming the dead time is 150 ns, Select R7 = R8 = 121 kΩ based on Figure 27 and Figure 28.
8.2.1.2.6 Step 3-5, Determine OCP Hiccup Off-Time Capacitance
Assuming off time is 0.8 s (Equation 15).
CHICC = THICC ´
2.7 mA
2.7 mA
= 0.8 s ´
= 1.03 mF Þ C7 = 1.0 mF
2.4 V - 0.3 V
2.4 V - 0.3 V
(38)
8.2.1.2.7 Step 3-6, Determine Primary-Side OVP Resistance
Assuming OV_OFF = 73 V, OV_ON = 72 V (Equation 16 to Equation 18).
R2 £
0.7 V ´ (Vr - Vf )
11mA ´ (Vr - 0.7 V )
=
0.7 V ´ (73 V - 72 V )
11mA ´ (73 V - 0.7 V )
= 880 W Þ R2 = 866 W
(39)
VR - 0.7 V
73 V - 0.7 V
´ R2 =
´ 866 W = 89.4kW Þ R1 = 88.7kW
0.7 V
0.7 V
0.7 V ´ (VR - VF ) - 11mA ´ R2 ´ (VR - 0.7 V )
R3 =
=
11mA ´ Vr
R1 =
=
0.7 V ´ (73 V - 72 V ) - 11mA ´ 866 W ´ (73 V - 0.7 V )
11mA ´ 73 V
(40)
= 14 W Þ R14 = 14 W
(41)
8.2.1.2.8 Step 3-7, Select Capacitance for VDD and VREF
As recommended by the data sheet, select C6 = C4 = 1 µF. The final design is shown in Figure 46.
40
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+
+
Figure 46. Schematics of Primary-Side Control Design Example
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8.2.1.3 Application Curves
Figure 47. Load Transient
Figure 48. Output Ripple
Figure 49. Clock Signal and Switching Node Waveform
Figure 50. Enable Turnon Waveform
VGS
VDS
Figure 51. Enable Turnoff Waveform
42
Figure 52. Secondary-Side Switching Waveform
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8.2.2 Secondary-Side Half-Bridge Controller with Synchronous Rectification
UCC28250 also supports secondary-side control. Refer to Figure 53. In this configuration, the UCC28250 can be
used in a design that produces smooth turnon performance with an output prebias condition. The design
example and guidelines are summarized in Designing UCC28250 as a Secondary Side Control for Output TurnOn with a Pre-Bias Condition, SLAA477, and Using the UCC28250EVM-564, SLUU441.
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Figure 53. Secondary-Side Half-Bridge Controller With Synchronous Rectification
44
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9 Power Supply Recommendations
The COMP pin is the internal error amplifier’s output and also the input signal for PWM comparator. The
maximum input common voltage of the PWM comparator is 2.8 V. TI suggests programming the peak value of
RAMP to be lower than 2.3 V. Otherwise, the voltage of COMP pin should be clamp to be lower than 2.8 V by
external circuit to make the internal PWM comparator work properly. Refer to COMP (3/10) for the detail
information.
10 Layout
10.1 Layout Guidelines
To increase the reliability and robustness of the design, the following layout guidelines must be met.
1. REF/EA+ The REF/EA+ pin is the noninverting input of the error amplifier. For secondary side control, this
pin is used to set the reference of voltage loop which decides the output voltage. So it is important to keep it
clear from any of high voltage switching nodes. In addition, a decoupling capacitor located closely is
recommended. For primary side control, this pin must be connected to opto-coupler. it is important minimize
the loop area by running the EA+ signal and GND trace in parallel.
2. FB/EA- Minimize the loop between FB/EA- and COMP and keep it clear from any of high voltage switch
nodes to avoid the noise injection into to the compensation loop.
3. COMP Minimize the loop between FB/EA- and COMP and keep it clear from any of high voltage switch
nodes to avoid the noise injection into to the compensation loop.
4. GND As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon
the integrity of the ground return. Place all decoupling and filter capacitors as close as possible to the device
pins with short traces. The AGND pin is used as the return connection for the low-power signaling and
sensitive signal so it should be separated from the power stage ground to avoid ground bouncing.
5. VDD, VREF The VCC pin must be decoupled to GND by minimum 1-μF ceramic capacitors placed close to
the pins.
6. SRA, SRB, OUTA, OUTB The SRA and SRB gate drive pins can be used to drive the inputs of gate driver or
to directly drive the primary winding of a gate-drive transformer or the to directly drive the input of isolator.
The tracks connected to these pins carry high dv/dt signals. Minimize noise pickup by routing them as far
away as possible from tracks connected to sensitive signal including EA+, EA-, COMP, VSENSE, RT,
RAMP/CS, ILIM, PS, SP.
7. HICC, SS, EN, OVP/OTP The connection track between the pin and external corresponding capacitor should
be short.
8. PS, SP, RT, VSENSE, RAMP/CS, ILIM These pins are noise sensitive so allocate the related resistor as
close as possible with the good ground connection.
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10.2 Layout Example
Figure 54. Layout Example
10.3 Thermal Protection
Internal thermal shutdown circuitry protects the UCC28250 in the event the maximum rated junction temperature
is exceeded. When activated, typically at 160°C, with the maximum threshold at 170°C and minimum threshold at
150°C the controller is forced into a low power standby mode. The outputs (OUTA, OUTB, SRA, SRB) are
disabled. This helps to prevent accidental device overheating. A 20°C hysteresis is added to prevent comparator
oscillation. During thermal shutdown, the UCC28250 follows a normal start-up sequence after the junction
temperature falls below 140°C (typical value, with 130°C minimum threshold and 150°C maximum threshold).
46
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Designing UCC28250 as a Secondary Side Control for Output Turn-On with a Pre-Bias Condition, SLAA477
• Using the UCC28250EVM-564, SLUU441
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC28250PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28250
UCC28250PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28250
UCC28250RGPR
ACTIVE
QFN
RGP
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28250
UCC28250RGPT
ACTIVE
QFN
RGP
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28250
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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