UCC28528DWG4


 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005           
 FEATURES DESCRIPTION The UCC28521 and UCC28528 combination PFC/PWM controllers provide complete control functionality for any off-line power system requiring compliance with the IEC1000−3−2 harmonic reduction requirements. By combining the control and drive signals for the PFC and the PWM stages into a single device, significant performance and cost benefits are gained. D Provides Control of PFC and PWM Power Stages In One Device D Trailing-Edge PFC, Trailing-Edge PWM Modulation D Built-In Sequencing of PFC and PWM Turn-On D 2-A Source and 3-A Sink Gate Drive for Both PFC and PWM Stages D Typical 16-ns Rise Time and 7-ns Fall Time into 1-nF Loads PFC Features − Average-Current-Mode Control for Continuous Conduction Mode Operation − Highly-Linear Multiplier for Near-Unity Power Factor − Input Voltage Feedforward Implementation − Improved Load Transient Response − Accurate Power Limiting − Zero Power Detect PWM Features − Peak-Current-Mode Control Operation − 1:1 PFC:PWM Frequency Option − Programmable maximum Duty Cycle Limit Up to 90% − Programmable Soft-Start APPLICATIONS D High-Efficiency Server and DesktopSupplies D High-Efficiency Telecom AC-DC Converter Based on the UCC28511, the new devices employ an average current mode control architecture with input voltage feedforward. The major difference of the UCC28521/28 is the trailing-edge / trailing-edge (TEM/TEM) modulation scheme for the PFC/PWM stages. The UCC28528 differs from the UCC28521 as its PWM stage does not turn off with the falling bulk voltage. The UCC28528 PWM was designed for low power auxiliary supplies. These devices offer performance advantages over earlier generation combination controllers. A key PWM feature is programmable maximum duty cycle. For the PFC stage, the devices feature an improved multiplier and the use of a transconductance amplifier for enhanced transient response. The core of the PFC section is in a three-input multiplier that generates the reference signal for the line current. The UCC28521/28 features a highly linearized multiplier circuit capable of producing a low distortion reference for the line current over the full range of line and load conditions. A low-offset, high-bandwidth current error amplifier ensures that the actual inductor current (sensed through a resistor in the return path) follows the multiplier output command signal. The output voltage error is processed through a transconductance voltage amplifier. AVAILABLE APPLICATION OPTIONS PART NUMBER PWM STAGE APPLICATION UCC28521 PWM shuts off at 71% of the nomonal bulk voltage ac−dc and main dc−dc converter UCC28528 PWM does not turn off with falling bulk voltage ac−dc and standby converter 
  !"# $ %&'# "$  (&)*%"# +"#', +&%#$ %! # $('%%"#$ (' #-' #'!$  '."$ $#&!'#$ $#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1  "** (""!'#'$, Copyright  2005, Texas Instruments Incorporated www.ti.com 1 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 DESCRIPTION (CONTINUED) The transient response of the circuit is enhanced by allowing a much faster charge/discharge of the voltage amplifier output capacitance when the output voltage falls outside a certain regulation window. A number of additional features such as UVLO circuit with selectable hysteresis levels, an accurate reference voltage for the voltage amplifier, zero power detect, OVP/enable, peak current limit, power limiting, high-current output gate driver characterize the PFC section. The PWM section features peak current mode control (with a ramp signal available to add slope compensation), programmable soft-start, accurate maximum duty cycle clamp, peak current limit and high-current output gate driver. The PWM stage is suppressed until the PFC output has reached 90% of its programmed value during startup. During line dropout and turn off, the UCC28521 allows the PWM stage to operate until the PFC output has dropped to 71% of its nominal bulk output value. The UCC28528 on the other hand allows the PWM stage to operate continuously until the bias falls below the UVLO turn-off threhold. Both devices are available in 20-pin DW package. SIMPLIFIED APPLICATION DIAGRAM PRIMARY SECONDARY + + RECT D1 − − VAC + BIAS UCC28521/28 11 PWRGND GT2 10 12 GT1 VCC 9 13 SS2 14 − REF ISENSE2 8 PKLMT VERR 7 15 CAOUT GND 6 16 ISENSE1 17 MOUT 18 IAC 19 VFF 20 VREF CT_BUFF 5 D_MAX 4 VSENSE 3 RT VAOUT PWM V−LOOP + Z 2 1 Z REF 2 VOUT Z www.ti.com 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted)†} Supply voltage VCC Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Gate drive current (GT1, GT2) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 A Pulsed Sourcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2.5 A Sinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 A Maximum GT1, GT2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC+0.3 V Input voltage VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 11 V D_MAX, SS2, CAOUT, ISENSE1, MOUT, VFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VREF+0.3 V VAOUT, CT_BUFF, ISENSE2, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V Pin Current RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 mA VFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA CT_BUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA VAOUT, VERR, ISENSE2, SS2, CAOUT, IAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Maximum pin capacitance ISENSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 pF Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 0C to 150 0C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 0C to 150 0C Lead temperature 1.6mm (1/16 inch from case for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 0C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute−maximum−rated conditions for extended periods may affect reliability. ‡ Currents are positive into, negative out of the specified terminal. All voltages are referenced to GND. ELECTROSTATIC DISCHARGE (ESD) PROTECTION PARAMETER MAX UNITS Human body model 2.5 CDM 0.5 kV AVAILABLE OPTIONS{} PACKAGED DEVICES OPTIONS PFC:PWM FREQUENCY RATIO UVLO TURN-ON (V) UVLO HYSTERESIS (V) PWM UVLO2 TURN-OFF (V) PWM UVLO2 HYSTERESIS (V) SOIC W−20 (DW) 1:1 10.2 0.5 5.30 1.45 UCC28521DW 1:1 10.2 0.5 − − UCC28528DW † The DW package is available taped and reeled. Add R suffix to device type (e.g. UCC28512DWR) to order quantities of 2,000 devices per reel. ‡ All devices are rated from −40°C to +105°C. AVAILABLE OPTIONS{ PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT THERMAL IMPEDANCE JUNCTION TO CASE TA < 25°C POWER RATING TA < 25°C DERATING FACTOR TA < 105°C POWER RATING 8-pin plastic SOIC (DW) 84.3 °C/W 16.4 °C/W 1.5 W 84.3 mW/°C 0.5 W † Based on low−K PCB ∅ LFM. www.ti.com 3 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 ELECTRICAL CHARACTERISTICS TA = –40°C to 105°C for the UCC2851x, TA = TJ, VCC = 12 V, RT = 156 kΩ, RCT_BUFF = 10 kΩ (unless otherwise noted) supply current PARAMETER TEST CONDITIONS Supply current, off VCC turn-on threshold −300 mV Supply current, on no load on GT1 or GT2 MIN TYP MAX UNITS 100 150 µA 4 6 mA undervoltage lockout (UVLO) PARAMETER TEST CONDITIONS MIN TYP MAX VCC turn-on threshold UCC28521 9.7 10.2 10.8 VCC turn-off threshold UCC28521 9.1 9.7 10.6 UVLO hysteresis UCC28521 0.3 0.5 0.8 UNITS V voltage amplifier PARAMETER Input voltage TEST CONDITIONS MIN TYP MAX 25°C 7.39 7.50 7.61 Over temperature 7.35 7.50 7.65 100 300 VSENSE bias current Open loop gain VSENSE = VREF 2 V ≤ VAOUT ≤ 4 V High-level output voltage ILOAD = –150 µA ILOAD = 150 µA 50 60 UNITS V nA dB 5.3 5.5 5.6 0.00 0.05 0.15 70 100 130 −1 −3.5 1 3.5 MIN TYP MAX UNITS VREF + 0.440 VREF + 0.490 VREF + 0.540 V 300 500 600 Enable threshold 1.7 1.9 2.1 Enable hysteresis 0.08 0.2 0.3 Low-level output voltage gM conductance Maximum source current IVAOUT = −20 µA to 20 µA Maximum sink current V µS mA PFC stage overvoltage protection and enable PARAMETER TEST CONDITIONS Overvoltage reference window Hysteresis 4 www.ti.com mV V 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 ELECTRICAL CHARACTERISTICS TA = –40°C to 105°C for the UCC2851x, TA = TJ, VCC = 12 V, RT = 156 kΩ, RCT_BUFF = 10 kΩ (unless otherwise noted) current amplifier PARAMETER Input offset voltage Input bias current Input offset current Open loop gain TEST CONDITIONS VCM = 0 V, VCM = 0 V, VCAOUT = 3 V VCAOUT = 3 V VCM = 0 V, VCM = 0 V, VCAOUT = 3 V 2 V ≤ VCAOUT ≤ 5 V High-level output voltage 0 V ≤ VCM ≤ 1.5 V, VCAOUT = 3 V ILOAD = –500 µA Low-level output voltage Gain bandwidth product(1) ILOAD = 500 µA See Note 1 Common−mode rejection ratio MIN TYP –5 MAX UNITS 0 5 −50 −100 25 100 mV nA 90 dB 80 5.6 6.3 7.0 0 0.2 0.5 2.0 V MHz oscillator PARAMETER TEST CONDITIONS fPWM, PWM frequency, initial accuracy Frequency, voltage stability TA = 25°C 10.8 V ≤ VCC ≤ 15 V Frequency, total variation Line, Temp MIN 170 dc-to-dc ramp peak voltage TYP MAX 200 230 −1% 1% 160 240 4.5 dc-to-dc ramp amplitude voltage(1) (peak-to-peak) 5.0 UNITS kHz kHz 5.5 4.0 V PFC ramp peak voltage 4.5 5.0 5.5 PFC ramp amplitude voltage (peak-to-peak) 3.5 4.0 4.5 voltage reference PARAMETER Input voltage Load regulation TEST CONDITIONS MIN TYP MAX UNITS 25°C 7.39 7.50 7.61 V Over temperature 7.35 7.50 7.65 V 5 15 1 10 –25 −50 Line regulation IREF = −1 mA to −6 mA 10.8 V ≤ VCC ≤ 15 V Short circuit current VREF = 0V −20 mV mA peak current limit PARAMETER TEST CONDITIONS PKLMT reference voltage PKLMT propagation delay PKLMT to GT1 MIN TYP MAX UNITS –20 0 20 mV 150 300 500 ns multiplier PARAMETER TEST CONDITIONS MIN TYP MAX UNITS IMOUT, high-line low-power output current IMOUT, high-line high-power output current IAC = 500 µA, VFF = 4.7 V, IAC = 500 µA, VFF = 4.7 V, VAOUT = 1.25 V −3 –6 −9 VAOUT = 5 V −75 –90 −110 IMOUT, low-line low-power output current IMOUT, low-line high-power output current IAC = 150 µA, VFF = 1.4 V, IAC = 150 µA, VFF = 1.4 V, VAOUT = 1.25 V −10 –15 −50 VAOUT = 5 V −245 –290 −330 IMOUT, IAC-limited output current Gain constant (k) IAC = 150 µA, VFF = 1.3 V, IAC = 300 µA, VFF = 2.8 V, VAOUT = 5 V −245 –290 −330 0.8 1 1.2 1/V IAC = 150 µA, VFF = 1.4 V, IAC = 500 µA, VFF = 4.7 V, VAOUT = 0.25 V 0 –0.2 µA IMOUT, zero current VAOUT = 0.25 V 0 –0.2 µA IAC = 500 µA, VFF = 4.7 V, IAC = 150 µA, VFF = 1.4 V, VAOUT = 0.5 V Power limit (IMOUT × VFF) VAOUT = 2.5 V VAOUT = 5 V −343 µA 0 –0.2 µA –406 −462 µW 1. Ensured by design. Not 100% tested in production. www.ti.com 5 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 ELECTRICAL CHARACTERISTICS TA = –40°C to 105°C for the UCC2851x, TA = TJ, VCC = 12 V, RT = 156 kΩ, RCT_BUFF = 10 kΩ (unless otherwise noted) zero power PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Zero power comparator threshold Measured on VAOUT, falling edge 0.20 0.33 0.50 V Zero power comparator hysteresis Measured on VAOUT, rising edge 40 90 140 mV PFC gate driver PARAMETER TEST CONDITIONS MIN TYP MAX GT1 pull-up resistance −100 mA ≤ ∆IOUT ≤ −200 mA 5 12 GT1 pull-down resistance IOUT = 100 mA 2 10 16 25 7 15 93% 95% 100% 1% − 7% GT1 output rise time RLOAD = 10 Ω CLOAD = 1 nF, GT1 output fall time Maximum duty cycle Minimum duty cycle (trailing edge) See Note 1 UNITS Ω ns PWM stage undervoltage lockout (UVLO2) PARAMETER TEST CONDITIONS PWM turn-on reference UCC28521 PWM turn-off threshold UCC28521 Hysteresis UCC28521 MIN TYP 6.30 6.75 MAX 7.30 5.3 1.16 1.45 UNITS V 1.74 PWM stage soft-start PARAMETER TEST CONDITIONS SS2 charge current SS2 discharge current UCC28521 Input voltage (VERR) UCC28521 VSENSE = 7.5 V, SS2 = 0 V VSENSE = 2.5 V, SS2 = 2.5 V, (UVLO2 = Low, ENABLE = High) MIN TYP MAX UNITS –7.0 –10.5 –14.0 µA 6 10 14 mA 300 mV IVERR = 2 mA,UVLO2 = Low PWM stage duty cycle clamp PARAMETER Maximum duty cycle TEST CONDITIONS D_MAX = 4.15 V MIN 70% TYP 75% MAX UNITS 80% PWM stage pulse-by-pulse current sense PARAMETER TEST CONDITIONS Current sense comparator offset voltage ISENSE2 = 0 V, 1. Ensured by design. Not 100% tested in production. 6 measured on VERR www.ti.com MIN 1.35 TYP 1.50 MAX 1.65 UNITS V 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 ELECTRICAL CHARACTERISTICS TA = –40°C to 105°C for the UCC2851x, TA = TJ, VCC = 12 V, RT = 156 kΩ, RCT_BUFF = 10 kΩ (unless otherwise noted) PWM stage overcurrent limit PARAMETER TEST CONDITIONS MIN Peak current comparator threshold voltage Input bias current(1) 1.15 TYP MAX 1.30 1.45 50 UNITS V nA PWM stage gate driver PARAMETER TEST CONDITIONS MIN TYP MAX UNITS GT2 pull-up resistance −100 mA ≤ ∆IOUT ≤ −200 mA 5 12 GT2 pull-down resistance IOUT = 100 mA 2 10 Ω 16 25 ns 7 15 ns GT2 output rise time RLOAD = 10 Ω CLOAD = 1 nF, GT2 output fall time Ω 1. Ensured by design. Not 100% tested in production. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION PFC O Output of the current control amplifier of the PFC stage. CAOUT is internally connected to the PWM comparator input in the PFC stage 5 PWM O Internally buffered PWM stage oscillator ramp output, typically used to program slope compensation with a single resistor 4 PWM I Positive input to set the maximum duty cycle clamp level of the PWM stage duty ratio can be between 0.09 and 0.90. NAME NO. Stage CAOUT 15 CT_BUFF D_MAX GND 6 − − Analog ground GT1 12 PFC O PFC stage gate drive output GT2 10 PWM O PWM stage gate drive output IAC 18 PFC I Multiplier current input that is proportional to the instantaneous rectified line voltage ISENSE1 16 PFC I Non-inverting input to the PFC stage current amplifier ISENSE2 8 PWM I Input for PWM stage current sense and peak current limit MOUT 17 PFC I/O PKLMT 14 PFC I Voltage input to the PFC peak current limit comparator PWRGND 11 − − Power ground for GT1, GT2 and high current return paths PFC multiplier high−impedance current output, internally connected to the current amplifier inverting input RT 2 − I Oscillator programming pin that is set with a single resistor to GND SS2 13 PWM I Soft start for the PWM stage VAOUT 1 PFC I/O VCC 9 − I Positive supply voltage pin VERR 7 PWM I Feedback error voltage input for the PWM stage, typically connected to an optocoupler output VFF 19 PFC I Voltage feedforward pin for the PFC stage, sources an IAC/2 current that should be externally filtered VREF 20 − O Precision 7.5-V reference output VSENSE 3 PFC I Inverting input to the PFC transconductance voltage amplifier, and input to the OVP, ENABLE and UVLO2 comparators Output of the PFC transconductance voltage amplifier and it is internally connected to the Zero Power Detect comparator input and the multiplier input www.ti.com 7 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 BLOCK DIAGRAM OSC CLK2 6.75 V CT_BUFF D_MAX VERR ISENSE2 5 4 7 8 SS2 VCC 13 9 UVLO2 + PWM STAGE SOFT START ENABLE 1.9 V 7.5 V REFERENCE 20 VREF + RT 2 3V PFC:PWM Frequency 1:1 = IRT UVLO 10.2 V, 9.7 V + VCC UCC28521 only IRT D_MAX COMP ILIMIT PWM 10 1.3 V 1.5 V R R S + + CLK GT2 Q PWM + CLK CLK PWM PWM 8.0 V PFC VAOUT 3 0.33 V + VCC ÷X MULT X + 7.5 V VFF 19 + (VFF)2 CURRENT AMP MIRROR 2:1 IAC MOUT PFC ZERO POWER 1 gM VOLTAGE ERROR AMP VSENSE PFCOVP + CLK + PWM 18 S 12 GT1 11 PWRGND 14 PKLMT Q R R PFC ILIMIT + 17 16 15 6 ISENSE1 CAOUT GND DETAILED PIN DESCRIPTIONS CAOUT (Pin 15): This is the output of a wide-bandwidth operational amplifier that senses line current and commands the PFC stage PWM comparator to force the correct duty cycle. This output can swing above the PFC ramp peak voltage to command maximum duty cycle and below the PFC ramp voltage to force zero duty cycle when necessary. Connect current loop compensation components between CAOUT and MOUT. CT_BUFF (Pin 5): The 4-V amplitude oscillator ramp is internally buffered at this pin to allow a resistor to be connected directly from this pin to ISENSE2 for slope compensation. The internal buffer can drive a typical 500-µA resistive load at this pin. D_MAX (Pin 4): Program the maximum duty cycle at GT2 by applying a dc voltage to this pin. Between 0.09 and 0.90, the maximum duty ratio is linearly related to D_MAX. Usually, this voltage is set with a precision resistor divider powered by VREF. A first order approximation, with the CT_BUFF frequency near 200 kHz, is estimated by: D MAX ^ V DX * 1.15 V 4V where, DMAX is a dimensionless ratio VDX is the voltage at D_MAX in volts This pin can also be used to set DMAX to 0 by setting VDX less than 0.7 V. 8 www.ti.com 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 DETAILED PIN DESCRIPTIONS (CONTINUED) GND (Pin 6): Signal ground for the integrated circuit. All voltages measured with respect to ground are referenced to this pin. The bypass capacitors for VCC and VREF should connect to this pin with as little lead length as possible. PWRGND must be externally connected to this pin. For best results, use a single small circuit trace to electrically connect between the circuits that use the GND return path and the circuits that use the PWRGND return path. GT1 (Pin 12): A 2-A peak source and 3-A peak sink current totem pole MOSFET gate driver for the PFC stage. Some overshoot at GT1 can be expected when driving a capacitive load, but adding a minimal series resistor of about 2 Ω between GT1 and the external MOSFET gate can reduce this overshoot. GT1 is disabled unless VCC is outside the UVLO region and VREF is on. GT2 (Pin 10): A 2-A peak source and 3-A peak sink current totem pole MOSFET gate driver for the PWM stage, identical to the driver at GT1. IAC (Pin 18): This multiplier input senses the rectified ac line voltage. A resistor between IAC and the line voltage converts the instantaneous line voltage waveform into a current input for the analog multiplier. The recommended maximum IAC current is 500 µA. ISENSE1 (Pin 16): This pin is the non-inverting input terminal of the current amplifier. Connect a resistor between this pin and the grounded side of the PFC stage current sensing resistor. The resistor connected to this pin should have a value that equals the value of the resistor that is connected between the MOUT pin and the ungrounded side of the PFC current sense resistor. ISENSE2 (Pin 8): A voltage across the PWM stage external current sense resistor generates the input signal to this pin, with the peak limit threshold set to 1.3 V for peak current mode control. An internal 1.5-V level shift between ISENSE2 and the input to the PWM comparator provides greater noise immunity. The oscillator ramp can also be summed into this pin for slope compensation. Figure 31 shows the typical relationship of the capacitance on the ISENSE2 pin and the minimum controllable limit of the pulse width on the gate2 output. If the VERR is at the voltage that corresponds to a minimum controllable duty cycle and then is reduced further the pulse width collapses to near zero. MOUT (Pin 17): The output of the multiplier and the input to the current amplifier in the PFC stage are internally connected at this pin. Set the power range of the PFC stage with a resistor tied between the MOUT pin and the non-grounded end of the PFC current sense resistor. Connect impedance between the MOUT pin and the CAOUT pin to compensate the PFC current control loop. The multiplier output is a current and the current amplifier input is high impedance. The multiplier output current is given by: I MOUT + ǒVVAOUT * 1.0Ǔ K ǒVVFFǓ I IAC 2 where, K is the multiplier gain constant, in volts−1. IMOUT is limited to two times IAC for power limiting. PKLMT (Pin 14): Program the peak current limit of the PFC stage using this pin. The threshold for peak limit is 0 V. Use a resistor divider between VREF and the non-grounded side of the PFC current sense resistor in order to shift the level of this signal to a voltage that corresponds to the desired overcurrent threshold voltage, measured across the PFC current sense resistor. PWRGND (Pin 11): Ground for the output drivers at GT1 and GT2. This ground should be tied to GND externally via a single Kelvin connection. www.ti.com 9 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 DETAILED PIN DESCRIPTIONS (CONTINUED) RT (Pin 2): A resistor between RT and GND programs the oscillator frequency, measured at CT_BUFF. In all options, the PWM stage operates at the frequency that is measured at CT_BUFF. In the UCC28521 the PFC stage operates at the same frequency as the PWM stage. The voltage is dc (nominally 3 V); do not connect a capacitor to this pin in an attempt to stabilize the voltage. Instead, connect the GND side of the oscillator-programming resistor closer to the GND pin. The recommended range of resistors is 45 kΩ to 500 kΩ for a frequency range of 600 kHz to 65 kHz, respectively. Resistor RT programs the oscillator frequency fS, as measured at CT_BUFF, according to the following equation: RT + 31 ǒ 1 1 * 2.0 10 *12 f S Ǔ 10 *7 where, RT is in Ω fS is in Hz SS2 (pin 13): A capacitor between SS2 and GND programs the softstart duration of the PWM stage gate drive. When the UVLO2 comparator enables the PWM stage, an internal 10.5-µA current source charges the external capacitor at SS2 to 3 V to ramp the voltage at VERR during startup. This allows the GT2 duty cycle to increase from 0% to the maximum clamped by the duty cycle comparator over a controlled time delay tSS given by: C SS2 + t SS 10.5 3 10 *6 , Farads In the event of a disable command or a UVLO2 dropout, SS2 quickly discharges to ground to disable the PWM stage gate drive. VAOUT (Pin 1): This transconductance voltage amplifier output regulates the PFC stage output voltage and operates between GND and 5.5 V maximum to prevent overshoot. Connect the voltage compensation components between VAOUT and GND. When this output goes below 1 V, the multiplier output current goes to zero. When this output falls below 0.33 V, the zero power detect comparator ensures the PFC stage gate drive is turned off. In the linear range, this pin sources or sinks up to 30 µA. A slew rate enhancement feature enables VAOUT to sink or source up to 3.3 mA, when operating outside the linear range. VCC (Pin 9): Chip positive supply voltage that should be connected to a stable source of at least 20 mA between 12 V and 17 V for normal operation. Bypass VCC directly to GND with a 0.1 µF or larger ceramic capacitor to absorb supply current spikes caused by the fast charging of the external MOSFET gate capacitances. VERR (Pin 7): The voltage at this pin controls the GT2 duty cycle and is connected to the feedback error signal from an external amplifier in the PWM stage. This pin is clamped to a maximum of 3 V and can demand 100% duty cycle at GT2. The typical pull-up current flowing out of this pin is 10 µA. VFF (Pin 19): The output current from this pin comes from an internal current mirror that divides the IAC input current by 2. The input voltage feedforward signal for the multiplier is then generated across an external single-pole R/C filter connected between VFF and GND. At low line, the VFF voltage should be set to 1.4 V. VREF (Pin 20): This is the output of an accurate 7.5-V reference that powers most of the internal circuitry and can deliver over 10 mA, with a typical load regulation of 5 mV ensured for an external load of up to 6 mA. The internal reference is current limited to 25 mA, which protects the part if VREF is short-circuited to ground. VREF should be bypassed directly to GND with a ceramic capacitor between 0.1 µF and 10 µF for stability. VREF is disabled and remains at 0 V when VCC is below the 9.7-V UVLO threshold. VSENSE (Pin 3): Inverting input to the PFC transconductance voltage amplifier, which serves as the PFC feedback connection point. When VSENSE operates within +/− 0.35 V of its steady-state value, the current at VAOUT is proportional to the difference between the VREF and VSENSE voltages by a factor of gM. Outside this range, the magnitude of the current of VAOUT is increased in order to enhance the slew rate for rapid voltage control recovery in the PFC stage. Decisive activation and deactivation of the voltage control recovery is internally implemented with about 120 mV of hysteresis at VSENSE. VSENSE is internally connected to the PFC OVP, Enable and UVLO2 comparators as well. 10 www.ti.com 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 APPLICATION INFORMATION D2 L1 D3 PRIMARY SECONDARY + + R3 D1 R6 T1 D4 C2 VOUT C1 R1 Q1 − Q2 R4 R2 R5 GND2 VAC PGND R9 R8 PGND C5 AGND C6 R14 C7 R13 U1 12 GT1 VCC 9 13 SS2 ISENSE2 8 14 PKLMT VERR 7 15 CAOUT GND 6 16 ISENSE1 CT_BUFF 5 17 MOUT D_MAX 4 18 IAC VSENSE 3 19 VFF RT 2 VAOUT 1 20 VREF R15 R11 D5 C3 AGND UCC28521/28 GT2 10 11 PWRGND R7 R12 R10 C8 REF C9 REF R16 C4 R17 R22 D6 R18 GND2 C14 AGND PGND R19 R20 C10 U2 R23 C13 R25 R25 C12 C11 U3 TL431 R21 AGND R24 GND2 Figure 1. Typical Application Circuit: Boost PFC and Flyback PWM Power System The UCC28521 combination controller includes a power factor correction (PFC) controller that is synchronized with a pulse width modulator (PWM) controller integrated into one chip. The PFC controller has all of the features for an average current mode controlled PFC. The PWM controller has all of the features for an isolated peak current program mode controlled converter. The two controllers are internally synchronized at a fixed frequency with both the PFC controller and the PWM controller are trailing edge modulated (TEM). www.ti.com 11 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 APPLICATION INFORMATION design procedure The following discussion steps through the typical design process of a PFC/PWM converter system. The design process begins with the power stage elements, then the control elements for the PFC stage, then the control elements for the PWM stage. Keep in mind that a general design process is often iterative. Iteration typically begins after either simulating and/or testing the completed PFC/PWM system. This design procedure refers to the typical application in Figure 1. A design begins with a list of requirements for output voltage, output power and ac line voltage range. Other details, such as efficiency and permissible current harmonics could be given at the onset, or developed throughout the product design cycle. The need for power factor correction arises from either an agency requirement, such as EN−61000, or if the available line power is nearly equal to the output power of the power system. Hold-up time requirements are also necessary at the early stages of design. Typically, the hold-up time, tHU, is at least the period of 1.5 line cycles. The general structure of the PFC/PWM stage power system is two switched-mode converters connected in cascade. Each stage has an associated efficiency and each stage has its own set of fault limiting controls that must be properly set in order to achieve the desired line harmonic and load regulation performance, simultaneously. The PFC stage must always be designed to supply sufficient average power to the PWM stage. The cycle-by-cycle current limit of the PFC stage should be programmed to activate at a slightly larger power level at low ac line voltage than the average power clamp in order to allow for PFC current sense tolerances. This will allow power factor correction for the full range of maximum rated load. If the instantaneous load nearly equals the average load, then the fault clamps for the PWM stage can be programmed to limit power at a level that is slightly less than or equal to the average power clamp of the PFC stage. The margin for the clamping action should allow for measurement tolerances and efficiency. Conversely, if the instantaneous load has high peaks that are much shorter than the hold-up time, the current limit and duty ratio limits of the PWM stage can clamp at a higher level than the average power clamp in the PFC stage. In order to simplify the design procedure, the average and the peak loads of the PWM stage are assumed to be equal. Thus, all of the current limits and duty cycle limits are programmed to clamp power at a slightly lower level (10%) than the average power clamp on the PFC stage. developing the internal parameters Select the energy storage voltage VC1. Since the PFC stage is a boost converter, the voltage across C1 must be larger than the peak ac line voltage by enough to permit controllability in the event of load transients. Typically, this will be around 5% which is about 400 V for a universal ac line application of 85 VAC to 265 VAC. Once the energy storage voltage, VC1, is determined, the range of the PFC stage duty ratio, D1, is set. For CCM operation of the PFC stage, the minimum PFC duty ratio is given by: D 1(min) + 1 * 12 Ǹ2 VAC MIN V C1 (1) www.ti.com 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 APPLICATION INFORMATION Select an approximate switching frequency for the PFC stage. A good starting frequency for a MOSFET based PFC stage is in the range of 100 kHz to 200 kHz, depending on maximum line voltage and maximum line current. Adjustments in switching frequency may result from meeting switching loss requirements in Q1 and D3, or in order to optimize the design of L1. Select an appropriate topology for the PWM stage using the information about the power requirements and the magnitude of VC1. For simplicity, the typical application in Figure 1 shows a flyback converter in the PWM stage. In most cases, the PWM stage topology must have transformer isolation and the topology must require only one pulse-width signal. Topologies that have these features include: • • • • single-transistor forward converter single-transistor flyback converter two-transistor forward converter two-transistor flyback converter Estimate the nominal and the maximum duty ratios of the PWM stage (D2(nom) , D2(max) and the associated peak Q2 drain current, iQ2(peak)), based on the topology, PWM hysteresis option and output voltage requirements of the PWM stage. Also estimate whether or not it is appropriate to operate the PWM stage at the same switching frequency as the PFC stage or if the PWM stage can operate at twice the switching frequency of the PFC stage. Base the estimation for the switching frequency of the PWM stage on the maximum voltages and currents of the power MOSFETs and power diodes. Program the oscillator frequency of the PWM stage with the value of R20. R20 + 31 ǒ 1 1 * 2.0 10 *12 f S(pwm) Ǔ 10 *7 , W (2) Most applications require that the PWM stage regulates at the minimum energy storage capacitance voltage. Maximum duty ratio D2(max) and iQ2(peak) should be calculated for the minimum energy storage voltage in order to estimate the peak current stresses for transformer T1 and any other inductive element in the PWM stage. At this point, enough information is available to estimate which member of the UCC28510 family should be selected. www.ti.com 13 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 APPLICATION INFORMATION power stage elements The power stage elements include the following elements: C1−3, D1−5, L1, R2, R5, Q1, Q2, T1. Details concerning the PWM stage elements C2, D4, D5, Q2 and T1 will not be discussed in detail here, due to their dependence on the choice PWM stage topology. The PWM stage is an isolated dc-to-dc topology with the same stresses and loss mechanisms that are typical for the selected topology. An estimation of the average steady state duty ratio of the PWM stage and the Q2 switch current will be needed for stress estimations in the PFC stage. Also, the natural step response of the PWM stage is required to estimate the soft start capacitor, C5, and the bias supply capacitor, C3. The selection process of the PFC stage elements C1, C3, D1−3 and Q1 are discussed in detail here. In general, the selection process for the PFC stage elements is the same as for a typical fixed switching frequency PFC design, except for capacitor C1 due to PFC/PWM stage synchronization. Diode bridge D1 is selected to withstand the rms line current and the peak ac line voltage. Diode D2 allows capacitor C1 to charge during initial power up without saturating L1 and it is selected to withstand the peak inrush current and peak of the maximum ac line voltage. Additional inrush current limiting circuitry in series with the ac line could be required, depending on agencies or situations. The PFC stage inductor, L1, is selected to have a maximum current ripple at the minimum ac line voltage. Typically a ripple factor, kRF, is chosen to be about 0.2. If the line current has excessive crossover distortion, a larger ripple factor (perhaps 0.3) will reduce the distortion but the line current will have more switching ripple. Initially, the inductance can be estimated by approximating the input power equal to the output power. L1 + V AC(min) where, k RF + 2 D 1(min) k RF T S(pfc) P IN Di L1(p−p) i L1(max) and T S(pfc) is (3) 1 switching frequency of the PFC Inductor L1 must be designed to withstand the maximum ac rms line current without saturation at the peak ac line current. Select power MOSFET Q1 and diode D3 with the same criteria that is normally used for fixed switching frequency PFC design. They must have sufficient voltage rating to withstand the energy storage voltage, VC1 and they must have sufficient current ratings. Gate drive resistor R9 is necessary to limit the source and sink current from the GT1 pin. Some circumstances require additional gate drive components for improved protection and performance.[10] A similar gate drive resistor, R10, is required between the GT2 pin and the gate of Q2 for the same reason. 14 www.ti.com 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 APPLICATION INFORMATION The current sense resistor for the PFC stage, R2, is selected to operate over a 1-V dynamic range (VDYNAMIC). The sense resistor must also have a large enough power rating to permit safe operation with the maximum RMS line current. R2 + V DYNAMIC i L1(max) ) 0.5 Di L1(p−p) where, i L1(max) + (4) Ǹ2 P IN V AC(min) The PFC ILIMIT comparator threshold is at the ground reference for the controller device. So, the PFC current sense voltage, measured at PKLMT must be biased with a positive voltage to cross 0.0 V when the instantaneous PFC current is at its maximum. The bias voltage is established with R14 and R7, as shown in equation 7, and resistor R14 is arbitrarily chosen around 10 kΩ. R7 + R14 1 VREF *1 iL1(max) R2 (5) The capacitance value of the energy storage capacitor, C1 is selected to meet hold-up time requirements (tHU) by the equation: C1 + 2P OUT t HU V C1 * ǒV C1 * 0.7V C1Ǔ 2 2 (6) Capacitor C1 must be rated for the selected energy storage voltage and it must be able to withstand the rms ripple current, IC1(rms), that is produced by the combined action of the PFC stage and the PWM stage. The average Q2 drain current during the interval that GT2 activates MOSFET Q2 is used to find IC1(rms). An initial estimate can be made using the inequality in equation 9, then consult Figure 2 for better accuracy. I C1(rms) + P OUT Ǹ 16 V BOOST *1 3 * p V AC(max) (7) The ratio of IC1(rms) to IQ2 can be found by using the appropriate graph, Figure 3 for the 1X:1X oscillator option or Figure 4 for the 1X:2X oscillator option. To use the graphs, locate the ratio of VAC to VC1 along the horizontal axis then, draw a vertical line to the intersection of the curve for the duty ratio of the PWM stage. Draw a horizontal line from the intersection to the vertical axis and read the ratio of IC1(rms) to IQ2. www.ti.com 15 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 APPLICATION INFORMATION The current sense resistor for the PWM stage, R5, is selected so that at maximum current, its voltage is the threshold voltage of the peak current comparator (nominally 1.3 V). R5 + V THǒPWM stage I LIMITǓ i Q2(peak) (8) In many cases, an input line filter will be necessary in order to meet the requirements of an agency or application. The input line filter design has been omitted from this procedure due to the vast array of requirements and circumstances. We urge you to refer to Reference [11] for details. PFC stage control The PFC stage is designed in a three-step process. First, set the dynamic range of the multiplier, second, stabilize the average current control loop and third, stabilize the voltage loop that controls the energy storage capacitor voltage. Use as much of the dynamic range of the multiplier as possible. The current control loop must have wide bandwidth in order to follow the instantaneous rectified line voltage. The voltage loop must be slower than twice the ac line frequency so that it will not compromise the power factor. multiplier The dynamic range of the multiplier is a function of the currents and/or voltages of the IAC, VAOUT and VFF pins. Coordinate the selection process to use the full range of the multiplier and obtain the desired power limiting features. Select the components R1 and R15 to use the iIAC(t) range and the VVFF range under the condition that the maximum of the VVAOUT range, described in equation 11. The selection process is similar to the selection process for UC3854, except for the VFF voltage and MOUT current limitations.[12] In this product series, the divide-by-square function is internally implemented so that it divides by the greater of 1.4 V or VVFF. If the 1.4-V level controls the divider, power factor correction may still occur if the VAOUT level is within the functioning range of the multiplier. Power factor correction occurs during that condition because the multiplier section functions as a two-input multiplier, rather than a three-input multiplier. Notice that the voltage at the VFF pin will be proportional to the average of the IAC current. Typically, VVFF=1.4 V at low ac line voltage is set as the design boundary; the upper boundary of VVFF will remain within the range if the functional ac line voltage range varies by less than 4.3:1. 0 v i IAC(t) v 500 mA, (9) 0 v V VAOUT(t) v 5 V, 1.4 V v V VFF v V VREF * 1.4 V 16 www.ti.com 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 APPLICATION INFORMATION The selection process begins with the selection of R1 so that the peak IAC current at high ac line is about 500 µA, see Table 2. Second, select R15 for the minimum VFF voltage, also shown in Table 2. Third, select C8, in Table 2, to average the VFF voltage with sufficiently low ripple to meet a third harmonic distortion budget. For a system with a 3% THD target, it is typical to allow the feedforward circuit to contribute 1.5% third harmonic distortion to the input waveform [4]. An attenuation factor of 0.022 will meet the criteria. Finally, select the MOUT resistor in Table 2, R12, so that the voltage across R12 equals the voltage across sense resistor R2 under the condition of maximum power, minimum ac line voltage (VVFF, MIN), and VAOUT at its maximum level of 5 V. Experimentally, the multiplier output resistor, R12, may need to be increased slightly if the energy storage capacitor voltage sags under maximum load. This would be due to tolerances in the components and the multiplier. In order to minimize current amplifier offsets, set the value of the resistor on the ISENSE1 pin, R8, equal to the value of R12 as shown in in Table 2. Table 1. REFERENCE DESIGNATOR EQUATION Ǹ2 V R1 I AC(max) 2 C8 R1 P V R8 IN V VFF(avgmin) AC(min) IAC(peak) + 500 mA set V VFF(avgmin) + 1.4 V 0.9 1 p 2 R12 set i IAC(peak) V R15 NOTES f AC A FF(2) (R1)(R2)k VAOUT(max) *1 ǒ A R15 V VFF(min) V AC(min) Ǔ 2 FF(2) + 0.022 for 3% THD k=1 VVFF(min) = 1.4V VVAOUT(max) = 5.0V Always change R8 if R12 is changed R12 PFC current loop control This controller uses average current loop control for the PFC stage. The current control loop must typically be fast enough to track the rectified sinusoidal ac line voltage. There are many ways to design a controller that will stabilize the PFC current loop. The method that is described here achieves good results for most applications.[5] This method assumes that both the natural frequency of the system and the zero of the linearized boost PFC are much lower than both the switching frequency and the desired crossover frequency, fCO(pfc), as described in equation 12. The left side of the inequality in equation 12 will usually be true since the capacitance of C1 is quite large. 1 * D PWM(min) ǸL1 C1 2P IN and C1 V C1 2 tt 2 p f CO(pfc) tt 2 p f S(pfc) (10) www.ti.com 17 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 APPLICATION INFORMATION The left side of the inequality should be at least a factor of 10 lower than the middle term; the right side of the inequality should be at least five times larger than the middle term. For the purposes of 50 Hz to 60 Hz power factor correction, good results can be achieved with the crossover frequency set to about 10 kHz. A lower crossover might be necessary if the switching frequency of the PWM stage is below 100 kHz, or if the compensator gain at the crossover frequency is large (over ~40 dB). Upon selecting the crossover frequency, select R13 to set the gain at the crossover frequency, then select C6 to place a zero at the crossover frequency and select C7 to provide a pole at half of the switching frequency. The equations are in Table 3. Table 2. REFERENCE DESIGNATOR EQUATION 2 R13 p f R12 C6 R13 C7 p CO(pfc) L1 V 2 1 p f NOTES V CT_BUFF(p−p) V CT_BUFF(p−p) +4V C1 CO(pfc) 1 f S(pfc) PFC voltage loop The voltage loop must crossover at a lower frequency than twice the ac line frequency so that voltage corrections will not interfere with power factor correction. Second harmonic ripple from the sensed VC1 voltage directly results in third harmonic distortion on the ac line, similar to ripple on the VFF voltage. PWM stage control The control elements of the PWM stage are the same as a typical isolated current program mode converter. The secondary elements include C12 to C14, D6, R22 to R25, U2 and U3, which perform the error amplifier, compensation and isolation functions. On the primary side, VERR is connected to the node between the opto-isolator output, U2, and a pull-up resistor, R17. Resistor R17 represents the gain in the conversion from the output current of opto-isolator U2 and the VERR input. Slope compensation is programmed using resistors R18 and R11, which form a summing node at ISENSE2. The voltage at CT_BUFF is a saw-tooth waveform that swings between 1 V and 5 V. Many applications require a duty ratio limit for the PWM stage in order to prevent transformer saturation. Program the maximum duty ratio using the following ratio of resistors R16 to R19. V VREF R16 + *1 R19 1 ) 4 D PWM(max) (11) Soft-start The soft-start capacitor, C5, which is connected to SS2, controls the soft-start ramp of the PWM stage. The soft-start ramp begins when the VSENSE voltage exceeds 6.75 V. In order to avoid loop saturation, the soft-start ramp rate must be less than or equal to the open loop response of the PWM stage converter. 18 www.ti.com 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 REFERENCE DESIGN Universal line input 100-W PFC output with 12 V, 8-W bias rail supply design is discussed in UCC28517EVM, TI literature number SLUU117. UCC28517 is a closely related combo device to the UCC28521. The UCC28517 has 1:2 PFC:PWM frequency option. The schematic is shown in Figures 2, 3, 4. Please refer to the SLUU117 document on http://www.ti.com for further details. + Figure 2. Section A + Figure 3. Section B www.ti.com 19 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 REFERENCE DESIGN Note: D10 and D9 are Schottky diodes from Vishay, part no. BYS10−25 Figure 4. Section C 20 www.ti.com 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS STARTUP CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 5.0 140 130 ICC − Supply Current − mA ICC(off) − Startup Current − µA 4.8 120 110 100 UCC 28521 4.6 4.4 4.2 4.0 3.8 3.6 3.4 90 3.2 3.0 80 −50 −25 0 25 50 75 100 125 −50 −25 Temperature − °C 25 50 75 100 125 Temperature − °C Figure 5 Figure 6 SUPPLY CURRENT vs SUPPLY VOLTAGE REFERENCE VOLTAGE vs TEMPERATURE 4.5 7.60 10.2 V UVLO Turn-On Threshold 4.0 7.58 VREF − Reference Voltage − V 3.5 ICC − Supply Current − mA 0 3.0 2.5 2.0 1.5 1.0 7.56 7.54 7.52 7.50 7.48 7.46 7.44 0.5 7.42 0.0 7.40 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 −50 −25 0 25 50 75 100 125 Temperature − °C VCC − Supply Voltage − V Figure 8 Figure 7 www.ti.com 21 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS VREF vs LOAD CURRENT VREF CURRENT LIMIT 7.500 7.0 7.495 6.0 7.490 5.0 VREF − V VCC = 10 V VREF − Reference Voltage − V 8.0 7.485 4.0 7.480 3.0 VCC = 12 V 7.475 2.0 7.470 1.0 7.465 0.0 7.460 0 10 20 30 40 VCC = 15 V 0.0 VREF − External Load Current − mA 5.0 Figure 9 15.0 20.0 Figure 10 PFC UVLO THRESHOLDS vs TEMPERATURE (UCC28521) PWM UVLO2 THRESHOLDS vs TEMPERATURE (UCC28521) 12 8 UVLO On UVLO2 On 7 10 UVLO Off UVLO2 Threshold − V UVLO Threshold − V 10.0 IREF − External Load Current − mA 8 6 4 6 UVLO2 Off 5 4 3 2 UVLO2 Hysteresis 2 UVLO Hysteresis 1 0 0 −50 22 −25 0 25 50 75 100 125 −50 −25 0 25 50 Temperature − °C Temperature − °C Figure 11 Figure 12 www.ti.com 75 100 125 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs RT OVER VCC (11 V TO 15 V) (−40°C TO 105°C) OSCILLATOR FREQUENCY vs RT 800 1000 f - Oscillator Frequency − kHz f - Oscillator Frequency − kHz 700 100 600 500 400 300 200 100 0 0 10 100 10 1000 100 1000 RT − Timing Resistor − kΩ RT − Timing Resistor − kΩ Figure 13 Figure 14 GT1 MAXIMUM DUTY CYCLE vs PFC SWITCHING FREQUENCY (CAOUT = 0.85 V) GT1, GT2 PULL-UP, PULL-DOWN RESISTANCE vs TEMPERATURE 8 100 RDS(on) − Gate Resistance − Ω GT1 Maximum Duty Cycle − % 7 99 98 97 96 95 6 Pull-up 5 4 3 2 Pull-down 1 0 94 0 100 200 300 400 500 −50 −25 0 25 50 75 100 125 Temperature − °C GT1 Switching Frequency − kHz Figure 15 Figure 16 www.ti.com 23 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS GT1 RISE/FALL TIME vs CLOAD AND RSERIES (VCC = 12 V) GT1, GT2 RISE AND FALL TIMES vs TEMPERATURE 18 45 tR: RSERIES = 2 Ω 35 16 tR, tF − Rise and Fall Time − ns tR, tF − Rise and Fall Time − ns 40 tF: RSERIES = 2 Ω 30 25 tR: RSERIES = 10 Ω 20 tF: RSERIES = 10 Ω 12 tR 14 12 10 8 6 10 4 5 2 0 0 0 4 2 tF −50 6 −25 Figure 17 75 100 125 MULTIPLIER OUTPUT CURRENT vs VOLTAGE ERROR AMPLIFIER OUTPUT 100 350 100 kHz IMOUT − Multiplier Output Current − µA 90 GT2 Maximum Duty Cycle − % 50 Figure 18 GT2 MAXIMUM DUTY CYCLE vs D_MAX VOLTAGE 200 kHz 70 500 kHz 60 50 800 kHz 40 30 20 300 IAC = 150 µA VFF = 1.4 V 350 IAC = 300 µA VFF = 2.8 V 200 150 100 IAC = 500 µA VFF = 4.7 V 50 10 0 0 1.0 1.5 2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 D_MAX Voltage − V Figure 19 24 25 Temperature − °C CLOAD − nF 80 0 1.0 4.0 2.0 VAOUT − Voltage Error Amplifier Output − V Figure 20 www.ti.com 6.0 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS MULTIPLIER CONSTANT POWER PERFORMANCE MULTIPLIER GAIN vs VOLTAGE ERROR AMPLIFIER OUTPUT 500 2.0 VAOUT = 5 V 450 400 IMOUT x VFF − µW Multiplier Gain − K 1.8 1.6 1.4 IAC = 150 µA, VFF = 1.4 V 1.2 VAOUT = 4 V 350 300 350 VAOUT = 3 V 200 150 VAOUT = 2 V 100 IAC = 300 µA, VFF = 2.8 V 1.0 50 IAC = 500 µA, VFF = 4.7 V 0 0.8 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 0 5.5 VAOUT − Voltage Error Amplifier Output − V 2 5 Figure 22 CURRENT AMPLIFIER OPEN LOOP GAIN AND PHASE 120 150 gm − VEA Transconductance − µs 120 Phase Gain − dB, Phase − Degree 4 VFF − Feedforward Voltage − V Figure 21 90 60 3 Gain 30 0 −30 VOLTAGE AMPLIFIER TRANSCONDUCTANCE vs TEMPERATURE 100 80 60 40 20 −60 0 −90 1 102 104 106 108 −50 −25 0 25 50 Frequency − Hz Temperature − °C Figure 23 Figure 24 www.ti.com 75 100 125 25 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS VOLTAGE AMPLIFIER OUTPUT CURRENT IN LINEAR REGION OF OPERATION 4 40 3 30 VEA − Output Current − µA Voltage Amplifier Output Current − mA VOLTAGE AMPLIFIER OUTPUT CURRENT CAPABILITY 2 1 0 −1 −2 −3 20 10 0 −10 −20 −30 −4 −40 7.0 7.2 7.6 7.4 7.8 7.0 8.0 VSENSE − Voltage Normalized to VREF − V 7.2 7.6 7.8 7.4 VSENSE − Voltage Normalized to VREF − V Figure 25 8.0 Figure 26 VOLTAGE AMPLIFIER VSENSE BIAS CURRENT vs TEMPERATURE VOLTAGE AMPLIFIER OPEN LOOP GAIN AND PHASE 300 180 VAOUT Load = 15 pF Gain − dB, Phase − Degree IIB − VEA VSENSE Bias Current − nA Phase 150 120 90 Gain 60 30 0 200 150 100 50 0 −30 10 26 250 103 105 107 −50 −25 0 25 50 Frequency − Hz Temperature − °C Figure 27 Figure 28 www.ti.com 75 100 125 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS VOLTAGE AMPLIFIER SLEW CURRENTS vs TEMPERATURE SOFTSTART CURRENTS vs TEMPERATURE 15 5 IDISCHG (mA) 3 ICHG − µA, IDISCHG −mA VEA ISOURCE, ISINK − mA 4 ISINK 2 1 0 −1 10 5 0 −5 −2 ICHARGE (µA) −3 ISOURCE −10 −4 −15 −5 −50 −25 0 25 50 75 100 125 Temperature − °C −50 −25 0 25 50 75 100 125 Temperature − °C Figure 29 Figure 30 TYPICAL MINIMUM ON TIME vs CAPACITANCE 60 Absolute Maximum Limit of Capacitance Allowed Duty Cycle − % 50 40 30 20 10 0 0 100 200 300 400 500 Capacitance − pF Figure 31 www.ti.com 27 

 SLUS608D − JANUARY 2005 REVISED NOVEMBER 2005 REFERENCES 1. Evaluation Module and associated User’s Guide, UCC28521EVM, Texas Instruments Literature Number SLUU218 2. Datasheet, UCC38500/1/2/3 BiCMOS PFC/PWM Combination Controller, Texas Instruments Literature Number SLUS419C 3. Power Supply Seminar SEM−600, High Power Factor Preregulator for Off-line Power Supplies, L.H. Dixon, Texas Instruments Literature Number SLUP087 4. Power Supply Seminar SEM−700, Optimizing the Design of a High Power Factor Switching Preregulator, L.H. Dixon, Texas Instruments Literature Number SLUP093 5. Power Supply Seminar SEM−1500 Topic 2, Designing High-Power Factor Off−Line Power Supplies, by James P. Noon 6. Application Note, UC3854 Controlled Power Factor Correction Circuit Design ,Texas Instruments Literature Number SLUA144 7. Design Note, Optimizing Performance in UC3854 Power Factor Correction, Texas Instruments Literature Number SLUA172 8. Design Note, UC3854A and UC3854B Advanced Power Factor Correction Control ICs, Texas Instruments Literature Number SLUA177 9. Design Note, UC3854A/B and UC3855A/B Provide Power Limiting with Sinusoidal Input Current for PFC Front Ends, Texas Instruments Literature Number SLUA196 10. Laszlo Balogh, A Design and Application Guide for High Speed Power MOSFET Gate Drive Circuits, 2001 Power Supply Design Seminar Manual SEM1400, 2001 11. Bob Mammano and Bruce Carsten, Understanding and Optimizing Electromagnetic Compatibility in Switchmode Power Supplies, 2002 Power Supply Design Seminar Manual SEM1500, 2002 RELATED PRODUCTS PART NUMBER DESCRIPTION COMMENTS UCC28510-17 Advanced BiCMOS PFC/PWM combination controllers 1:1 or 1:2 frequency option; leading edge, trailing edge modulation, programmable PWM Max dc UCC38500/1/2/3 BiCMOS PFC/PWM combination controller 1:1 leading edge, trailing edge modulation, 50% PWM Max dc UCC3817/18 BiCMOS power factor preregulator High PF, UC3854 compatible, leading edge trailing edge modulation UCC3819 Programmable output power factor preregulator Tracking boost topology for dynamic output voltage adjustments UC3854 High Power Factor Preregulator High PF, industry standard PFC controller; 35 VCC max UC3854A/B Enhanced high power factor preregulator Improved high PF, industry standard PFC controller; 22 VCC max UC3855A/B High performance power factor preregulator ZVT output for lower EMI emission & higher efficiencies UC3853 High power factor preregulator 8-Pin package; simplified architecture to minimized external components UCC38050 Transition mode PFC controller Constant on-time transition mode PFC controller UC3852 High power factor preregulator Constant off-time transition mode PFC controller; 30 VCC max REVISION HISTORY 28 REVISION DATE SLUS608B 6/27/05 CHANGE Corrected CAOUT pin description. www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) UCC28521DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UCC28521DW UCC28528DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 UCC28528DW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of