UCC2897PW

  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008   
        FEATURES D Ideal for Active Clamp/Reset Forward, D D D D D D D D D D DESCRIPTION The UCC2897 PWM controller simplifies implementation of the various active clamp/reset and synchronous rectifier switching power topologies. Flyback and Synchronous Rectifier Apps Provides Complementary Auxiliary Driver with Programmable Deadtime (Turn-On Delay) between AUX and MAIN Switches Peak Current-Mode Control with 0.5-V Cycle-by-Cycle Current Limiting Hiccup Mode 0.75-V Current Limit TrueDrivet 2-A Sink, 2-A Source Outputs 110-V Input Startup Device Trimmed Internal Bandgap Reference for Accurate Line UV and Line OV Threshold Programmable Slope Compensation High-Performance 1.0-MHz Synchronizable Oscillator with Internal Timing Capacitor Precise Programmable Maximum Duty Cycle PB-Free Lead Finish Package Based on the UCC2891 active-clamp controller the UCC2897 is a peak current-mode, fixedfrequency, high-performance pulse width modulator. It includes the logic and the drive capability for the P-channel auxiliary switch along with a simple method of programming the critical delays for proper active clamp operation. Features include an internal programmable slope compensation circuit, precise DMAX limit, and a synchronizable oscillator with an internal timing capacitor. An accurate line monitoring function also programs the converter’s ON and OFF transitions with regard to the bulk input voltage. The UCC2897 adds a second level hiccup mode current sense threshold, bi-directional synchronization and the input overvoltage protection functionalities that are not available on the 16-pin UCC2891. The UCC2897 is offered in 20-pin TSSOP (PW) and 20-pin QFN (RTJ) package. APPLICATIONS D High-Efficiency DC/DC Power Supplies D Server Power, 48-V Telecom, Datacom, and 42-V Automotive Applications TYPICAL APPLICATION DIAGRAM BIAS WINDING UCC2897 3 RDEL 4 RTON 5 RTOFF 6 VREF 7 VIN 1 LINEOV 19 LINEUV 18 VDD 17 PVDD 16 +VIN CBULK LOAD CCLAMP Q1 Q2 SYNC 15 8 GND OUT 9 CS AUX 14 10 RSLOPE PGND 13 12 SS/SD FB 11 SR DRIVE RCS SECONDARY SIDE E/A RF  
    !"   #!$% &"' &!   #" #" (" "  ") !" && *+' &! #", &"  ""%+ %!&" ",  %% #""' UDG−03186 Copyright  2006 − 2008, Texas Instruments Incorporated www.ti.com 1 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Line input voltage, VIN 120 Supply voltage range, VDD (IDD < 10 mA) FB, CS, SYNC Analog inputs Output source current (peak), IO_SOURCE Output sink current (peak), IO_SINK 15 V −0.3 to (VREF + 0.3) 2.5 OUT, AUX A −2.5 Operating junction temperature range, TJ −55 to 150 Storage temperature, Tstg −65 to 150 °C C Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds 300 (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of, the specified terminal. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VDD 8.5 Supply bypass capacitance NOM 12.0 MAX 14.5 UNIT V µF 1 Timing resistance, RON, ROFF (for 250-kHz operation) 75 Operating junction temperature, TJ −40 Reference bybass capacitance, CREF 0.1 kΩ 125 °C µF ORDERING INFORMATION PART NUMBERS{ TA APPLICATION AUX OUTPUT POLARITY CYCLE-BYCYCLE CS THRESHOLD HICCUP MODE CS THRESHOLD 110-V HV JFET START-UP CIRCUIT −40°C to 125°C DC/DC P-Channel 0.5 V 0.75 V Yes TSSOP−20 (PW)} QFN−20 (RTJ)} UCC2897PW UCC2897RTJ † The PW package is available taped and reeled. Add R suffix to device type (e.g. UCC2897PWR) to order quantities of 2,000 devices per reel. Bulk quantities are 70 units per tube. The RTJ package is available in two options of tape and reel. The RTJT is orderable in small reels of 250 (e.g. UCC2897RTJT); the RTJR contains 3000 pieces per reel (e.g. UCC2897RTJR). ‡ The TSSOP-20 (PW) and QFN−20 (RTJ) package uses Pb-free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature and compatible with either lead free or Sn/Pb soldering operations. 2 www.ti.com 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 PIN ASSIGNMENTS QFN PACKAGE (BOTTOM VIEW) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 N/C LINEOV LINEUV VDD PVDD OUT AUX PGND SS/SD FB 1 RDEL NC VIN NC LINEOV 2 3 4 5 20 6 19 7 18 8 17 9 16 10 15 14 13 12 11 CS RSLOPE FB SS/SD PGND LINEUV VDD PVDD OUT AUX VIN N/C RDEL RTON RTOFF VREF SYNC GND CS RSLOPE RTON RTOFF VREF SYNC GND PW PACKAGE (TOP VIEW) ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RT(on) = RT(off) = 75 kΩ, RDEL = 10 kΩ, RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERALL VDD Supply voltage range IDD Operating supply current(1)(2) 14.5 VFB = 0 V, VCS = 0 V, Outputs not switching 2 3 V mA HIGH-VOLTAGE BIAS SECTION VDD startup current Current available from VDD during startup 4 10 mA 12.2 12.7 13.2 Minimum operating voltage after start 7.6 8.0 8.4 Hysteresis 4.4 4.7 5.0 1.243 1.268 1.294 V 11.8 12.5 13.2 µA UNDERVOLTAGE LOCKOUT Start threshold voltage(1) V LINE MONITOR VLINEUV, OV ILINEHYS Line-on, Line-off voltage thresholds Line hysteresis SOFT-START ISS_CH Charge current IRT(on) = 2.5 V / RT(on) IRTON -30% IRTON IRTON +30% ISS_DSH Discharge current IRT(on) = 2.5 V / RT(on) IRTON -30% IRTON IRTON +30% 0.4 0.5 0.6 VSS/SD Discharge/shutdown threshold voltage (1) Set VDD above the start threshold before setting at 12 V. (2) Does not include current of the external oscillator network. www.ti.com A µA V 3 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RT(on) = RT(off) = 75 kΩ, RDEL = 10 kΩ, RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 4.85 5.00 5.15 4.75 5.00 5.25 −20 −11 -10% R CS R SLOPE +10% 237 250 263 UNIT VOLTAGE REFERENCE VREF Reference voltage TJ = 25°C 0 A < IREF < 5 mA, ISC Short circuit current INTERNAL SLOPE COMPENSATION REF = 0 V, m FB = High Slope over temperature TJ = 25°C V mA OSCILLATOR fOSC Oscillator frequency Total variation TJ = 25°C Line, Temperature 225 VP_P Oscillator amplitude (peak-to-peak) SYNCHRONIZATION 270 2 SYNC input high voltage V 1.6 50 SYNC pull down output current (3) SYNC pull up output current(3) SYNC output pulse width(3) tDEL PWM SYNC-to-output delay Maximum duty cycle 66% V ns 600 µA −600 µA 150 ns 50 ns 70% Minimum duty cycle PWM offset V 3.0 SYNC input low voltage SYNC input pulse width (4) kHz 74% 0% CS = 0 V 0.43 0.52 0.61 10 19 28 V OUTPUT (OUT AND AUX) tR tF Rise time CLOAD = 2 nF Fall time CLOAD = 2 nF tDEL tDEL Delay time (AUX to OUT) CLOAD = 2 nF, RDEL = 10 kΩ Delay time (OUT to AUX) CLOAD = 2 nF, RDEL = 10 kΩ IOUT(src) IOUT(sink) Output source current 14 23 110 130 ns 115 −2 Output sink current 2 VOUT(low) Low-level output voltage IOUT = 150 mA VOUT(high) High-level output voltage IOUT = −150 mA (1) Set VDD above the start threshold before setting at 12 V. (2) Does not include current of the external oscillator network. (3) This pulse is typically 150 ns. (4) Maximum pulse width needs to be less than DMAX, which is a function of RT(on) and RT(off). 4 5 90 www.ti.com A 0.4 0.9 V 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 CT DMAX OUT AUX (N-channel) tDEL tDEL UDG−03147 Figure 1. Output Timing Diagram ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RT(on) = RT(off) = 75 kΩ, RDEL = 10 kΩ, RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted) TEST CONDITIONS MIN TYP MAX PARAMETER UNIT CURRENT SENSE VLVL VERR(max) Current sense level shift voltage Maximum voltage error (clamped) Cycle-by-cycle VCS Current sense threshold VFB = 5 V Hiccup mode www.ti.com 0.45 0.50 4.8 5.0 0.55 5.2 0.43 0.48 0.53 0.71 0.76 0.81 V 5 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 FUNCTIONAL BLOCK DIAGRAM VIN 1 VREF N/C 2.5 V 2 0.05 y IRDEL IRDEL RDEL CLOCK 1.27 V 1−DMAX OUT IDSCHG VREF IRDEL VDD S Q R D Q 14 AUX 13 PGND + Turn−on Delay VREF 0.75 V 5 y ISLOPE 0.43 y ICHG 4yR 9 CT ISLOPE 6 OUT VREF IRDEL VREF RSLOPE 15 REF 0.5 V CS VDD 16 PVDD Turn−on Delay GEN 8 17 OUT SYNC GND LINEUV OFF 5 7 18 13 V/8 V PWM CT SYNC LINEOV VDD End 4 6 19 LineUV Start 2.5 V VREF N/C 1.27 V ICHG RTOFF 20 LineOV 3 2.5 V RTON 0.05 y IRDEL VREF 1−DMAX 12 SS/SD Restart VDD VREF LineUV LineOV R 10 UVLO & SS Enable 11 www.ti.com FB 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 TERMINAL FUNCTIONS TERMINAL NAME UCC2897 I/O DESCRIPTION AUX 14 O This output drives the auxiliary clamp P−channel MOSFET which is turned on when the main PWM switching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-A source turnon current and 2-A sink turn-off current. CS 9 I This pin is used to sense the peak current utilized for current mode control and for current limiting functions. The peak signal which can be applied to this pin before pulse-by-pulse current limiting activates is approximately 0.50 V for the UCC2897. FB 11 I This pin is used to bring the error signal from an external optocoupler or error amplifier into the PWM control circuitry. Often, there is a resistor tied from FB to VREF, and an optocoupler is used to pull the control pin closer to GND to reduce the pulse width of the OUT output driving the main power switch of the converter. GND 8 − This pin serves as the fundamental analog ground for the PWM control circuitry. This pin should be connected to PGND directly at the device. LINEOV 19 I Provides the LINE overvoltage function. LINEUV 18 I This pin provides a means to accurately enable/disable the power converter stage by monitoring the bulk input voltage or another parameter. When the circuit initially starts (or restarts from a disabled condition), a rising input on LINEUV enables the outputs when the threshold of 1.27 V is crossed. After the circuit is enabled, then a falling LINEUV signal disables the outputs when the same threshold is reached. The hysteresis between the two levels is programmed using an internal current source. OUT 15 O This output pin drives the main PWM switching element MOSFET in an active clamp controller. It can directly drive an N-channel device with 2-A source turn-on current and 2-A sink turn-off current. PGND 13 − The PGND should serve as the current return for the high-current output drivers OUT and AUX. Ideally, the current path from the outputs to the switching devices, and back would be as short as possible, and enclose a minimal loop area. PVDD 16 I This is the supply pin for the power devices in the IC. It is separated internally from the VDD pin. RSLOPE 10 I A resistor connected from this pin to GND programs an internal current source that sets the slope compensation ramp for the current mode control circuitry. RTDEL 3 I A resistor from this pin to GND programs the turn-on delay of the two gate drive outputs to accommodate the resonant transitions of the active clamp power converter. RTOFF 5 I A resistor connected from this pin to GND programs an internal current source that discharges the internal timing capacitor. RTON 4 I A resistor connected from this pin to GND programs an internal current source that charges the internal timing capacitor. SS/SD 12 I A capacitor from SS/SD to ground is charged by an internal current source of IRTON to program the soft-start interval for the controller. During a fault condition this capacitor is discharged by a current source equal to IRTON. SYNC 7 I The SYNC pin serves as a bidirectional synchronization input/output for the internal oscillator. The synchronization function is implemented such that the user programmable maximum duty cycle (set by RTON and RTOFF) remains accurate during synchronized operation. VDD 17 I This is the power supply for the device. There should be a minimum 0.1-µF capacitor directly from VDD to PGND. VIN 1 I This pin is connected to the input power rail directly. Inside the device, a high-voltage start-up device is utilized to provide the start-up current for the controller until a bootstrap type bias rail becomes available. VREF 6 O This is the 5-V reference voltage that can be utilized for an external load of up to 5 mA. Since this reference provides the supply rail for internal logic, it should be bypassed to AGND as close as possible to the device. www.ti.com 7 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 DETAILED PIN DESCRIPTIONS VIN (pin 1) The UCC2897 controller are equipped with a high voltage, P-channel JFET start up device to initiate operation from the input power source of the converter in applications where the input voltage does not exceed the 110-V maximum rating of the start up transistor. In these applications, the VIN pin can be connected directly to the positive terminal of the input power source. The internal JFET start up transistor provides approximately 15-mA charge current for the energy storage capacitor (CBIAS) connected across the VDD (pin 14) and PGND (pin 11) terminals. Note that the start up device is turned off immediately when the voltage on the VDD pin exceeds approximately 13.5 V, the controller’s undervoltage lockout threshold for turn-on. The JFET is also disabled at all times when the high-current gate drivers are switching to protect against excessive power dissipation and current through the device. For more information on biasing the UCC2897, refer to the Setup Guide and Additional Application Sections of this datasheet. RDEL (pin 3) This pin is internally connected to an approximately 2.5-V DC source. A resistor (RDEL) to GND (pin 6) sets the turn-on delay for both gate drive signals of the UCC2987 controller. The delay time is identical for both switching transitions, between OUT (pin 13) is turning off and AUX (pin 14) is turning on as well as when AUX (pin 14) is turning off and OUT (pin 13) is turning on. The delay time is defined as: t DEL + R DEL 1.1 10 *11 (1) For proper selection of the delay time refer to the various references describing the design of active clamp power converters. RTON (pin 4) This pin is internally connected to an approximately 2.5-V DC source. A resistor (RON) to GND (pin 6) sets the charge current of the internal timing capacitor. The RTON pin, in conjunction with the RTOFF pin (pin 3) are used to set the operating frequency and maximum operating duty cycle of the UCC2897. RTOFF (pin 5) This pin is internally connected to an approximately 2.5-V DC source. A resistor (ROFF) to GND (pin 6) sets the discharge current of the internal timing capacitor. The RTON and RTOFF pins are used to set the switching period (TSW) and maximum operating duty cycle (DMAX) according to the following equations: t ON + 37.33 t OFF + 16 10 *12 10 *12 R ON (2) R OFF (3) T SW + t ON ) t OFF D MAX + 8 (4) t ON T SW (5) www.ti.com 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 DETAILED PIN DESCRIPTIONS (continued) VREF (pin 6) The controller’s internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a good quality ceramic bypass capacitor (CVREF) to GND (pin 6) for noise filtering and to provide compensation to the regulator circuitry. The recommended CVREF value is 0.22-µF. The minimum bypass capacitor value is 0.022-µF limited by stability considerations of the bias regulator, while the maximum is approximately 22-µF. The VREF pin is internally current limited and can supply approximately 5-mA to external circuits. The 5-V bias is only available when the undervoltage lock out (UVLO) circuit enables the operation of UCC2897 controller. For the detailed functional description of the undervoltage lock out (UVLO) circuit refer to the Functional Description section of this datasheet. SYNC (pin 7) This pin is a bi-directioanl synchonization terminal. This pin provides an input for an external clock signal which can be used to synchronize the internal oscillator of the UCC2897 controller. The synchronizing frequency must be higher than the free running frequency of the onboard oscillator ǒT SYNC t T SWǓ. The acceptable minimum pulse width of the synchronization signal is approximately 50 ns (positive logic), and it should remain shorter than ǒ1 * D MAXǓ T SYNC where DMAX is set by RON and ROFF. If the pulse width of the synchronization signal stays within these limits, the maximum operating duty ratio remains valid as defined by the ratio of RON and ROFF, and DMAX is the same in free running and in synchronized modes of operation. If the pulse width of the synchronization signal would exceed the ǒ1 * DMAXǓ T SYNC limit, the maximum operating duty cycle is defined by the synchronization pulse width. In the stand-alone mode, the SYNC pin is driven by the internal oscillator which provides output pulses of approximately 100-ns wide 5-V amplitude square wave. This signal can be use to synchronize other PWM controllers or circuits needing a constant frequency time base. For more information on synchronization of the UCC2897 refer to the Functional Description section of this datasheet. GND (pin 8) This pin provides a reference potential for all small signal control and programming circuitry inside the UCC2897. Ground layout is critical for correct operation. High current surges from the MOSFET drivers conduct through PVDD, OUT, AUX, and PGND. TO localize these surges, PVDD must be bypassed directly to PGND. PGND current must be electrically, capacitively, and inductively isolated from GND with only one short trace connecting PGND to GND, located to best minimize noise into GND. www.ti.com 9 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 DETAILED PIN DESCRIPTIONS (continued) CS (pin 9) This is a direct input to the PWM and current limit comparators of the UCC2897 controller. The CS pin should never be connected directly across the current sense resistor (RCS) of the power converter. A small, customary R−C filter between the current sense resistor and the CS pin is necessary to accommodate the proper operation of the onboard slope compensation circuit and in order to protect the internal discharge transistor connected to the CS pin (RF, CF). Slope compensation is achieved across RF by a linearly increasing current flowing out of the CS pin. The slope compensation current is only present during the on-time of the gate drive signal of the main power switch (OUT) of the converter. The internal pull-down transistor of the CS pin is activated during the discharge time of the timing capacitor. This time interval is ǒ1 * D MAXǓ T SW long and represents the ensured off time of the main power switch. The UCC2897 has a two level over-current protection. There are two different thresholds for cycle by cycle and hiccup mode current limit operation. The UCC2897 will operate continuously in cycle-by-cycle current limit mode with a 0.5-V maximum current sense voltage. In case the magnetic components would saturate and the current level increases by an additional 50% (0.75-V threshold), a hiccup cycle is initiated. The hiccup cycle consists of a wait period with no switching action while the soft-start capacitor is slowly discharged to 0.5 V followed by a normal soft start sequence. RSLOPE (pin 10) A resistor (RSLOPE) connected between this pin and GND (pin 6) sets the amplitude of the slope compensation current. During the on time of the main gate drive output (OUT) the voltage across RSLOPE is a representation of the internal timing capacitor waveform. As the timing capacitor is being charged, the voltage across RSLOPE also increases, generating a linearly increasing current waveform. The current provided at the CS pin for slope compensation is proportional to this current flowing through RSLOPE. Due to the high speed, AC voltage waveform present at the RSLOPE pin, the parasitic capacitance and inductance of the external circuit components connected to the RSLOPE pin should be carefully minimized. For more information on how to program the internal slope compensation refer to the Setup Guide section of this datasheet. FB (pin 11) This pin is an input for the control voltage of the pulse width modulator of the UCC2897. The control voltage is generated by an external error amplifier by comparing the converters output voltage to a voltage reference and employing the compensation for the voltage regulation loop. Usually, the error amplifier is located on the secondary side of the isolated power converter and its output voltage is sent across the isolation boundary by an opto coupler. Thus, the FB pin is usually driven by the opto coupler. An external pull-up resistor to the VREF pin (pin 4) is also needed for proper operation as part of the feedback circuitry. The control voltage is internally buffered and connected to the PWM comparator through a voltage divider to make it compatible to the signal level of the current sense circuit. The useful voltage range of the FB pin is between approximately 2.5 V and 4.5 V. Control voltages below the 2.5-V threshold result in zero duty cycle. 10 www.ti.com 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 DETAILED PIN DESCRIPTIONS (continued) SS/SD (pin 12) A capacitor (CSS) connected between this pin and GND (pin 6) programs the soft start time of the power converter. The soft-start capacitor is charged by a precise, internal DC current source which is programmed by the RON resistor connected to pin 2. The soft-start current is defined as: I SS + 2.5 V R ON 0.43 (6) This DC current charges CSS from 0 V to approximately 5 V. Internal to the UCC2897 controller, the soft start capacitor voltage is buffered and ORed with the control voltage present at the FB pin (pin 9). The lower of the two voltages manipulates the controller’s PWM engine through the voltage divider described with regards to the FB pin. Accordingly, the useful control range on the SS pin is similar to the control range of the FB pin and it is between 2.5 V and 4.5 V approximately. PGND (pin 13) This pin serves as a dedicated connection to all high-current circuits inside the UCC2897. The high-current portion of the controller consists of the two high-current gate drivers, and the various bias connections except VREF (pin 4). While the PGND (pin 11) and GND (pin 6) pins are connected internally, a low-impedance, external connection between the two ground pins is also required. It is recommended to form a separate ground plane for the low current setup components (RDEL, RON, ROFF, CVREF, CF, RSLOPE, CSS and the emitter of the opto-coupler in the feedback circuit). This separate ground plane (GND) should have a single connection to the rest of the ground of the power converter (PGND) and this connection should be between pin 6 and pin 11 of the controller. AUX (pin 14) This is a high-current gate drive output for the auxiliary switch to implement the active clamp operation for the power stage. The auxiliary output (AUX) of the UCC2897 drives a P-channel device as the clamp switch therefore it requires an active low operation (the switch is ON when the output is low). OUT (pin 15) This high-current output drives an external N-channel MOSFET. Each controller in the UCC2897 uses active high drive signals for the main switch of the converter. Due to the high speed and high-drive current capability of these outputs (AUX, OUT) the parasitic inductance of the external circuit components connected to these pins should be carefully minimized. A potential way of avoiding unnecessary parasitic inductances in the gate drive circuit is to place the controller in close proximity to the MOSFETs and by ensuring that the outputs (AUX, OUT) and the gates of the MOSFET devices are connected by wide, overlapping traces. PVDD (pin 16) The PVDD pin in the supply rail for the output power devices of the IC. It is completely separated internally by the VDD pin. www.ti.com 11 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 DETAILED PIN DESCRIPTIONS (continued) VDD (pin 17) The VDD rail is the primary bias for the internal, high-current gate drivers, the internal 5-V bias regulator and for parts of the undervoltage lockout circuit. To reduce switching noise on the bias rail, a good quality ceramic capacitor (CHF) must be placed very closely between the VDD pin and PGND (pin 11) to provide adequate filtering. The recommended CHF value is 1-µF for most applications but its value might be affected by the properties of the external MOSFET transistors used in the power stage. In addition to the low-impedance, high-frequency filtering, the controller’s bias rail requires a larger value energy storage capacitor (CBIAS) connected parallel to CHF. The energy storage capacitor must provide the hold up time to operate the UCC2897 (including gate drive power requirements) during start up. In steady state operation the controller must be powered from a bootstrap winding off the power transformer or by an auxiliary bias supply. In case of an independent auxiliary bias supply, the energy storage is provided by the output capacitance of the bias supply. LINEUV (pin 18) This input monitors the incoming power source to provide an accurate undervoltage lockout function with user programmable hysteresis for the power supply controlled by the UCC2897. The unique property of the UCC2897 is to use only one pin to implement these functions without sacrificing on performance. The input voltage of the power supply is scaled to the precise 1.27-V threshold of the undervoltage lockout comparator by an external resistor divider (RIN1, RIN2). Once the line monitor’s input threshold is exceeded, an internal current source gets connected to the LINEUV pin. The current generator is programmed by the RDEL resistor connected to pin 1 of the controller. The actual current level is given as: I HYST + 2.5 V R DEL 0.05 (7) As this current flows through RIN2 of the input divider, the undervoltage lockout hysteresis is a function of IHYST and RIN2 allowing accurate programming of the hysteresis of the line monitoring circuit. For more information on how to program the line monitoring function refer to the Setup Guide of this datasheet. LINEOV (pin 19) In the UCC2897 controller the high-voltage start-up device is not utilized thus pin 16 is used for a different function. This input monitors the incoming power source to provide an accurate overvoltage protection with user programmable hysteresis for the power supply controlled by the controller. The circuit implementation of the overvoltage protection function is identical to the technique used for monitoring the input power rail for undervoltage lockout. This allows implementing an accurate threshold and hysteresis using only one pin. The input voltage of the power supply is scaled to the precise 1.27-V threshold of the overvoltage protection comparator by an external resistor divider (RIN3, RIN4). Once the line monitor’s input threshold is exceeded, an internal current source gets connected to the LINEOV pin. The current generator is programmed by the RDEL resistor connected to pin 1 of the controller. The actual current level is given as: I HYST + 2.5 V R DEL 0.05 (8) As this current flows through RIN4 of the input divider, the overvoltage protection hysteresis is a function of IHYST and RIN4 allowing accurate programming of the hysteresis of the line monitoring circuit. For more information on how to program the overvoltage protection, refer to the Setup Guide of this datasheet. 12 www.ti.com 
  SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008 FUNCTIONAL DESCRIPTION JFET Control and UVLO The UCC2897 controller includes the 110-V high voltage JFET start up transistor. The steady state power consumption of the of the control circuit which also includes the gate drive power loss of the two power switches of an active clamp converter exceeds the current and thermal capabilities of the device. Thus the JFET should only be used for initial start up of the control circuitry and to provide keep-alive power during stand-by mode when the gate drive outputs are not switching. Accordingly, the start-up device is managed by its own control algorithm implemented on board the UCC2897. The following timing diagram illustrates the operation of the JFET start up device. VON VIN Bootstrap bias VDD OFF JFET OFF OFF Enable Command SS/SD OUTPUTs OFF OFF OFF SWITCHING SWITCHING UDG−03148 Figure 2. JFET Control Startup and Shutdown During initial power up the JFET is on and charges the CBIAS and CHF capacitors connected to the VDD pin (pin 14). The VDD pin is monitored by the controller’s undervoltage lockout circuit to ensure proper biasing before the operation is enabled. When the VDD voltage reaches approximately 13.5 V (UVLO turn-on threshold) the UVLO circuit enables the rest of the controller. At that time, the JFET is turned off and 5 V appears on the VREF terminal (pin 4). Switching waveforms might not appear at the gate drive outputs unless all other conditions of proper operation are met. These conditions are: D D D D sufficient voltage on the VREF pin (VVREF > 4.5V) the voltage on the CS pin is below the current limit threshold the control voltage is above the zero duty cycle boundary (VFB > 1.25 V) the input voltage is in the valid operating range (VVON