UCC2917DTRG4

Obsolete Devices UCC2917 UCC3917 www.ti.com SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 Positive Floating Hot-Swap Power Manager Check for Samples: UCC2917, UCC3917 FEATURES DESCRIPTION • • • • • • • The UCCx917 family of positive-floating hot-swap managers provides complete power management, hot-swap, and fault handling capability. The voltage limitation of the application is only restricted by the external component voltage limitations. The device provides its own supply voltage via a charge pump referenced to VOUT. The onboard 10-V shunt regulator protects the device from excess voltage. The devices also have catastrophic fault indication to alert the user that the ability to shut off the output Nchannel MOSFET has been bypassed. All control and housekeeping functions are integrated and externally programmable. These include the fault current level, maximum output sourcing current, maximum fault time, soft-start time, and average N-channel MOSFET power limiting. 1 • • • • Manages Hot-Swap of 15 V and Above Precision Fault Threshold Programmable Average Power Limiting Programmable Linear Current Control Programmable Overcurrent Limit Programmable Fault Time Internal Charge Pump to Control External Nchannel MOSFET Device Fault Output and Catastrophic Fault Indication Fault Mode Programmable to Latch or Retry Shutdown Control Undervoltage Lockout APPLICATIONS • • 390-V DC Distribution General High-Voltage Power Management The fault level across the current-sense amplifier is fixed at 50 mV to minimize total drop out. Once 50 mV is exceeded across the current-sense resistor, the fault timer starts. The maximum allowable sourcing current is programmed with a voltage divider from the VREF/CATFLT pin to generate a fixed voltage on the MAXI pin. The current level at which the output appears as a current source is equal to VMAXI divided by the current-sense resistor. If desired, a controlled current startup can be programmed with a capacitor on MAXI. When the output current is below the fault level, the output device is switched on with full gate drive. When the output current exceeds the fault level, but is less than maximum allowable sourcing level programmed by MAXI, the output remains switched on, and the fault timer starts charging the timing capacitor CT. Once CT charges to 2.5 V, the output device is turned off and attempts either a retry sometime later or waits for the state on the LATCH pin to change if in latch mode. When the output current reaches the maximum sourcing current level, the output device appears as a current source. ORDERING INFORMATION TJ PACKAGED DEVICES DIP (J) DIP (N) SOIC (D) –40°C to 85°C UCC2917J UCC2917N UCC2917D 0°C to 70°C UCC3917J UCC3917N UCC3917D 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated Obsolete Devices UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE MIN Output Current Supply (2) SHTDWN, LATCH, VREF (2) UNIT MAX 20 mA –500 µA mA Line Current PLIM 10 Input voltage MAXI VDD + 0.3 V Junction temperature, TJ –55 150 °C Storage temperature, Tstg –65 150 °C 300 °C Lead temperature (Soldering, 10 sec.) (1) (2) 2 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.colsep Currents are positive into, negative out of the specified terminal. Consult the Packaging section of the Interface Products Data Book (TI Literature Number SLUD002) for thermal limitations and considerations of package. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Obsolete Devices www.ti.com UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS 0°C ≤ TA ≤ 70°C for the UCC3917, –40°C to 85°C for the UCC2917, CCT = 4.7 nF, TA = TJ, all voltages are with respect to VOUT, current is positive into and negative out of the specified terminal, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY Supply current (1) IDD 4.0 5 11 mA UVLO turn on threshold From VOUT 7.9 8.8 9.7 V UVLO off voltage 5.5 6.5 7.5 V VSS regulator voltage –6 –5 –4 V 47.5 50 53 mV 46 50 54 mV 50 500 –78 –50 –28 µA 4.5 V FAULT TIMING TA = 25°C Overcurrent threshold Over operating temperature Overcurrent input bias CT charge current bias VCT = 1 V CT catastrophic fault threshold D 3.4 CT fault threshold 2.25 2.5 2.75 V CT reset threshold 0.32 0.5 0.62 V 1.7% 2.7% 3.7% IOUT = 0 6 8 10 IOUT = –100 µA 5 7 9 0.03 0.50 0.6 0.9 Output duty cycle Fault condition OUTPUT VOH High-level output voltage VOL Output low voltage IOUT = 500 µA IOUT = 1 mA V V LINEAR CURRENT Sense control voltage IBIAS Input bias current VMAXI = 100 mV 85 100 115 mV VMAXI = 400 mV 370 400 430 mV 50 500 nA 2.4 2.8 V VMAXI = 200 mV SHUTDOWN Shutdown threshold 2.0 Input current VSHTDWN = 0 V 24 40 60 µA 100 500 ns 1.7 2 2.3 V 24 40 60 µA Shutdown delay LATCH VLATCH Latch threshold Input current VLATCH = 0 V Fault output high VCT = 0 V, ISOURCE = 0 µA Fault output low VCT = 5 V, ISINK = 200 µA FLTOUT 6 8 10 V 0.01 0.05 V 5. 5.5 V POWER LIMITING VSENSE regulator voltage IPLIM = 64 µA Duty cycle control 4.5 IPLIM = 64 µA 0.6% 1.2% 1.7% IPLIM = 1 mA 0.045% 0.1% 0.2% VREF/CATFLT VREF regulator voltage ISINK (1) 4.5 Fault output low IVREF/CATFLT = 5 mA Output sink current VCT = 5 V, VVREF/CATFLT = 5 V Overload comparator threshold Relative to MAXI 5. 5.5 V 0.22 0.50 V 15 40 70 mA 110 200 290 mV Set by user using the RSS resistor. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Submit Documentation Feedback 3 Obsolete Devices UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 www.ti.com D PACKAGE 16 PINS (TOP VIEW) J, N PACKAGE 16 PINS (TOP VIEW) PLIM 1 16 LATCH SENSE 2 15 VREF/CATFLT OUTPUT 3 14 MAXI VOUT 4 13 VDD C2N 5 12 SHTDWN C2P 6 11 FLTOUT C1N 7 10 CT C1P 8 9 PLIM 1 16 SENSE 2 15 VREF/ CATFLT OUTPUT 3 14 MAXI VOUT 4 13 VDD C2N 5 12 SHTDWN C2P 6 11 FLTOUT C1N 7 10 CT C1P 8 9 VSS LATCH VSS DEVICE INFORMATION PIN DESCRIPTIONS PIN NAME NO. I/O DESCRIPTION C1N 7 I Negative side of the upper charge-pump capacitor. C1P 8 I Positive side of the upper charge-pump capacitor. C2N 5 I Negative side of the lower charge-pump capacitor. C2P 6 I Positive side of lower charge-pump capacitor. CT 10 I A capacitor is connected to this pin to set the fault time. The fault time must be more than the time to charge the external load capacitance (see application information). FLTOUT 11 O Provides fault output indication. Interface to this pin is usually performed through level-shift transistors. Under a non-fault condition, FLTOUT is pulled to a high state. When a fault is detected by the fault timer or the undervoltage lockout, this pin is driven to a low state, indicating the output N-channel MOSFET is in the off state. LATCH 16 I Pulling this pin low causes a fault to latch until this pin is brought high or a power-on reset is attempted. However, pulling this pin high before the reset time is reached does not clear the fault until the reset time is reached. Keeping LATCH high results in normal operation of the fault timer. Users should note there is an R-C delay dependent upon the external capacitor at this pin. MAXI 14 I Programs the maximum-allowable sourcing current. Since VREF/CATFLT is a regulated voltage, a voltage divider can be derived to generate the program level for MAXI. The current level at which the output appears as a current source is equal to the voltage on MAXI divided by the current-sense resistor. If desired, a controlled current start-up can be programmed with a capacitor on MAXI (to VOUT), and a programmed start delay can be achieved by driving the shutdown with an open collector/drain device into an RC network. OUTPUT 3 O Gate drive to the N-channel MOSFET pass element. PLIM 1 I This feature ensures that the average external N-channel MOSFET power dissipation is controlled. A resistor is connected from this pin to the drain of the external N-channel MOSFET pass element. When the voltage across the N-channel MOSFET exceeds 5 V, current flows into PLIM, which adds to the fault timer charge current, reducing the duty cycle from the 3% level. SENSE 2 I Input voltage from the current-sense resistor. When there is greater than 50 mV across this pin with respect to VOUT, a fault is sensed, and the CCT capacitor starts to charge. SHTDWN 12 I This pin provides shutdown control. Interface to this pin is usually performed through level-shift transistors. When shutdown is driven low, the output disables the N-channel MOSFET pass device. VOUT 4 I Ground reference for the device. 4 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Obsolete Devices UCC2917 UCC3917 www.ti.com SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 PIN DESCRIPTIONS (continued) PIN NAME NO. VDD I/O DESCRIPTION I Power to the device is supplied by an external current-limiting resistor on initial power up or if the load is shorted. As the load voltages rises (VOUT), a small amount of power is drawn from VOUT by an internal charge pump. The charge pump's input voltage is regulated by an on-device 5-V zener. Power to VDD is supplied by the charge pump under normal operation (i.e., external FET is on). 13 VREF/CATFLT 15 O This pin primarily provides an output reference for the programming of MAXI. Secondarily, it provides catastrophic fault indication. In a catastrophic fault, when the device unsuccessfully attempts to shutdown the N-channel MOSFET pass device, this pin pulls to a low state when CT charges above the catastrophic fault threshold. A possible application for this pin is to trigger the shutdown of an auxiliary FET in series with the main FET for redundancy. VSS 9 I Negative reference out of the device. This pin is normally current fed via a resistor to load ground. FUNCTIONAL BLOCK DIAGRAM VDD LATCH 13 16 VDD UVLO >10 V = Enable < 6 V = Disable 40 mA – VDD 5V 40 mA SHTDWN 12 3 OUTPUT 2 SENSE 4 VOUT + Disable – VOUT PLIM VDD + VOUT 1 VOUT Output Low FLTOUT 11 C1P 5V Reference 8 50 mV 10 V C2P 7 6 10 CT – + 5 + + 5V C2N On-Time Delay Logic Supply + C1N + OC – + – 4V 200 mV 9 15 14 VSS VREF/CATFLT MAXI UDG-99055 Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Submit Documentation Feedback 5 Obsolete Devices UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 www.ti.com APPLICATION INFORMATION FAULT TIMING Figure 1 shows the detailed circuitry for the fault timing function of the UCC3917. For simplicity, first consider a typical fault mode where the overload comparator and the current source I3 do not come into play. A typical fault occurs once the voltage across the current-sense resistor, RS, exceeds 50 mV. This causes the overcurrent comparator to trip and the timing capacitor to charge with current source I1 plus the current from the power limiting amplifier, or PLIM amplifier. The PLIM amplifier is designed to only source current into the CT pin once the voltage across the output FET exceeds 5 V. The current IPL is related to the voltage across the FET as shown in Equation 1. IPL = (VIN - VVOUT ) RPL (1) VIN RPLPLIM 1 + + – + MAXI I3 50 mA IPL VOUT 2 SENSE 5V OUTPUT SENSE 0.2 V Overload PLIM Ampllifier + – + 50 mV + OC – I3 1 mA Fault H = Close H = Close 2.5 V – + Fault Latch RSENSE VOUT I2 1.5 mA 4 0.5 V To Load – + S Q R Q OUTPUT Drive H = Off Reset 10 UGD-00073 CT CCT VOUT Figure 1. Fault Timing Circuitry for the UCC3917, Including Power Limit and Overload NOTE Under normal fault conditions where the output current is slightly above the fault level, VVOUT ≅ VIN, IPL = 0, and the CCT charging current is I1. During a fault, CCT charges at a rate determined by the internal charging current and the external timing capacitor, CT. Once CCT charges to 2.5 V, the fault comparator switches and sets the fault latch. Setting the fault latch causes both the output to switch off and the charging switch to open. CT must now discharge with current source I2 until 0.5 V is reached. Once the voltage at CCT reaches 0.5 V, the fault latch resets (assuming LATCH is high, otherwise the fault latch does not reset until the LATCH pin is brought high or a power-on reset occurs). This re-enables the output and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the overcurrent comparator closes the charging switch causing the cycle to repeat. 6 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Obsolete Devices www.ti.com UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 Under a constant fault the duty cycle is shown in Equation 2. I2 1.5 mA = D= IPL - I1 IPL + 50 mA where • IPL is 0 µA under normal operations (see Figure 2) (2) However, during large transients average power dissipations can be limited using the PLIM pin. The average dissipation in the pass element is shown in Equation 3. 1.5 mA PFET(avg) = (VIN - VVOUT )´ IMAXI ´ D = (VIN - VVOUT )´ IMAXI ´ IPL + 50 mA where • both Equation 4 and Equation 5 are true (3) VIN - VOUT >> 5 V IPL = (4) (VIN - VVOUT ) RPL (5) Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Submit Documentation Feedback 7 Obsolete Devices UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 www.ti.com IOUT IMAXI IFAULT IOUT(nom) VCT 2.5 V Timing capacitor (CCT) voltage (w/r/t VOUT) 0.5 V 0V VOUT VIN VOUT (w/r/t GND) 0V t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 UDG-99147 Figure 2. Typical Timing Diagram Table 1. Timing Stages TIME 8 CONDITION DESCRIPTION t0 Safe condition Output current is nominal, output voltage is at the positive rail, VIN t1 Fault control reached Output current rises above the programmed fault value, CT begins to charge with approximately 50 µA t2 Maximum current reached Ooutput current reaches the programmed maximum level and becomes a constant current with value IMAX. t3 Fault occurs CCT has charged to 2.5 V, fault output goes low, the FET turns off allowing no output current to flow, VOUT discharges to ground t4 Retry CT has discharged to 0.5 V, but fault current is still exceeded, CT begins charging again, FET is on, VVOUT rises to VIN. t5 t5 = t3 This Illustrates 3% duty cycle. t6 t6 = t4 t7 Output short circuit if VOUT is short circuited to ground, CT charges at a higher rate depending upon the values for VIN and RPL. t8 Fault occurs Output is still short circuited, but the occurrence of a fault turns the FET off so no current is conducted. t9 Fault remains Output short circuit released, still in fault mode. t10 t10 = t0 Fault released, safe condition – return to normal operation of the circuit breaker. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Obsolete Devices www.ti.com UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 Note that t6 – t5 ≅ 36 × (t5 – t4). and where IPL >> 50 µA, the duty cycle can be approximated in Equation 6. 1.5 mA ´ RPL D= (VIN - VVOUT ) (6) Therefore the average power dissipation in the MOSFET can be approximated by Equation 7. 1.5 mA ´ RPL PFET(avg) = (VIN - VVOUT )´ IMAXI ´ =I ´ 1.5 mA ´ RPL (VIN - VVOUT ) MAXI (7) Notice that since (VIN – VVOUT) cancels, average power dissipation is limited in the N-channel MOSFET pass element (see Figure 3). Also, a value for RPL can be approximated by using Equation 8. PFET(avg) RPL = IMAX ´ 1.5 mA (8) 25 RPL = ∞ RPL = 10 MΩ RPL = 5 MΩ RPL = 2 MΩ RPL = 1 MΩ RPL = 500 kΩ RPL = 200 kΩ 22.5 Average Power (W) 20 17.5 15 12.5 10 7.5 5 2.5 0 0 30 60 90 120 150 180 MOSFET Voltage (Output Shorted) (V) 210 G000 Figure 3. OVERLOAD COMPARATOR The overload comparator provides protection against a shorted load during normal operation when the external N-channel FET is fully enhanced. Once the FET is fully enhanced the linear current amplifier essentially saturates and the system is in effect operating open loop. Once the FET is fully enhanced the linear current amplifier requires a finite amount of time to respond to a shorted output possibly destroying the external FET. The overload comparator is provided to quickly shutdown the external MOSFET in the case of a shorted output (if the FET is fully enhanced). During an output short, CT is charged by I3 at ≈ 1 mA. The current threshold for the overload comparator is a function of IMAX and a fixed offset and is defined as: 200mV IOVERLOAD = IMAX ´ RS (9) WHen the overcurrent comparator trips, the UCC3917 enters a programmed fault mode (hiccup or latched). It should be noted that on subsequent retries during hiccup mode or if a short should occur when the UCC3917 is actively limiting the current, the output current does not exceed IMAX. In the event that the external FET does not respond during a fault the UCC3917 sets the VREF/CATFLT pin low to indicate a catastrophic failure. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Submit Documentation Feedback 9 Obsolete Devices UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 www.ti.com SELECTING THE MINIMUM TIMING CAPACITANCE To ensure that the device starts up correctly the designer must ensure that the fault time programmed by CT exceeds the startup time of the load. The startup time (tSTART) is a function of several components; load resistance and load capacitance, soft-start components R1, R2 and CSS, the power limit current contribution determined by RPL, and CIN. Use Equation 10 to calculate the start time using a parallel capacitor-constant current load. C ´ VIN tSTART = LOAD (IMAX - ILOAD ) (10) Use Equation 11 to calculate calculate the start time using a parallel R-C load. æ ö VIN tSTART = RLOAD ´ CLOAD ´ ln ´ ç 1 ÷ è IMAX ´ RLOAD ø (11) If the power limit function is not be used, then CCT(min) can be found using Equation 12. I ´t CT(min ) = CH START dVCT where • dVCT is the hysteresis on the fault detection circuitry (12) During operation in the latched fault mode configuration dVCT = 2.5 V. When the UCC3917 is configured for the hiccup or retry mode of fault operation dVCT = 2.0 V. If the power limit function is used, the CCT charging current becomes a function of ICH + IPL. CCT(min) is found by integrating Equation 13 with respect to VCT. æ æ öù ö é -t ç ÷ú ÷ ç ê R C ´ VIN - (IMAX ´ RLOAD )´ ê1 - eè LOAD LOAD ø ú ÷ ç ç ê ú÷ ç ë û ÷ ´ dt CT(min ) = ç ICH + ÷ dV RPL CT ç ÷ ç ÷ ç ÷ ç ÷ è ø (13) The minimum timing capacitance is calculated in Equation 14. 1 CT(min ) = ´ é (ICH ´ RPL ) + VIN - (IMAX ´ RLOAD ) ´ tSTART + VIN ´ RLOAD ´ CLOAD ù û RPL ´ dVCT ë ( 10 Submit Documentation Feedback ) (14) Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Obsolete Devices UCC2917 UCC3917 www.ti.com SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 SELECTING OTHER EXTERNAL COMPONENTS Other external components are necessary for correct operation of the device. Referring to Figure 13, resistors RSENSE, RSS, RDD, R17, R18, and R19 and Equation 15 theough Equation 17 apply: 50mV RSENSE = IFAULT (15) æ (VIN - 5 V ) ö RSS = ç ÷ ç ÷ IDD è ø (16) æ (VIN - 10 V ) ö RDD = ç ÷ ç ÷ IDD è ø (17) (R17 + R18 + R19) > 20 kΩ (current limit out of VREF) Use a value of 0.1 µF for the external charge pump capacitors. SOFT-START OPERATION The soft-start circuits in Figure 4, and Figure 5 gradually ramp up the load current on power-up, retry, or if the SHTDWN pin is pulled high. Control circuitry (not shown) turns on Q1 to discharge C1 when FLTOUT or SHTDWN are low (i.e., external power MOSFET is off) so the load current always ramps from zero. The circuit in Figure 4 uses an inexpensive bipolar transistor for Q1 so the component cost is lower than the circuit in Figure 5. R3 R2 R2 VREF 15 VREF 15 + C1 MAXI 14 Q1 R1 VOUT + C1 MAXI 14 Q1 R1 4 VOUT UDG-00017 Figure 4. Soft-Start Circuit Using A Higher-Cost BiPolar Transistor 4 UDG-11278 Figure 5. Soft-Start Circuit Using A Lower-Cost MOSFET Soft-start operation minimizes the voltage disturbance on the power bus when a circuit card is inserted into a live back plane. This disturbance could reset a system, which is not desirable when high availability is required. A server is an example of a high availability system. Soft-start operation is initiated with the SHTDWN pin in as shown in Figure 6. The anode of D2 is grounded when the card is in the back plane. R2 limits the SHTDWN pin current to between 60 µA and 500 µA (i.e., 60 µA < 0.65 V / R2 < 500 µA). Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Submit Documentation Feedback 11 Obsolete Devices UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 www.ti.com VIN RDD D2 R1 Z Q1 13 VDD 8 U1 UCC3917 PLIM 1 C1P OUTPUT 3 7 C1N SENSE 2 6 C2P VREF/CATFLT 15 5 C2N MAXI 14 11 FLOUT CT 10 12 SHTDWN VOUT 4 16 LATCH VSS 9 Short Pin D1 RGR R2 D2 GND Plug-In Card Back Plane UDG-00019 Figure 6. Soft-Start Operation with SHTDWN I/O INTERFACE The SHTDWN and LATCH inputs and FLTOUT output are referenced to VOUT. Level-shifting circuits are needed if the device communicates with logic that is referenced to load/system ground. INTERFACING TO LATCH AND SHTDWN Two level shift circuits for LATCH and SHTDWN are shown in Figure 7. The optocoupler (Figure 7) is simple, but the constant-current sink (Figure 8) is a low-cost solution. 12 SHTDWN 12 SHTDWN 1 kW 1 kW 16 LATCH IN 16 LATCH IN 4N25 GND 4N25 4 VOUT 4 GND UDG-11202 Figure 7. Optocoupler Interface 12 Submit Documentation Feedback VOUT UDG-11202 Figure 8. Constant-Current Sink Interface Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Obsolete Devices UCC2917 UCC3917 www.ti.com SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 Design Example 1: Using the TTL Signal to Control the LATCH Pin Input A TTL signal controls the LATCH input of the UCC3917 using the circuit in Figure 8. Determine the component values if the maximum load voltage is 60 V. The assumptions for this analysis are: • VBE ≈ 0.65 V • VCE(sat) ≈ 0.1 V • R1||R2 1.7 V • Logic "1" input: 2 V < VIH < 5 V ⇒ 60 mA < IC < 500 µA and VC < 1.7 V This response establishes the relationship between R1, R2, and R3. æ R2 ö R1 > 0.23 VB - VIL(max ) ´ ç ÷ < VBE ¾¾® R2 è R1 + R2 ø If VIN = VIL(max) = 0.8 V, then Q1 is off and If VIN = VIH(max) = 5 V, then: æ 1.7 V - VCE(sat ) ö æ R2 ö R1 ç ÷ < 500 mA ¾¾® R3 > 3.2kW I = C < ¾¾ ® > VB - VIL(max ) ´ ç V 0.23 ÷ BE ç ÷ R3 + R R R è ø 2ø 2 è 1 VC = VCE(sat ) + VE < 1.7 V ¾¾® VE < 1.6 V V = (V - V ) < 1.6 V ¾¾® V < 2.25 V E (V B - VIH(max ) ´ R2 ) R1 + R2 < 2.25 V ¾¾® B BE B R1 > 1.222 R2 If VIN = VIH(max) = 2 V, then: VB = IC = (V IH(min ) ´ R2 (R1 + R2 ) (VB - VBE ) R3 )¾¾® 2V æR ö 1+ ç 1 ÷ è R2 ø > 60 mA ¾¾® R3 < (VB - VBE ) 60 mA In summary, R1, R2, and R3 obey the inequalities: R1 > 1.222 R2 and 3.2kW < R3 < (VB - 0.65 ) 60 mA , where VB = 2V æR ö 1+ ç 1 ÷ è R2 ø If R1 / R2 = 1.3, then 3.2 kΩ < R3 < 3.66 kΩ. R1 = 4.64 kΩ for the case where R2 = R3 = 3 kΩ. The same design can be used to control the UCC3917's SHTDWN input. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Submit Documentation Feedback 13 Obsolete Devices UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 www.ti.com Interfacing to FLTOUT The level shift circuit in Figure 9 is a way to interface to FLTOUT. The operation of this circuit and the SHTDWN / LATCH level shift circuit in Figure 8 are similar. Design Example 2: A TTL-Compatible Output Level Shifter Using FLOUT This design example describes a TTL compatible output level shifter for FLTOUT. The maximum system voltage is 60 V. Use a level shift circuit as shown in Figure 9. The FLTOUT output can swing to the charge pump voltage, which is 10 V above the load voltage. In a 60-V application, the collector-emitter of Q1 can be as high as –70 V. A FMMT593 transistor, with a VCEO(max) rating of –100 V, is a suitable choice for Q1. 13 VDD R3 R2 R1 11 FLTOUT Q1 FLTOUT R4 GND UDG-00022 Figure 9. Interfacing to FLTOUT Calculation Steps Step 1. Output saturation voltage constraint. VC(on ) = VE + VCE(sat ) > 2.4 V (TTL output high ) (18) If VC(on ) = 2.6 V, then VE = 2.6 V + (-0.1V ) = 2.5 V (19) ( ) Step 2. Source current constraint. IC = 100 µA Step 3. Calculate the value of R3. R3 = (6 V - VE ) (6 V - VE ) (6 V - 2.5V ) IE = IC = 100 mA = 35kW (20) Step 4. Calculate the base voltage. VB = VE + VBE = (2.5 V - 0.65 V ) = 1.85 V (21) Step 5. Calculate the voltage divider. The voltage divider formula for R1 and R2 is shown in Equation 22 R2 R 6V ´ 6 V @ (6 V - VB ) or 1 = R2 (VB - 1) (R1 + R2 ) (22) Equation 23 assumes negligible loading by Q1. R1 = hfe ´ R3 R2 (23) 14 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Obsolete Devices www.ti.com UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 If hfe = 100, then: ö R1 æ R 6 =ç ÷ = 2.24 and 1 2.4 V, R 4 > 100 mA (25) Choose an R4 value of 49.9 kΩ. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Submit Documentation Feedback 15 Obsolete Devices UCC2917 UCC3917 SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 www.ti.com PRELOADING THE OUTPUT RDD provides a sneak path for current between 3 mA and 11 mA (e.g., at 0 V output) to trickle into the load when the power FET is off (see Figure 10). VIR VOUT RDD VDD OUTPUT 10 V + – VOUT LOAD 5V VSS Sneak Path UCC3917 RSS GND GND UDG-00021 Figure 10. Simplified Schematic Illustrating IDD Sneak Path This current causes an unacceptably high output voltage at shutdown if the output is not adequately loaded. In this case, it is necessary to preload the HSPM output to keep the shutdown voltage level acceptable. The preload also insures reliable start-up of the UCC3917 by holding the output voltage low when power is first applied to the HSPM. A resistor is usually an unacceptable preload because it creates a power dissipation problem when the FET turns on. For example, a 90.9-Ω preload (used to limit the shutdown voltage of a 48-V HSPM to less than 1 V) adds 25-W of power dissipation to the system. In a 100-V system, this dissipation increases to 110 W. The power dissipation overhead increases with the system voltage squared for a resistive preload. 16 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: UCC2917 UCC3917 Obsolete Devices UCC2917 UCC3917 www.ti.com SLUS203D – FEBRUARY 2000 – REVISED MAY 2013 Figure 11 shows how the active load limits the shutdown voltage without creating a power dissipation problem. 4 TAPER – VOUT Q3 VIN R4 R3 Q1 R2 Q2 R1 UDG-00024 Figure 11. Active Preload This load is a constant-current sink (i.e., Q3 is off) when the power FET is off. The shutdown voltage is less than 0.85 V if the sink current, set by R1, is greater than 11 mA. V ISNKFET(off ) = BE > 11A R1 (26) The power dissipation of Q1 is kept to a minimum when the power FET turns on by tapering the sink current as the load voltage rises as shown in Equation 27 . ö ææ V ö ö æ R2 ISNKFET(on ) = ç ç BE ÷ - VOUT ÷ ´ ç ÷ ç ÷ ç ÷ è è R1 ø ø è (R1 ´ R3 ) ø (27) For R1