UCC2946D


 SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007      
        FEATURES D Fully Programmable Reset Threshold D Fully Programmable Reset Period D Fully Programmable Watchdog Period D 2% Accurate Reset Threshold D Input Voltage Down to 2 V D Input 18-µA Maximum Input Current D Reset Valid Down to 1 V The UCCx946 is also resistant to glitches on the VDD line. Once RES has been deasserted, any drops below the threshold voltage need to be of certain time duration and voltage magnitude to generate a reset signal. These values are shown in Figure 1. An I/O line of the microprocessor may be tied to the watchdog input (WDI) for watchdog functions. If the I/O line is not toggled within a set watchdog period, programmable by the user, WDO is asserted. The watchdog function is disabled during reset conditions. DESCRIPTION The UCCx946 is designed to provide accurate microprocessor supervision, including reset and watchdog functions. During power up, the device asserts a reset signal RES with VDD as low as 1 V. The reset signal remains asserted until the VDD voltage rises and remains above the reset threshold for the reset period. Both reset threshold and reset period are programmable by the user. The UCCx946 is available in 8-pin SOIC(D), 8-pin PDIP (N) and 8-pin TSSOP(PW) packages to optimize board space. VDD 8 POWER TO CIRCUITRY 400 nA RP 4 + 1.235 V S Q 3 RES POWER ON RESET + R Q Q S Q R + RTH 2 WP 8−BIT COUNTER 400 nA 6 + + WATCHDOG TIMING WDI 7 1.235 V S Q R Q A2 100 mV + A3 CLR A1 5 WDO A0 CLK + EDGE DETECT 1 GND UDG−02192  
     !"#   $"%&! '#( '"! !  $#!! $# )# #  #* "# '' +,( '"! $!#- '#  #!#&, !&"'# #-  && $##( Copyright  2007, Texas Instruments Incorporated www.ti.com 1 

 SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007 ORDERING INFORMATION PACKAGED DEVICES(3) TA (D) (N) (PW) −40°C to 95°C UCC2946D UCC2946N UCC2946PW 0°C to 70°C UCC3946D UCC3946N UCC3946PW (1) The D and PW packages are also available taped and reeled. Add an R suffix to the device type (i.e., UCC2946DR) for quantities of 3,000 devices per reel. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UCC2946 UCC3946 UNIT 10 V Input voltage range, VIN Junction temperature range, TJ −55 to 150 Storage temperature, Tstg −65 to 150 °C C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal. D PACKAGE (TOP VIEW) GND RTH RES RP 1 8 2 7 3 6 4 5 VDD WDI WP WDO TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION GND 1 − Ground reference for the device RES 3 O This pin is high only if the voltage on the RTH has risen above 1.235 V. Once RTH rises above the threshold, this pin remains low for the reset period. This pin asserts low and remains low if the RTH voltage dips below 1.235 V for an amount of time determined by Figure 1. RTH 2 I This input compares its voltage to an internal 1.25-V reference. By using external resistors, a user can program any desired reset threshold. RP 4 I This pin allows the user to program the reset period by adjusting an external capacitor. VDD 8 I Supply voltage for the device. WDI 7 I This pin is the input to the watchdog timer. If this pin is not toggled or strobed within the watchdog period, WDO is asserted. WDO 5 O This pin is the watchdog output. This pin is asserted low if the WDI pin is not strobed or toggled within the watchdog period. WP 6 I This pin allows the user to program the watchdog period by adjusting an external capacitor. 2 www.ti.com 

 SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C and 2.0 V ≤ VDD ≤ 5.5 V for the UCC3946, TA = −40°C to 95°C and 2.1 V ≤ VDD ≤ 5.5 V for the UCC2946, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE VDD Operating voltage IDD Supply current VDD(min) Minimum operating voltage(1) UCC2946 2.1 5.5 UCC3946 2.0 5.5 UCC2946 12 18 UCC3946 10 18 UCC2946 1.1 UCC3946 1.0 V µA A V RESET SECTION UCC2946 Reset threshold voltage UCC3946 VDD rising 1.170 1.235 1.260 1.190 1.235 1.260 Threshold hysteresis ILEAK VOH VOL 15 Input leakage current ISOURCE = 2 mA ISINK = 2 mA UCC2946 Low-level output voltage UCC3946 VDD-to-output delay time ISINK = 20 µA, A, UCC3946 CRP = 64 nF nA VDD−0.3 0.1 0.4 VDD = 1 V V 0.2 VDD = −1 mV/µs UCC2946 Reset period mV 5 High-level output voltage V µs 120 140 200 320 160 200 260 ms WATCHDOG SECTION VIH VIL High-level input voltage, WDI 0.7×VDD Low-level input voltage, WDI UCC2946 Watchdog period UCC3946 CRP = 64 nF Watchdog pulse width VOH High-level output voltage VOL Low-level output voltage (1) Minimum supply voltage where RES is considered valid. 0.96 0.3×VDD 1.60 2.56 1.12 1.60 2.08 50 ISOURCE = 2 mA ISINK = 2 mA www.ti.com V s ns VDD−0.3 0.1 V 3 

 SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007 APPLICATION INFORMATION The UCCx946 supervisory circuit provides accurate reset and watchdog functions for a variety of microprocessor applications. The reset circuit prevents the microprocessor from executing code during undervoltage conditions, typically during power-up and power-down. In order to prevent erratic operation in the presence of noise, voltage glitches where voltage amplitude and time duration are less than the values specified in Figure 1 are ignored. 200 OVERDRIVE VOLTAGE WITH RESPECT TO RESET THRESHOLD vs DELAY TO OUTPUT LOW ON RESB 180 VTH − Overdrive Voltage − mV 160 140 120 100 80 RT Senses Glitch, RES Goes Low for Reset Period 60 40 20 0 100 Glitches Ignored, RESB Remains High 110 120 130 140 150 160 TDELAY − Delay Time − µs 170 180 Figure 1. The watchdog circuit monitors the microprocessor’s activity, if the microprocessor does not toggle WDI during the programmable watchdog period WDO goes low, alerting the microprocessor’s interrupt of a fault. The WDO pin is typically connected to the non-maskable input of the microprocessor so that an error recovery routine can be executed. 4 www.ti.com 

 SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007 APPLICATION INFORMATION PROGRAMMING THE RESET VOLTAGE AND RESET PERIOD The UCCx946 allows the reset trip voltage to be programmed with two external resistors. In most applications VDD is monitored by the reset circuit, however, the design allows voltages other than VDD to be monitored. Referring to Figure 2, the voltage below which reset is asserted is determined by: V RESET + 1.235 ) R2Ǔ ǒR1 R2 (1) In order to keep quiescent currents low, resistor values in the megaohm range can be used for R1 and R2. A manual reset can be easily implemented by connecting a momentary push switch in parallel with R2. RES is ensured to be low with VDD voltages as low as 1 V. VDD 8 POWER TO CIRCUITRY 400 nA RP 4 1.235 V S Q + CRP RES R Q RTH RESET 3 + − VDD R1 + − POWER ON RESET Q S 2 uP R2 I/O 8−BIT COUNTER Q R 400 nA WP 6 + CWP − A3 + A2 CLR A1 100 mV + WDI 7 Q R Q WDO 5 NMI A0 CLK + − 1.235 V S WATCHDOG TIMING EDGE DETECT GND 1 UDG−98002 Figure 2. Typical Application Diagram www.ti.com 5 

 SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007 APPLICATION INFORMATION Once VDD rises above the programmed threshold, RES remains low for the reset period defined by: T RP + 3.125 C RP (2) where TRP is time in milliseconds and CRP is capacitance in nanofarads. CRP is charged with a precision current source of 400 nA, a high-quality, low-leakage capacitor (such as an NPO ceramic) should be used to maintain timing tolerances. Figure 3 illustrates the voltage levels and timings associated with the reset circuit. UDG−97067 t1: VDD > 1 V, RES is ensured low. t2: VDD > programmed threshold, RES remains low for TRP. t3: TRP expires, RES pulls high. t4: Voltage glitch occurs, but is filtered at the RTH pin, RES remains high. t5: Voltage glitch occurs whose magnitude and duration is greater than the RTH filter, RES is asserted for TRP. t6: On completion of the TRP pulse the RTH voltage has returned and RES is pulled high. t7: VDD dips below threshold (minus hysteresis), RES is asserted. Figure 3. Reset Circuit Timings 6 www.ti.com 

 SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007 APPLICATION INFORMATION PROGRAMMING THE WATCHDOG PERIOD The watchdog period is programmed with CWP as follows: T WP + 25 C WP (3) where TWP is in milliseconds and CWP is in nanofarads. A high-quality, low-leakage capacitor should be used for CWP. The watchdog input WDI must be toggled with a high-to-low or low-to-high transition within the watchdog period to prevent WDO from assuming a logic level low. WDO maintains the low logic level until WDI is toggled or RES is asserted. If at any time RES is asserted, WDO assumes a high logic state and the watchdog period be reinitiated. Figure 4 illustrates the timings associated with the watchdog circuit. TRP VDD RESET 0V TWP VDD WDI 0V VDD WDO 0V t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 UDG−98007 t1: t2: t3: t4: t5: t6: t7: t8: t9: t10: t11: t12: t13: t14: Microprocessor is reset. WDI is toggled some time after reset, but before TWP expires. WDI is toggled before TWP expires. WDI is toggled before TWP expires. WDI is not toggled before TWP expires and WDO asserts low, triggering the microprocessor to enter an error recovery routine. The microprocessor’s error recovery routine is executed and WDI is toggled, reinitiating the watchdog timer. WDI is toggled before TWP expires. WDI is toggled before TWP expires. RES is momentarily triggered, RES is asserted low for TRP. Microprocessor is reset, RES pulls high. WDI is toggled some time after reset, but before TWP expires. WDI is toggled before TWP expires. WDI is toggled before TWP expires. VDD dips below the reset threshold, RES is asserted. Figure 4. Watchdog Circuit Timings www.ti.com 7 

 SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007 APPLICATION INFORMATION CONNECTING WDO TO RES In order to provide design flexibility, the reset and watchdog circuits in the UCCx946 have separate outputs. Each output independently drives high or low, depending on circuit conditions explained previously. In some applications, it may be desirable for either the RES or WDO to reset the microprocessor. This can be done by connecting WDO to RES. If the pins try to drive to different output levels, the low output level dominates. Additional current flows from VDD to GND during these states. If the application cannot support additional current (during fault conditions), RES and WDO can be connected to the inputs of an OR gate whose output is connected to the microprocessor’s reset pin. LAYOUT CONSIDERATIONS A 0.1-µF capacitor connected from VDD to GND is recommended to decouple the UCCx946 from switching transients on the VDD supply rail. Since RP and WP are precision current sources, capacitors CRP and CWP should be connected to these pins with minimal trace length to reduce board capacitance. Care should be taken to route any traces with high voltage potential or high speed digital signals away from these capacitors. Resistors R1 and R2 generally have a high ohmic value, traces associated with these parts should be kept short in order to prevent any transient producing signals from coupling into the high impedance RTH pin. TYPICAL CHARACTERISTICS INPUT CURRENT vs INPUT VOLTAGE THRESHOLD RESISTANCE vs AMBIENT TEMPERATURE 12.0 1.26 11.5 1.25 IDD − Input Current − µA VRTH − Threshold Resistance − V VDD = 5 V 1.24 1.23 1.22 10.5 10.0 9.5 1.21 1.20 −55 11.0 9.0 −35 −15 5 25 45 65 85 105 125 TA − Ambient Temperature − °C 3 4 5 VDD − Input Voltage − V Figure 6. Figure 5. 8 2 www.ti.com 6 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) UCC2946D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2946 Samples UCC2946DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2946 Samples UCC2946DTR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2946 Samples UCC2946PW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 2946 Samples UCC2946PWTR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 2946 Samples UCC3946D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3946 Samples UCC3946DTR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3946 Samples UCC3946PW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 3946 Samples UCC3946PWTR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 3946 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of