UCC3626PWTRG4


 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 
     FEATURES D Two-Quadrant and Four-Quadrant Operation D Integrated Absolute Value Current Amplifier D Pulse-by-Pulse and Average Current Sensing D Accurate, Variable Duty-Cycle Tachometer Output D Trimmed Precision Reference D Precision Oscillator D Direction Output DESCRIPTION The UCC3626 motor controller device combines many of the functions required to design a high-performance, two- or four-quadrant, threephase, brushless dc motor controller into one package. Rotor position inputs are decoded to provide six outputs that control an external power stage. A precision triangle oscillator and latched comparator provide PWM motor control in either voltage- or current-mode configurations. The oscillator is easily synchronized to an external master clock source via the SYNCH input. Additionally, a QUAD select input configures the chip to modulate either the low-side switches only, or both upper and lower switches, allowing the user to minimize switching losses in less demanding two-quadrant applications. The device includes a differential current-sense amplifier and absolute-value circuit which provide an accurate reconstruction of motor current, useful for pulse-by-pulse overcurrent protection, as well as closing a current control loop. A precision tachometer is also provided for implementing closed-loop speed control. The TACH_OUT signal is a variable duty-cycle, frequency output, which can be used directly for digital control or filtered to provide an analog feedback signal. Other features include COAST, BRAKE, and DIR_IN commands, along with a direction output, DIR_OUT. Copyright  2002, Texas Instruments Incorporated  
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 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 AVAILABLE OPTIONS TA PDIP (N) PACKAGED DEVICES SOIC{ (DW) TSSOP{ (PW) –40_C to 85_C UCC2626N UCC2626DW UCC2626PW 0_C to 70_C UCC3626N UCC3626DW UCC3626PW {The DW and PW packages are available taped and reeled. Add TR suffix to device type (e.g. UCC2626DWTR) to order quantities of 2,000 devices per reel. N PACKAGE (TOP VIEW) GND VREF TACH_OUT R_TACH C_TACH CT SYNCH DIR_OUT SNS_NI SNS_I IOUT OC_REF PWM_I PWM_NI 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DW and PW PACKAGES (TOP VIEW) VDD AHI ALOW BHI BLOW CHI CLOW DIR_IN QUAD BRAKE COAST HALLC HALLB HALLA GND VREF TACH_OUT R_TACH C_TACH CT SYNCH DIR_OUT SNS_NI SNS_I IOUT OC_REF PWM_I PWM_NI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD AHI ALOW BHI BLOW CHI CLOW DIR_IN QUAD BRAKE COAST HALLC HALLB HALLA absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Input voltage, BRAKE, COAST, DIR_IN, HALLA, HALLB, HALLC, OC_REF, QUAD, SYNCH, PWM_I, PWM_NI . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD SNS_I, SNS_NI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD Output current AHI, ALOW, BHI, BLOW, CHI, CLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA DIR_OUT, IOUT, TACH_OUT, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltages are with respect to GND. Currents are positive into negative out of the specified terminal. 2 www.ti.com 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 block diagram 28 VDD 2 VREF 27 AHI 25 BHI 23 CHI 26 ALOW 24 BLOW QUAD 20 5 VOLT REFERENCE BRAKE 19 COAST 18 1.75V DIR_IN 21 DIRECTION SELECT HALLA 15 HALLB 16 HALL DECODER HALLC 17 DIR_OUT 8 DIRECTION DETECTOR EDGE DETECTOR PWM_NI 14 22 CLOW PWM_I 13 PWM COMPARATOR OSCILLATOR RxC SYNCH 7 CT 6 OC_REF 12 IOUT 11 SNS_NI OVERCURRENT COMPARATOR S Q R Q S SENSE AMPLIFIER R 9 SNS_I 10 Q ONE SHOT Q 3 TACH_OUT 5 C_TACH 4 R_TACH 1 GND PWM LOGIC X5 UDG–97173 www.ti.com 3 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 electrical characteristics over recommended operating conditions, VCC = 12 V; CT = 1 nF, R_TACH = 250 kΩ, C_TACH = 100 pF, TA = TJ, TA = –40°C to 85°C for the UCC2626, and 0°C to 70°C for the UCC3626 (unless otherwise noted) overall PARAMETER TEST CONDITIONS Supply current Outputs not switching MIN TYP MAX UNIT 1 3 5 MIN TYP MAX UNIT mA undervoltage lockout PARAMETER TEST CONDITIONS Start threshold UVLO hysteresis 9.0 10.5 11.0 V 0.35 0.40 0.50 V MIN TYP MAX UNIT 4.9 5 5.1 V 10 mV 10 mV 5-V reference PARAMETER TEST CONDITIONS Output voltage Line regulation voltage IVREF = –2 mA 11 V < VCC < 14.5 V Load regulation voltage –1 mA > IVREF > –5 mA Short circuit current 40 120 240 mA coast input comparator MIN TYP MAX UNIT Threshold voltage PARAMETER TEST CONDITIONS 1.60 1.75 2.00 V Hysteresis 0.04 0.10 0.16 V MIN TYP MAX UNIT current sense amplifier PARAMETER TEST CONDITIONS Input offset voltage VCM = 0 V Input bias current VCM = 0 V 5 10 15 µA Gain VCM = 0 V 4.85 5.00 5.15 V/V PSRR 11 V < VCC < 14.5 V 60 dB High-level output voltage IIOUT= –100 µA IIOUT = 100 µA 6.3 V VIOUT = 2 V VIOUT = 2 V 500 µA 300 µA Low-level output voltage UCC3626 Output source current UCC2626 8 70 mV mV pwm comparator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input common mode range 2.0 8.0 V Propagation delay time 75 150 ns MAX UNIT overcurrent comparator PARAMETER TEST CONDITIONS MIN Input common mode range 0.0 Propagation delay time 50 MIN TYP 5.0 V 175 250 ns TYP MAX UNIT logic inputs PARAMETER TEST CONDITIONS High-level logic input voltage QUAD, BRAKE, DIR, SYNCH Low-level logic input voltage QUAD, BRAKE, DIR, SYNCH 4 www.ti.com 3.6 V 1.4 V 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 electrical characteristics over recommended operating conditions, VCC = 12 V; CT = 1 nF, R_TACH = 250 kΩ, C_TACH = 100 pF, TA = TJ, TA = –40°C to 85°C for the UCC2626, and 0°C to 70°C for the UCC3626 (unless otherwise noted) hall buffer inputs PARAMETER TEST CONDITIONS MIN TYP MAX 1.9 2.1 High-level input voltage HALLA, HALLB, HALLC 1.7 Hysteresis HALLA, HALLB, HALLC 0.6 Input current 0V < VIN < 5 V 1.0 UNIT V V µA –25 oscillator PARAMETER TEST CONDITIONS Frequency RTACH = 250 kΩ, CT = 1nF 12 V < VCC < 14.5 V Frequency change with voltage MIN TYP MAX UNIT 9.0 10.0 11.0 kHz 3% CT peak voltage 7.25 7.5 7.75 CT peak-to-valley voltage 4.75 5.0 5.25 SYNCH pin minimum pulse width 500 V V ns tachometer PARAMETER TEST CONDITIONS IOUT = –10 µA IOUT = 10 µA High-level output voltage/VREF Low-level output voltage MIN Low-level on-resistance High-level ramp threshold voltage CTACH charge current UNIT 20 mV 1 1.5 kΩ 1 1.5 kΩ 2.5 Ramp voltage On time accuracy On-time MAX 100% 0 IOUT = –100 µA IOUT = 100 µA High-level on-resistance TYP 99% 2.375 2.500 48 51 V 2.625 V 53 µA UCC3626 RTACH = 49.9 kΩ See Note 1 –3% 3% UCC2626 See Note 1 –4% 3% direction output PARAMETER TEST CONDITIONS IOUT = –100 µA IOUT = 100 µA High-level output voltage Low-level output voltage MIN TYP MAX UNIT 4.5 5.2 V 0 0.5 V output PARAMETER TEST CONDITIONS MIN TYP Maximum duty cycle IOUT = 2 mA IOUT = 100 µA 0.0 Lo le el o Low-level output tp t voltage oltage IOUT = –2 mA IOUT = –100 µA 4.0 High level output voltage High-level Rise and fall time CI = 10 pF NOTE 1: tON is calculated using the formula t ON + MAX UNIT 100% C TACH 0.1 0.0 4.7 4.8 0.5 V 0.1 V 5.2 V 5.2 V 100 ns ǒV HI * V LOǓ I CHARGE www.ti.com 5 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 pin descriptions AHI, BHI, CHI: Digital outputs used to control the high-side switches in a three-phase inverter. For specific decoding information reference Table I. ALOW, BLOW, CLOW: Digital outputs used to control the low-side switches in a three-phase inverter. For specific decoding information reference Table I. BRAKE: BRAKE is a digital input which causes the device to enter brake mode. In brake mode all three highside outputs (AHI, BHI & CHI) are turned off, while all three lowside outputs (ALOW, BLOW, CLOW) are turned on. During brake mode the tachometer output remains operational. The only conditions that can inhibit the low-side commands during brake are UVLO, exceeding peak current, the output of the PWM comparator, or the COAST command. COAST: The COAST input consists of a hysteretic comparator which disables the outputs. The input is useful in implementing an overvoltage bus clamp in four-quadrant applications. The outputs are disabled when the input is above 1.75 V. CT: This pin is used in conjunction with the R_TACH pin to set the frequency of the oscillator. A timing capacitor is normally connected between this point and ground and is alternately charged and discharged between 2.5 V and 7.5 V. C_TACH: A timing capacitor is connected between this pin and ground to set the width of the TACH_OUT pulse. The capacitor is charged with a current set by the resistor on pin R_TACH . DIR_IN: DIR_IN is a digital input which determines the order in which the HALLA, HALLB, and HALLC inputs are decoded. For specific decode information reference Table I. DIR_OUT: DIR_OUT represents the actual direction of the rotor as decoded from the HALLA, HALLB, and HALLC inputs. For any valid combination of HALLA, HALLB, and HALLC inputs there are two valid transitions; one of which translates to a clockwise rotation and another which translates to a counterclockwise rotation. The polarity of DIR_OUT is the same as DIR_IN while motoring, (i.e. sequencing from top to bottom in Table 1.) GND: GND is the reference ground for all functions of the part. Bypass and timing capacitors should be terminated as close as possible to this point. HALLA, HALLB, HALLC: These three inputs are designed to accept rotor position information positioned 120° apart. For specific decode information reference Table I. These inputs should be externally pulled up to VREF or another appropriate external supply. IOUT: IOUT represents the output of the current sense and absolute value amplifiers. The output signal appearing is a representation of the following expression: ǒ Ǔ I OUT + ABS I SNS_I * I SNS_NI 5 This output can be used to close a current control loop as well as provide additional filtering of the current sense signal. OC_REF: OC_REF is an analog input which sets the trip voltage of the overcurrent comparator. The sense input of the comparator is internally connected to the output of the current sense amplifier and absolute value circuit. PWM_NI: PWM_NI is the noninverting input to the PWM comparator. PWM_I: PWM_I is the inverting input to the PWM comparator. QUAD: The QUAD input selects between two-quadrant operation (QUAD = 0) and four-quadrant operation (QUAD = 1) . When in two-quadrant mode, only the low-side devices are effected by the output of the PWM comparator. In four-quadrant mode both high- and low-side devices are controlled by the PWM comparator. 6 www.ti.com 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 pin descriptions SYNCH: The SYNCH input is used to synchronize the PWM oscillator with an external digital clock. When using the SYNCH feature, a resistor equal to R_TACH must be placed in parallel with CT. When not using the SYNCH feature, SYNCH must be grounded. SNS_NI, SNS_I: These inputs are the noninverting and inverting inputs to the current sense amplifier, respectively. The integrated amplifier is configured for a gain of five. An absolute value function is also incorporated into the output in order to provide a representation of actual motor current when operating in four-quadrant mode. TACH_OUT: TACH_OUT is the output of a monostable triggered by a change in the commutation state, thus providing a variable duty cycle, frequency output. The on time of the monostable is set by the timing capacitor connected to C_TACH. The monostable is capable of being retriggered if a commutation occurs during its on-time. R_TACH: A resistor connected between R_TACH and ground programs the current for both the oscillator and tachometer. VDD: VDD is the input supply connection for this device. Undervoltage lockout keeps the outputs off for inputs below 10.5 V. The input should be bypassed with a 0.1-µF ceramic capacitor, minimum. VREF: VREF is a 5-V, 2% trimmed reference output with 5 mA of maximum available output current. This pin should be bypassed to ground with a ceramic capacitor with a value of at least 0.1 µF. APPLICATION INFORMATION Table 1 provides the decode logic for the six outputs, AHI, BHI, CHI, ALOW, BLOW, and CLOW as a function of the BRAKE, COAST, DIR_IN, HALLA, HALLB, and HALLC inputs. Table 1. Commutation Truth Table HALL INPUTS HIGH-SIDE OUTPUTS LOW-SIDE OUTPUTS C A B C A B C 1 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 X 1 X X X X 0 0 0 0 0 0 1 0 X X X X 0 0 0 1 1 1 0 0 X 1 1 1 0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 0 0 BRAKE COAST DIR_IN A B 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 0 www.ti.com 7 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 APPLICATION INFORMATION The UCC3626 is designed to operate with 120° position sensor encoding. In this format, the three position sensor signals are never simultaneously high or low. Motors whose sensors provide 60° encoding, can be converted to 120° using the circuit shown in Figure 1. In order to prevent noise from commanding improper commutation states, some form of low-pass filtering on HALLA, HALLB, and HALLC is recommended. Passive RC networks generally work well and should be located as close as possible to the device. Figure 2 illustrates these techniques. VREF VREF 1 kΩ 499 Ω 1 kΩ HALLB HALLA 499 Ω HALLA HALLA 2.2 nF 2.2 nF VREF 1 kΩ VREF HALLA 1 kΩ 1 kΩ 499 Ω HALLB 2N2222A HALLB HALLB 2.2 nF 2.2 nF VREF 1 kΩ VREF 499 Ω 1 kΩ HALLC HALLC HALLC HALLC 2.2 nF 2.2 nF UDG–97182 Figure 1. Converting Hall Code From 60° to 120° 8 499 Ω www.ti.com UDG–97185 Figure 2. Passive Hall Filtering Technique 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 APPLICATION INFORMATION configuring the oscillator The UCC3626 oscillator is designed to operate at frequencies up to 250 kHz and provide a triangle waveform on CT with a peak-to-peak amplitude of 5 V for improved noise immunity. The current used to program CT is derived from the R_TACH resistor according to the following equation: I OSC + 25 Amps R_TACH (1) The oscillator frequency is set by R_TACH and CT according to the following relationship: f OSC + 2.5 R_TACH CT Hz (2) Timing resistor values should be between 25 kΩ and 500 kΩ, while capacitor values should be between 100 pF and 1 µF. Figure 3 provides a graph of oscillator frequency for various combinations of timing components. As with any high-frequency oscillator, timing components should be located as close as possible to the device pins when laying out the printed-circuit board. It is also important to reference the timing capacitor directly to the ground pin on the UCC3626 rather than daisy chaining it to another trace or the ground plane. This technique prevents switching current spikes in the local ground from causing jitter in the oscillator. synchronizing the oscillator A common system specification is to have all oscillators synchronized to a master clock. The UCC3626 provides a SYNCH input for this purpose. The SYNCH input is designed to interface with a digital clock pulse generated by the master oscillator. A positive-going edge on this input causes the UCC3626 oscillator to begin discharging. In order for the slave oscillator to function properly, it must be programmed for a frequency slightly lower than that of the master. Also, a resistor equal to R_TACH must be placed in parallel with CT. Figure 4 illustrates the waveforms for a slave oscillator programmed to 20 kHz with a master frequency of 30 kHz. The SYNCH pin must be grounded when not used. 1.E+06 OSCILLATOR FREQUENCY vs TIMING CAPACITANCE fOSC – PWM Frequency – Hz R_TACH = 25 kΩ R_TACH = 100 kΩ 1.E+05 1.E+04 R_TACH = 250 kΩ R_TACH = 500 kΩ 1.E+03 1.E–09 1.E–07 1.E–08 1.E–10 CT – Oscillator Timing Capacitance – F Figure 3 www.ti.com 9 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 APPLICATION INFORMATION programming the tachometer The UCC3626 tachometer consists of a precision 5-V monostable, triggered by either a rising or falling edge on any of the three Hall inputs, HALLA, HALLB, and HALLC. The resulting TACH_OUT waveform is a variable duty-cycle square wave whose frequency is proportional to motor speed, as given by: TACH_OUT + V 20 P Hz (3) where P is the number of motor pole pairs and V is motor velocity in RPM. The on time of the monostable is programmed via timing resistor R_TACH and capacitor C_TACH according to the following equation: t ON + R_TACH C_TACH sec (4) Figure 5 provides a graph of on times for various combinations of R_TACH and C_TACH. On time is typically set to a value less than the minimum TACH_OUT period as given by: t PERIOD (min) + 20 V MAX P sec (5) where P is the number of motor pole pairs and V is motor velocity in RPM. TACHOMETER ON-TIME vs TIMING CAPACITANCE SYNCH WITHOUT SYNCH tON – Tachometer On–Time – s 1.E+00 R_TACH = 500 kΩ 1.E–01 1.E–02 R_TACH = 250 kΩ 1.E–03 R_TACH = 100 kΩ 1.E–04 1.E–05 CT WITH SYNCH R_TACH = 25 kΩ 1.E–06 1.E–10 1.E–09 1.E–08 1.E–07 1.E–06 C_TACH – Tachometer Timing Capacitance – F Figure 4. Oscillator Waveforms 10 Figure 5 www.ti.com 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 APPLICATION INFORMATION The TACH_OUT signal can be used to close a digital velocity loop using a microcontroller, as shown in Figure 6, or directly low-pass filtered in an analog implementation, Figure 7. UCC3626 MC68HC11 AD558 PB0–PB7 DB0–DB7 PC0 VCE 4 R_TACH 5 C_TACH 6 CT 14 PWM_NI VCS VOUT 13 PWM_I VOUTSENSE VOUTSELECT IC1 3 TACH_OUT UDG–97188 Figure 6. Digital Velocity Loop Implementation Using MC68HC11 two quadrant vs four quadrant control Figure 8 illustrates the four possible quadrants of operation for a motor. Two-quadrant control refers to a system in which operation is limited to quadrants I and III (where torque and velocity are in the same direction). With a two-quadrant brushless dc amplifier, there are no provisions other than friction to decelerate the load, limiting the approach to less demanding applications. Four-quadrant controllers, on the other hand, provide controlled operation in all quadrants, including II and IV, where torque and rotation are of opposite direction. UCC3626 2 VREF 4 R_TACH 5 C_TACH 6 CT VELOCITY CW II I III IV CCW 14 – TORQUE CW PWM_NI 13 PWM_I 3 TACH_OUT + CCW UDG–97189 UDG–01118 Figure 8. Four Quadrants of Operation Figure 7. Simple Analog Velocity Loop www.ti.com 11 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 APPLICATION INFORMATION When configured for two-quadrant operation, (QUAD=0), the UCC3626 modulates only the low-side devices of the output power stage. The current paths within the output stage during the PWM on- and off-times are illustrated in Figure 9. During the on interval, both switches are on, and current flows through the load down to ground. During the off time, the lower switch is shut off, and the motor current circulates through the upper half bridge via the flyback diode. The motor is assumed to be operating in either quadrant I or III. If operation is attempted in quadrants II or IV by changing the DIR bit and reversing the torque, switches 1 and 4 are turned off and switches 2 and 3 turned on. Under this condition motor current very quickly decays, reverses direction and increases until the control threshold is reached. At this point, switch 2 turns off and current once again circulates in the upper half bridge. However, in this case, the motor’s BEMF is in phase with the current, (i.e. the motor’s direction of rotation has not yet changed.) Figure 10 illustrates the current paths when operating in this mode. Under these conditions there is nothing to limit the current other than motor and drive impedance. These high-circulating currents can result in damage to the power devices in addition to high, uncontrolled torque. VMOT VMOT S3 S1 S3 S1 S5 S5 IOFF IOFF IPHASE IPHASE + BEMF – + BEMF – ION ION S2 S4 S2 S6 UDG–01119 S6 UDG–01120 Figure 10. Two-Quadrant Reversal Figure 9. Two-Quadrant Chopping 12 S4 www.ti.com 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 APPLICATION INFORMATION By pulse width modulating both the upper and lower power devices (QUAD=1), motor current always decays during the PWM off time, eliminating any uncontrolled circulating currents. In addition, current always flows through the current sense resistor, providing a suitable feedback signal. Figure 11 illustrates the current paths during a four-quadrant torque reversal. Motor drive waveforms for both two- and four-quadrant operation are illustrated in Figure 12. VMOT S3 S1 S5 IPHASE + BEMF – IOFF ION S2 S4 S6 UDG–01121 Figure 11. Four-Quadrant Reversal www.ti.com 13 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 APPLICATION INFORMATION ROTOR POSITION IN ELECTRICAL DEGREES 0 60 120 180 240 300 360 420 480 540 600 660 720 H1 SENSOR INPUTS H2 H3 Code 101 100 110 010 011 001 101 100 110 010 011 001 HIGH SIDE AHI OUTPUTS QUAD=0 BHI CHI ALO LOW SIDE OUTPUTS BLO QUAD=0 CLO + A 0 – MOTOR PHASE CURRENTSB QUAD=0 + 0 – + C 0 – HIGH SIDE AHI OUTPUTS QUAD=1 BHI CHI ALO LOW SIDE OUTPUTS BLO QUAD=1 CLO + A 0 – MOTOR PHASE CURRENTSB QUAD=1 + 0 – + C 0 – 100% Duty Cycle PWM 50% Duty Cycle PWM Figure 12. Motor Drive and Current Waveforms for Two-Quadrant (QUAD=0) and Four-Quadrant (QUAD=1) Operation 14 www.ti.com UDG–97190 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 APPLICATION INFORMATION power stage design considerations The flexible architecture of the UCC3626 requires the user to pay close attention to the design of the power output stage. Two- and four-quadrant applications not requiring the brake function are able to use the power stage approach illustrated in Figure 13a. In many cases the body diode of the MOSFET can be used to reduce parts count and cost. If efficiency is a key requirement, Schottky diodes can be used in parallel with the switches. UDG–97190 VMOT VMOT CURRENT SENSE VMOT TO TO MOTOR MOTOR CURRENT SENSE TO MOT CURRENT SENSE (a) (b) (c) UDG–01122 CURRENT SENSE TWO QUADRANT FOUR QUADRANT SAFE BRAKING POWER REVERSAL (a) YES (b) YES YES NO NO YES (c) YES YES YES PULSE-BYPULSE AVERAGE Four-Quad Only YES YES No YES NO Four-Quad Only YES YES Figure 13. Power Stage Topologies If the system requires a braking function, diodes must be added in series with the lower power devices and the lower flyback diodes must be returned to ground, as pictured in Figure 13b, and 13c. This requirement prevents brake currents from circulating in the lower half bridge and bypassing the sense resistor. In addition, the combination of braking and four-quadrant control necessitates an additional resistor in the diode path to sense current during the PWM off time as illustrated in Figure 13c. www.ti.com 15 

 SLUS318B – APRIL 1999 – REVISED JANUARY 2002 APPLICATION INFORMATION current sensing The UCC3626 includes a differential current-sense amplifier with a fixed gain of five, along with an absolute value circuit. The current-sense signal should be low pass filtered to eliminate leading-edge spikes. In order to maximize performance, the input impedance of the amplifier should be balanced. If the sense voltage must be trimmed for accuracy reasons, a low-value input divider or a differential divider should be used to maintain impedance matching, as shown in Figure 14. RF RF SNS_NI RADJ RADJ RS SNS_NI RF CF RS CF RF RF SNS_I SNS_I RADJ