UCC381DP-3

UCC281-3/-5/-ADJ UCC381-3/-5/-ADJ Low Dropout 1 Ampere Linear Regulator Family FEATURES DESCRIPTION • Precision Positive Linear Voltage Regulation The UCC381-3/-5/-ADJ family of positive linear series pass regulators is tailored for low drop out applications where low quiescent power is important. Fabricated with a BiCMOS technology ideally suited for low input to output differential applications, the UCC381 will pass 1A while requiring only 0.5V of input voltage headroom. Dropout voltage decreases linearly with output current, so that dropout at 200mA is less than 100mV. Quiescent current is always less than 650µA. To prevent reverse current conduction, on-chip circuitry limits the minimum forward voltage to typically 50mV. Once the forward voltage limit is reached, the input-output differential voltage is maintained as the input voltage drops until undervoltage lockout disables the regulator. • 0.5V Dropout at 1A • Guaranteed Reverse Input/ Output Voltage Isolation with Low Leakage • Low Quiescent Current Irrespective of Load • Adjustable Output Voltage Version • Fixed Versions for 3.3V and 5V Outputs UCC381-3 and UCC381-5 versions have on-chip resistor networks preset to regulate either 3.3V or 5.0V, respectively. Furthermore, remote sensing of the load voltage is possible by connecting the VOUTS pin directly at the load. The output voltage is then regulated to 1.5% at room temperature and better than 2.5% over temperature. The UCC381-ADJ version has a regulated output voltage programmed by an external user-definable resistor ratio. • Logic Shutdown Capability • Short Circuit Power Limit of 3% • VIN • Current Limit • Remote Load Voltage for Accurate Load Regulation (continued) BLOCK DIAGRAM VIN 8 VPUMP VOLTAGE AMPLIFIER CURRENT LIMIT 1.3/2.1A CURRENT REFERENCE 4 VOUTS 2 GND 3 GND 6 GND 7 GND – – + + SHUTDOWN FOR FIXED VERSIONS R1 5 0.65V *ADJ VERSION ONLY VOUT R2 1.25V CT* 1 3% DUTY CYCLE CURRENT LIMIT TIMER R2 REVERSE VOLTAGE SENSE UCC381-ADJ UVLO THERMAL SHUTDOWN R1 0 OPEN UCC381-3 82k 50k UCC381-5 150k 50k UDG-98112 SLUS214B -JANUARY 2001 UCC281-3/-5/-ADJ UCC381-3/-5/-ADJ CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 3V Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . −55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C SOIC-8 (Top View) DP Package Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. All voltages are referenced to GND. VOUT 1 8 VIN GND 2 7 GND GND 3 6 GND VOUTS 4 5 CT* * ADJ version only DESCRIPTION (cont.) Short circuit current is internally limited. The device responds to a sustained overcurrent condition by turning off after a TON delay. The device then stays off for a period, TOFF, that is 32 times the TON delay. The device then begins pulsing on and off at the TON /(TON+TOFF) duty cycle of 3%. This drastically reduces the power dissipation during short circuit such that heat sinking, if at all required, must only accommodate normal operation. On the fixed output versions of the device TON is fixed at 400µs − a guaranteed minimum. On the adjustable version an external capacitor sets the on time. The off time is always 32 times TON. The UCC381 can be shutdown to 25µA (max) by pulling the CT pin low. Internal power dissipation is further controlled with thermal overload protection circuitry. Thermal shutdown occurs if the junction temperature exceeds 165°C. The chip will remain off until the temperature has dropped 20°C. The UCC281 series is specified for operation over the industrial range of −40°C to +85°C, and the UCC381 series is specified from 0°C to +70°C. These devices are available in the 8 pin DP surface mount power package. For other packaging options consult the factory. ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC381-X series and −40°C to +85°C for the UCC283-X series, VIN = VOUT + 1.5V, IOUT = 0mA, COUT = 2.2µF. CT = 1500pF for the UCC381-ADJ version and VOUT set to 5V. TJ = TA. PARAMETER TEST CONDITIONS MIN TYP TJ = 25°C 4.925 5 Over Temperature 4.875 MAX UNITS UCC381-5 Fixed 5V, 1A Family Output Voltage 5.075 V 5.125 V Line Regulation VIN = 5.15V to 9V 1 3 mV Load Regulation IOUT = 0mA to 1A 2 5 mV Drop Out Voltage, VIN – VOUT Peak Current Limit IOUT = 1A, VOUT = 4.85V, TA < 85°C 0.5 0.6 V IOUT = 200mA, VOUT = 4.85V, TA < 85°C 100 200 mV VOUT = 0V 2 Overcurrent Threshold 1 Current Limit Duty Cycle VOUT = 0V Overcurrent Time Out, TON VOUT = 0V 400 Quiescent Current Quiescent Current in Shutdown VIN = 9V Shutdown Threshold At CT Input Reverse Leakage Current 1V < VIN < VOUT, VOUT < 5.1V, at VOUT UVLO Threshold VIN where VOUT passes current 0.25 2 2.5 3.5 A 1.8 A 3 5 % 750 1600 µs 400 650 µA 10 25 µA 75 µA 3.0 V 0.65 2.8 V UCC281-3/-5/-ADJ UCC381-3/-5/-ADJ ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC381-X series and −40°C to +85°C for the UCC283-X series, VIN = VOUT + 1.5V, IOUT = 0mA, COUT = 2.2µF. CT = 1500pF for the UCC381-ADJ version and VOUT set to 5V. TJ = TA. PARAMETER TEST CONDITIONS MIN TYP TJ = 25°C 3.25 3.3 Over Temperature 3.22 MAX UNITS UCC381-3 Fixed 3.3V, 1A Family Output Voltage 3.35 V 3.38 V Line Regulation VIN = 3.45V to 9V 1 3 mV Load Regulation IOUT = 0mA to 1A 2 5 mV Dropout Voltage, VIN - VOUT Peak Current Limit IOUT = 1A, VOUT = 3.15V, TA < 85°C 0.6 0.8 V IOUT = 200mA, VOUT = 3.15V, TA < 85°C 100 200 mV VOUT = 0V 2 Overcurrent Threshold 1 Current Limit Duty Cycle VOUT = 0V Overcurrent Time Out, TON VOUT = 0V 400 Quiescent Current 3.5 A 1.8 A 3 5 % 750 1600 µs 400 650 µA 10 25 µA 75 µA Quiescent Current in Shutdown VIN = 9V Shutdown Threshold At CT Input Reverse Leakage Current 1V < VIN < VOUT, VOUT < 3.35V, at VOUT UVLO Threshold VIN where VOUT passes current 2.5 2.8 3.0 V TJ = 25°C 1.23 1.25 1.27 V Over Temperature 1.22 1.28 V 0.25 0.65 V UCC381-ADJ Adjustable Output, 1A Family Regulating Voltage at ADJ Input Line Regulation, at ADJ Input VIN = VOUT + 150mV to 9V 1 3 mV Load Regulation, at ADJ Input IOUT = 0mA to 1A 2 5 mV Dropout Voltage, VIN - VOUT Peak Current Limit IOUT = 1A, VOUT = 4.85V 0.5 0.6 V IOUT = 200mA, VOUT = 4.85V 100 200 mV VOUT = 0V 2 Overcurrent Threshold Current Limit Duty Cycle VOUT = 0V Overcurrent Time Out, TON VOUT = 0V, CT = 1500pF 400 Quiescent Current Quiescent Current in Shutdown VIN = 9V Shutdown Threshold At CT Input Reverse Leakage Current 1V < VIN < VOUT, VOUT < 9V, at VOUT 0.25 Bias Current at ADJ Input UVLO Threshold 3.5 A 1.8 A 3 5 % 1000 1600 µs 400 650 µA 10 25 µA 1 VIN where VOUT passes current 3 2.5 0.65 V 100 µA 100 250 nA 2.8 3.0 V UCC281-3/-5/-ADJ UCC381-3/-5/-ADJ PIN DESCRIPTIONS spect to the required transient loading. For example, if the load is very dynamic, a large capacitor will smooth out the response to load steps. CT: For UCC381-3 and UCC381-5 versions, this is the shutdown pin which, when pulled low, turns off the regulator output and puts the device in a low current state. For the UCC381-ADJ version, a capacitor is required between the CT pin and GND to set the TON time during overcurrent according to the following (typical) equation: VOUTS: Feedback for regulator sensing of the output voltage. For loads which are a considerable resistive distance from the VOUT pin, the VOUTS pin can be used to move the resistance into the control loop of the regulator, thereby effectively canceling the IR drop associated with the load path. For local regulation, merely connect this pin directly to the VOUT pin. For the UCC381-ADJ version, the output voltage can be set by two external resitors according to the following relationship: TON = 660 ,000 • CCT GND: All voltages are measured with respect to this pin. This is the low noise ground reference input for regulation. The output decoupling capacitor should be tied to PIN 7. VIN: Positive supply input for the regulator. Bypass this pin to GND with at least 1µF of low ESR, ESL capacitance if the source is located further than 1 inch from the device. R2   VOUT = 1. 25 •  1 +  R1   where R1 is a resistor connected between VOUT and VOUTS and R2 is a resistor connected between VOUTS and GND. VOUT: Output for regulator. The regulator does not require a minimum output capacitor for stability. Choose the appropriate size capacitor for the application with re- TYPICAL APPLICATION CIRCUIT CT NOTE 2 SHUTDOWN R2 NOTE 1 5 CT VOUTS VIN 8 R1 NOTE 1 UCC381 VIN VOUT 1.0µF 4 GND GND GND GND 7 6 3 2 1 OUTPUT COUT UDG-98148 Note 1: R1 and R2 for adjustable version only. For 3.3V and 5V versions connect VOUT to VOUTS. See Pin Descriptions. Note 2: CT timing capacitor is for adjustable version only. For 3.3V and 5V versions, the CT pin is used to enable or shutdown the part. See Pin Descriptions. 4 UCC281-3/-5/-ADJ UCC381-3/-5/-ADJ APPLICATION INFORMATION Overview The UCC381 family of low dropout linear (LDO) regulators provide a regulated output voltage for applications with up to 1A of load current. The regulator features a low dropout voltage and short circuit protection, making their use ideal for demanding high current applications requiring fault tolerance. A capacitive load on the regulator’s output will appear as a short circuit during start-up. If the capacitance is too large, the output voltage will not come into regulation during the initial TON period and the UCC381 will enter pulsed mode operation. The peak current limit, TON period, and load characteristics determine the maximum value of output capacitor that can be charged. For a constant current load the maximum output capacitance is given as follows: Short Circuit Protection The UCC381 provides unique short circuit protection circuitry that reduces power dissipation during a fault. When an overload situation is detected, the device enters a pulsed mode of operation at 3% duty cycle reducing the heat sink requirements during a fault. The UCC381 has two current thresholds that determine its behavior during a fault as shown in Fig. 1. When the regulator current exceeds the Overcurrent Threshold for a period longer than the TON, the UCC381 shuts off for a period (TOFF) which is 32 times TON. If the short circuit current exceeds the Peak Current Limit, the regulator limits the current to peak current limit during the TON period. The peak current limit is nominally 1 Amp greater than the overcurrent threshold. The regulator will continue in pulsed mode until the fault is cleared as illustrated in Fig. 1. COUT (max ) = (ICL − I LOAD ) • TON Farads VOUT (1) For worst case calculations the minimum values of on time (TON) and peak current limit (ICL) should be used. The adjustable version allows the TON time to be adjusted with a capacitor on the CT pin: TON (adj ) (µ sec) = 660 , 000 • C (µ Farads ) (2) For a resistive load (RLOAD) the maximum output capacitor can be estimated from: COUT (max ) = (3) TON R LOAD    1 • ln  VOUT  1−  I •R   CL LOAD           Farads OVERLOAD OUTPUT CURRENT PEAK CURRENT LIMIT IO (nom) OVERCURRENT THRESHOLD VO (nom) ROL ICL OUTPUT VOLTAGE TON 32T ON TON 32T ON Figure 1. UCC381 short circuit timing. 5 TON 32T ON UDG-98150 UCC281-3/-5/-ADJ UCC381-3/-5/-ADJ APPLICATION INFORMATION (cont.) Dropout Performance Referring to the Block Diagram, the dropout voltage of the UCC381 is equal to the minimum voltage drop (VIN to VOUT) across the N-Channel MOSFET. The dropout voltage is dependent on operating conditions such as load current, input and load voltages, as well as temperature. The UCC381 achieves a low Rds(ON) through the use of an internal charge-pump (VPUMP) that drives the MOSFET gate. Fig. 2 depicts typical dropout voltages versus load current for the 3.3V and 5V versions of the part, as well as the adjustable version programmed to 3.0V. VOUT -VIN (V) Vout = 3V Fig. 3 depicts the typical dropout performance of the adjustable version with various output voltages and load currents. 0.2 Operating temperatures effect the RDS(ON) and dropout voltage of the UCC381. Fig. 4 graphs the typical dropout for the 3.3V and 5V versions with a 3A load over temperature. 0.4 0.6 IOUT(A) DROP (3V) Referring to the Typical Application Circuit, the output voltage for the adjustable version is externally programmed through a resistive divider at the VOUTS pin as shown. 0.7 VIN-VOUT (V) 0.8 VOUT Vout = 5V 0.8 1 Figure 2. Typical dropout vs. load current. Voltage Programming R2   = 1. 25 •  1 +  Volts R1   Vout = 3.3V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 (4) DROP (5V) 0.6 0.5 For the fixed Voltage versions the resistive divider is internally set, and the VOUTS pin should be connected to the VOUT pin. The maximum programmed output voltage for the adjustable part is constrained by the 9V absolute rating of the IC (including the charge pump voltage) and its ability to enhance the N-Channel MOSFET. Unless the load current is well below the 1A rating of the device, output voltages above 7V are not recommended. The minimum output voltage can be programmed down to 1.25V, however, the input voltage must always be greater than the UVLO of the part. 0.4 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 Figure 4. Typical dropout vs. temperature (1A load). Iout = 0.2A Iout = 0.5A Iout = 1.0A 0.7 0.6 Shutdown Feature 0.5 VIN-VOUT (V) All versions include a shutdown feature, limiting quiescent current to 25µA typical. The UCC381 is shut down by pulling the CT pin to below 0.25V. As shown in the applications circuit, a small logic level MOSFET or BJT transistor connected to the CT pin can be driven with a digital signal, putting the device in shutdown. If the CT pin is not pulled low, the IC will internally pull up on the pin, enabling the regulator. The CT pin should not be forced high, as this will interfere with the short circuit protection feature. Selection of the timing capacitor for the adjustable version is explained in the Short Circuit Protection section. 0.4 0.3 0.2 0.1 0 3 3.5 4 4.5 5 VOUT (V) Figure 3. Typical dropout voltate vs. IOUT and VOUT. 6 UCC281-3/-5/-ADJ UCC381-3/-5/-ADJ APPLICATION INFORMATION (cont.) mal resistance is required by the application, the device heat sinking would need to be improved. Thermal Design The Packing Information section of the data book contains reference material for the thermal ratings of various packages. The section also includes an excellent article Thermal Characteristics of Surface Mount Packages, that is the basis of the following discussion. When the UCC381 regulator is in pulsed mode, due to an overload or short circuit in the application, the maximum average power dissipation is calculated as follows: PPULSE (avg ) = Thermal design for the UCC381 includes two modes of operation, normal and pulsed mode. In normal operation, the linear regulator and heat sink must dissipate power equal to the maximum forward voltage drop multiplied by the maximum load current. Assuming a constant current load, the expected heat rise at the regulator’s junction can be calculated as follows: T RISE = PDISS • (θ jc + θ ca) ° C (V IN (6)  TON − VOUT ) • ICL •   33 • TON   Watts  As seen in equation 6, the average power during a fault is reduced dramatically by the duty cycle, allowing the heat sink to be sized for normal operation. Although the peak power in the regulator during the TON period can be significant, the thermal mass of the package will generally keep the junction temperature from rising unless the TON period is increased to tens of milliseconds. (5) Where theta is thermal resistance and PDISS is the power dissipated. The thermal resistance of both the SOIC-8 DP package (junction to case) is 22 degrees Celsius per Watt. In order to prevent the regulator from going into thermal shutdown, the case to ambient theta must keep the junction temperature below 150C. If the LDO is mounted on a 5 square inch pad of 1 ounce copper, for example, the thermal resistance from junction to ambient becomes 40-70 degrees Celsius per Watt. If a lower ther- Ripple Rejection Even though the UCC381 linear regulators are not optimized for fast transient applications (Refer to UC182 “Fast LDO Linear Regulator”), they do offer significant power supply rejection at lower frequencies. Fig 5. depicts ripple rejection performance in a typical application. The performance can be improved with additional filtering. 90 RIPPLE REJECTION (db) 80 70 60 50 10uF, IOUT = 100mA 40 30 1uF, IOUT = 100mA 20 10uF, IOUT = 1A 10 0 1.0E+02 1uF, IOUT = 1A 1.0E+03 1.0E+04 FREQUENCY Figure 5. Ripple rejection vs. frequency. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 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