UCC5519PWPG4

 SLUS555 – FEBRUARY 2003   
   
            
  FEATURES D Meets SCSI–2, Ultra2 (SPI–2), Ultra3/Ultra160 D D D D D D (SPI–3), and Ultra320 (SPI–4) Standards 2.7-V to 5.25-V Termpwr Operation Built in SPI–3 Delay 3-pF Channel Capacitance Pin Compatible with SS–AR7519 225-mA MIN Source Regulator, Supports SE With all 9 Lines Low Available in a 28-Pin (PWP) TSSOP Package DESCRIPTION The UCC5519 is a multimode small computer system interface (SCSI) terminator that integrates the mode change delay function required by the SPI–3 specification. The device senses what types of SCSI drivers are present on the bus via the voltage on the DIFFSENS SCSI control line. High-voltage differential (HVD) SCSI drivers (EIA485) are not supported. If the chip detects the presence of a HVD SCSI device, it disconnects itself by switching all terminating resistors off the bus and enters a high-impedance state. The terminator can also be commanded to disconnect the terminating resistors with the DISCNCT input. Impedance is trimmed for accuracy and maximum effectiveness. Bus lines are biased to a fail-safe state to ensure signal integrity. BLOCK DIAGRAM HPD 2.15 V DIFFB DIGITAL FILTER 100 ms TO 300 ms 17 LVD 0.6 V SE REF 1.3 V 16 SOURCE/SINK REGULATORS SE REF 2.7 V DIFSENS 110 52 LVD REF 1.25 V 125 1.05 µA 3 L1– 2 L1+ 24 L9– 25 L9+ 52 10 µA 1.05 µA DISCNCT 13 110 TRMPWR 2.7 V to 5.25 V TRMPWR 2.7 V to 5.25 V 28 27 MODE SW1 SE LVD HVD DISCNCT UP DOWN OPEN OPEN OTHER SWITCHES 52 125 UP DOWN OPEN OPEN 1.05 µA 52 1.05 µA 1 14 REG GND 22 UDG–03017 6 HS/GND These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright  2003, Texas Instruments Incorporated  
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 SLUS555 – FEBRUARY 2003 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UCC5519 TERMPWR voltage 6 Signal line voltage 0 to 6 Package power dissipation UNIT V 0.5 W Operating junction temperature, TJ –55 to 150 °C Storage temperature, Tstg –65 to 150 (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of, the specified terminal. RECOMMENDED OPERATING CONDITIONS MIN TERMPWR voltage 2.7 NOM MAX UNIT 5.25 V ORDERING INFORMATION PACKAGED DEVICE TA DISCONNECT STATUS TSSOP–28 (PWP) 0°C to 70°C Regular UCC5519PWP † The PWP packages are available taped and reeled. Add R suffix to device type (e.g. UCC5519PWPR) to order quantities of 2,500 devices per reel. PWP PACKAGE (TOP VIEW) REG LINE1+ LINE1– LINE2+ LINE2– HS/GND LINE3+ LINE3– LINE4+ LINE4– LINE5+ LINE5– DISCNCT GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC – No internal connection 2 www.ti.com 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TERMPWR TERMPWR LINE9– LINE9+ LINE9– LINE8+ HS/GND LINE7– LINE7+ LINE6– LINE6+ DIFFB DIFFSENSE NC 
 SLUS555 – FEBRUARY 2003 ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C, TERMPWR = 2.7 V to 5.25 V, (unless otherwise specified the measurements). TERMPWR supply current PARAMETER TERMPWR supplyy current TEST CONDITION MIN TYP LVD (No load) 25 SE (No Load) 15 Disabled terminator MAX UNITS mA 2.5 TERMPWR voltage 2.7 5.25 V UNITS regulator PARAMETER TEST CONDITION MIN TYP MAX 1.25-V regulator LVD mode, 0.5 V _ VCM _ 2.0 V, all lines loaded 1.15 1.25 1.35 2.7-V regulator SE mode 2.5 2.7 3.0 1.3-V regulator Differential sense, ––5 mA _ IDIFSENSE _ 50 µA 1.2 1.3 1.4 1.25-V/2.7-V regulator source current LVD mode, VREG = 0 –225 –420 –800 1.25-V/2.7-V regulator sink current LVD mode, VREG = 3. 3 100 180 420 1.3-V regulator source current Differential sense, VDIF = 0 V –5 –15 1.3-V regulator sink current Differential sense, VDIF = 2.75 V 50 200 µA MAX UNITS V mA differential termination PARAMETER TEST CONDITION Differential impedance Common mode impedance (3) Differential bias current Output leakage Disabled, TERMPWR 0 < 5.25 V Output capacitance Single ended measurement to ground,(1) MIN TYP 100 105 110 Ω 100 200 100 125 mV 400 nA 3 pF NOTES: 1. 2. 3. 4. Ensured by design and engineering test, but not production tested. Current is the absolute value of current, as some addresses are pulled high, while others are pulled low. ZCM = 1.2 V/ 1(VCM +0.6) – I(VCM –0.6V); Where VCM = Voltage measured with L+ tied to L– and zero current applied; VLX= Output voltage for each terminator minus output pin (L1– through L9–) with each pin unloaded. ILX = Output current for each terminator minus output pin (L1– through L9–) with the minus output pin forced to 0.2V. 5. Noise on DIFFB will not cause a false mode change. The time delay is that same for a change from any mode to anyother mode. Within 300 ms after power is applied the mode is defined by the voltage of DIFFB. www.ti.com 3 
 SLUS555 – FEBRUARY 2003 ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C, TERMPWR = 2.7 V to 5.25 V, (unless otherwise specified the measurements). single ended termination section PARAMETER TEST CONDITION MIN TYP MAX UNITS Impedance Z = (VLx –0.2 V)/Ilx, (4) 100 108 116 Ω Signal level 0.2 V, all lines low –20 –23 –25.4 Signal level 0.5 V –17 Termination current –22.4 Output leakage Output capacitance Single ended measurement to ground(1) SE GND driver impedance I = 10 mA mA 400 nA 3 pF 20 60 Ω TYP MAX UNITS 0.8 2.0 V –1 1 10 30 Disconnect (DISCNCT) and Diff Buffer (DIFFB) input section PARAMETER TEST CONDITION MIN DISCNT threshold Input current DIFF B 0 V _ VDIFFB _ 2.75 V Input current disconnect µΑ Α time delay/filter PARAMETER TEST CONDITION MIN TYP MAX UNITS Mode change delay A new mode can start any time after a previous mode change has been detected.(5) 100 190 300 ms MIN TYP MAX UNITS –6 –4 status line output characteristics PARAMETER TEST CONDITION Source current VLOAD = 2.4 V Sink current VLOAD = 0.4 V mA 2 NOTES: 1. 2. 3. 4. 5 Ensured by design and engineering test, but not production tested. Current is the absolute value of current, as some addresses are pulled high, while others are pulled low. ZCM = 1.2 V/ 1(VCM +0.6) – I(VCM –0.6V); Where VCM = Voltage measured with L+ tied to L– and zero current applied; VLX= Output voltage for each terminator minus output pin (L1– through L9–) with each pin unloaded. ILX = Output current for each terminator minus output pin (L1– through L9–) with the minus output pin forced to 0.2V. 5. Noise on DIFFB will not cause a false mode change. The time delay is that same for a change from any mode to anyother mode. Within 300 ms after power is applied the mode is defined by the voltage of DIFFB. 4 www.ti.com 
 SLUS555 – FEBRUARY 2003 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION DIFF SENSE 16 O The SCSI bus DIFF SENSE line to detect what types of devices is connected to the SCSI bus. DISCNT 13 I Disconnect pin shuts down the terminator when it is not at the end of the bus. The disconnect pin low enables the terminator. DIFF B 17 I Senses the bus mode, a 50-Hz filter is required, 0.1 µF to ground and 20 kΩ to the SCSI bus DIFF SENSE line with internal SPI–3 100-ms to 300-ms delay. High-voltage differential has been detected on the DIFF B pin; the terminator is in high impedance. (Not brought out) HVD Line n– O Negative line in differential applications for the SCSI bus. Line n+ O Positive line for differential applications for the SCSI bus. LVD REG Low-voltage differential level is on the DIFF B pin; the terminator is in LVD mode. (Not brought out) 1 GND HS/GND NC REG pin should be bypassed to ground with a 4.7-µF capacitor. Single ended device has been detected on the DIFF B Pin; the terminator is in high impedance. (Not brought out) SE TERMPWR O 27, 28 14 6, 22 15 VIN 2.7-V to 5.25-V supply. TERMPWR should be bypassed to ground with a 4.7-µF capacitor. Signal ground This are for power dissipation and must be tied to ground and a large area of copper on 2 sided boards or to the Ground plane on multilayer boards with at least one feed through per pin with 10 mil etch going to the pins. No connect, other parts use this to disable the 1.3-V Diff sense drive. The circuit is wired with only one diff sense driver connected at each end. This function is not needed. www.ti.com 5 
 SLUS555 – FEBRUARY 2003 APPLICATION INFORMATION The diff sense line is driven by the terminator and monitored by the terminator DIFF B input pin. DIFF B has a digital filter and a 100-ms to 300-ms delay before the mode of the terminator is changed to reflect the new DIFF B input level. A set of comparators that allow for ground shifts determine the bus status as any DIFF SENSE signal below 0.5 V is single ended, between 0.7 V and 1.9 V is LVD SCSI, and above 2.2 V is HVD SCSI. The UCC5519 is high-impedance in HVD SCSI bus mode. Layout is very critical for Ultra160 and Ultra320 systems. Multilayer boards need to adhere to the impedance 120-Ω standard, including connectors and feed-throughs. This is normally done on the outer layers with 4-mil etch and 4-mil spacing between the runs within a pair, and a minimum of 8-mil spacing to the next pair. The spacing between the pairs reduces potential cross-talk. Beware of feed-throughs and through-hole connectors, each of which adds a lot of capacitance. The standard power and ground plane spacing yields about 1 pF to each plane; each feed-through adds about 2.5 pF to 3.5 pF. Enlarging the clearance holes on both power and ground planes can reduce the capacitance, and opening up the power and ground planes under the connector can reduce the capacitance for through-hole connector applications. Microstrip technology is normally too low of impedance and should not be used. It is designed for 50-Ω not 120-Ω differential systems. Capacitance balance is critical for Ultra160 and beyond; the balance capacitance is 0.5 pF per line with the balance between pairs is 2 pF. The components are designed with very tight balance, typically 0.1 pF between pins in a pair and 0.3 pF between pairs. Layout balance is critical, feed-throughs and etch length must be balanced, and preferably no feed-throughs would be used. Capacitance for devices should be measured in the typical application. Materials and components above and below the circuit board effect the capacitance. In 3.3-V Termpwr systems, the UCC3912 or UCC3918 should be used to replace the diode and fuse function. This reduces the voltage drop, allowing for the cable voltage drop for the terminators on the far end of the cable. 3.3-V battery systems have a 10% tolerance; the UCC3912 or UCC3918 has less than 150-mV drop under load, allowing for 150-mV drop in the cable system. All Texas Instrument LVD and multimode terminators are designed for 3.3-V systems, operating down to 2.7 V. In 5-V Termpwr systems the UCC3916, UCC3912 or UCC3918 can be used to replace the diode and fuse function. These reduce the voltage drop and protect the systems better than the diode and fuse or polyfuse. 6 www.ti.com 
 SLUS555 – FEBRUARY 2003 TYPICAL APPLICATION DIAGRAM UCC5519 Termpower UCC5519 L1+ 28 27 13 2 2 Termpower L1+ TRMPWR L1– 3 3 L1– L9+ 25 25 L9+ L9– 24 26 L9– CONTROL LINES (9) TRMPWR DISCNCT TRMPWR 28 TRMPWR 27 DISCNCT 13 DIFF SENSE DIFFS 16 REG DIFFB 1 17 4.7 µF 16 DIFFS DIFFB 20 k Ω 0.1 µF 1 27 4.7 µF 13 UCC5519 L1+ 2 2 L1+ L1– 3 3 L1– L9+ 25 25 L9+ L9– 26 26 L9– NC 16 16 NC TRMPWR DATA LINES (9) TRMPWR DISCNCT 4.7 µF 0.1 µF UCC5519 28 REG 17 20 k Ω TRMPWR 28 TRMPWR 27 DISCNCT 13 REG DIFFB DIFFB REG 1 17 17 1 4.7 µF 4.7 µF 4.7 µ F 0.001 µF 0.001 µF UCC5519 28 27 13 UCC5519 L1+ 2 2 L1+ L1– 3 3 L1– L9+ 25 25 L9+ L9– 26 26 L9– NC 16 16 TRMPWR DATA LINES (9) TRMPWR DISCNCT TRMPWR 28 TRMPWR 27 DISCNCT 13 NC REG DIFFB DIFFB REG 1 17 17 1 4.7 µF 4.7 µ F UDG–03015 www.ti.com 7 
 SLUS555 – FEBRUARY 2003 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°–ā8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 8 www.ti.com MECHANICAL DATA MHTS001D – JANUARY 1995 – REVISED MAY 1999 PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE 20 PINS SHOWN 0,30 0,19 0,65 20 0,10 M 11 Thermal Pad (See Note D) 4,50 4,30 0,15 NOM 6,60 6,20 Gage Plane 1 10 0,25 A 0°–ā8° 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 14 16 20 24 28 A MAX 5,10 5,10 6,60 7,90 9,80 A MIN 4,90 4,90 6,40 7,70 9,60 DIM 4073225/F 10/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2003, Texas Instruments Incorporated