UCD7230PWPR

UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 Digital Control Compatible Synchronous Buck Gate Drivers with Current Sense Conditioning Amplifier Check for Samples: UCD7230 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • Input from Digital Controller Sets Operating Frequency and Duty Cycle Up to 2-MHz Switching Frequency Dual Current Limit Protection with Independently Adjustable Thresholds Fast Current Sense Circuit with Adjustable Blanking Interval Prevents Catastrophic Current Levels Digital Output Current Limit Flag Low Offset, Gain of 48, Differential Current Sense Amplifier 3.3-V, 10-mA Internal Regulator Dual TrueDrive™ High-Current Drivers 10-ns Typical Rise/Fall Times with 2.2-nF Loads 4.5-V to 15.5-V Supply Voltage Range • • • Digitally-Controlled Synchronous-Buck Power Stages for Single and Multi-Phase Applications Especially Suited for Use with UCD91xx or UCD95xx Contollers High-Current Multi-Phase VRM/EVRD Regulators for Desktop, Server, Telecom and Notebook Processors Digitally-Controlled Synchronous-Buck Power Supplies Using mCs or the TMS320TM DSP Family DESCRIPTION The UCD7230 is part of the UCD7K family of digital control compatible drivers for applications utilizing digital control techniques or applications requiring fast local peak current limit protection. VOUT VIN CS BIAS VDD CS+ BST OUT1 SW PVDD OUT2 PGND + IO UVLO + IDLY 0.6 V POS BIAS 3V3 3V3 REG 48x NEG + Drive and Dead-Time ControlLogic (D;1-D) Enable Blank AGND AO ILOAD IN PWM Over Current I MAX ILIM CLF CLF SRE Current Limit Logic ILIM/10 IDLY SRE DLY UCD7230 + 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TrueDrive, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2010, Texas Instruments Incorporated UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com The UCD7230 is a MOSFET gate driver specifically designed for synchronous buck applications. It is ideally suited to provide the bridge between digital controllers such as the UCD91xx or the UCD95xx and the power stage. With cycle-by-cycle current limit protection, the UCD7230 device protects the power stage from faulty input signals or excessive load currents. The UCD7230 includes high-side and low-side gate drivers which utilize Texas Instrument’s TrueDrive™ output architecture. This architecture delivers rated current into the gate capacitance of a MOSFET during the Miller plateau region of the switching. Furthermore, the UCD7230 offers a low offset differential amplifier with a fixed gain of 48. This amplifier greatly simplifies the task of conditioning small current sense signals inherent in high efficiency buck converters. The UCD7230 includes a 3.3-V, 10-mA linear regulator to provide power to digital controllers such as the UCD91xx. The UCD7230 is compatible with standard 3.3-V I/O ports of the UCD91xx, the TMS320TM family DSPs, mCs, or ASICs. The UCD7230 is offered in PowerPAD™ HTSSOP or space-saving QFN packages. Package pin out has been carefully designed for optimal board layout SIMPLIFIED APPLICATION DIAGRAMS VIN UCD7230 UCD9112 ADC3 2 RB0 DPWMA0 1 VDD CS+ 20 2 SRE CSBIAS 19 3 SW 18 AD33 4 3V3 AVSS VD25 2 IN 2 VOUT OUT1 17 5 AGND BST 16 6 DLY PVDD 15 7 ILIM OUT2 14 8 CLF PGND 13 RPOS GSENSE 1 EAP VOUT DPWMB0 RB1/TMRI1 9 EAM I0 NEG 12 RNEG 1 GSENSE ADC2 10 A0 POS 11 RST COMMUNICATION (Programming& StatusReporting) 2 Figure 1. Single-Phase Synchronous Buck Converter using UCD9112 and one UCD7230 2 Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): UCD7230 UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 VIN UCD7230 RB0 1 VDD UCD9112 2 RB0 ADC3 2 SRE DPWMA0 CS+ 20 CSBIAS 19 3 IN 2 SW 18 AD33 4 3V3 AVSS 5 VD25 AGND 6 DLY 2 OUT1 17 VOUT RPOS1 BST 16 GSENSE PVDD 15 1 DPWMB0 ILIM OUT2 14 8 CLF PGND 13 7 EAP VOUT RB1/TMRI1 RNEG1 9 EAM NEG 12 I0 1 GSENSE ADC2 POS 11 10 A0 RST UCD7230 1 VDD 2 2 SRE RB0 DPWMA1 3 CS+ 20 CSBIAS 19 IN 2 SW 18 COMMUNICATION (Programming & Status Reporting) 4 3V3 5 AGND OUT1 17 6 DLY PVDD 15 DPWMB1 7 ILIM OUT2 14 RB3/TMRI0 8 CLF PGND 13 2 RPOS2 BST 16 RNEG2 9 I0 10 A0 ADC5 NEG 12 1 POS 11 2 Figure 2. Multi-Phase Synchronous Buck Converter using UCD9112 and two UCD7230 3 Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): UCD7230 UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com 3V3 17 16 15 SW UCD7230 (QFN RGW) (5x5, 0.65) 3 ILIM 4 14 OUT1 13 BST 12 PVDD 5 6 7 8 9 10 A0 POS NEG PGND 11 OUT2 I0 CLF 18 1 AGND 2 DLY CSBIAS 19 VDD 20 CS+ IN SRE CONNECTION DIAGRAMS ORDERING INFORMATION (1) TEMPERATURE RANGE -40°C to + 125°C (1) (2) (2) PACKAGED DEVICES PowerPAD™ HTSSOP-20 (PWP) QFN-20 (RGW) UCD7230PWP UCD7230RGW These products are packaged in Pb-Free and green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255-260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. QFN-20 (RGW) package is available taped and reeled. Add T suffix to device type (e.g. UCD7230RGW) to order quantities of 1,000 devices per reel. 4 Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): UCD7230 UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER VDD CONDITION 16 Supply voltage BST IDD Supply current VO Output gate drive voltage VALUE SW + 16 Quiescent 20 Switching, TA = 25°C, VDD = 12 V 200 OUT1, BST OUT2 -1 V to 36 -1 V to VDD+0.3 IOUT(sink) OUT1 4.0 IOUT(source) OUT1 -2.0 OUT2 4.0 IOUT(sink) Output gate drive current IOUT(source) OUT2 Analog inputs -1 to 20 CS+ -0.3 to 20 CSBIAS -0.3 to 16 POS, NEG -0.3 to 5.6 ILIM, DLY, I0 -0.3 to 3.6 Analog output A0 -0.3 to 3.6 Digital I/O’s IN, SRE, CLF -0.3 to 3.6 Power dissipation 2.67 TA = 25°C (QFN-20 package) TJ Junction operating temperature -55 to 150 Tstg Storage temperature -65 to 150 HBM CDM ESD rating Human body model 2000 Charged device model 500 Lead temperature (soldering, 10 sec) (1) V mA VV A -4.0 SW TA = 25°C (PWP-20 package) UNIT 300 V W °C V °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult company packaging information for thermal limitations and considerations of packages. 5 Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): UCD7230 UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS VDD = PVDD = 12 V, 4.7-mF from VDD to AGND, 1 mF from PVDD to PGND, 0.1 mF from CSBIAS to AGND, 0.22 mF from BST to SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 500 700 mA 5 8 mA SUPPLY Supply current, off VDD = 4.2 V Supply current Outputs not switching IN = LOW LOW-VOLTAGE UNDER-VOLTAGE LOCKOUT VDD UVLO ON VDD rising 4.25 4.50 4.75 VDD UVLO OFF VDD falling 4.00 4.25 4.50 100 250 400 3.267 3.3 3.333 3.234 3.3 3.366 VDD UVLO hysteresis V mV REFERENCE / EXTERNAL BIAS SUPPLY 3V3 initial set point TA = 25°C 3V3 over temperature 3V3 load regulation ILOAD = 1 mA to 10 mA, VDD = 5V 1 7 3V3 line regulation VDD = 4.75 V to 12 V, ILOAD = 10 mA 3 10 Short circuit current VDD = 4.75 V to 12 V 11 20 3V3 OK threshold, ON 3.3 V rising 2.8 3 3.2 3V3 OK threshold, OFF 3.3 V falling 2.6 2.8 3.0 V mV mA V INPUT SIGNAL (IN) INHigh Positive-going input threshold voltage 1.6 1.9 2.2 INLow Negative-going input threshold voltage 1.0 1.3 1.6 INHigh – INLow Input voltage hysteresis 0.4 0.6 0.8 Input resistance to AGND 50 100 150 Frequency ceiling 2 V kΩ MHz CURRENT LIMIT (ILIM) ILIM internal voltage setpoint ILIM=OPEN ILIM input impedance CLF output high level ILOAD = 4 mA CLF output low level ILOAD = 4 mA Propagation delay from IN to reset CLF 2nd IN rising to CLF falling after a current limit event 0.47 0.50 0.53 V 20 42 65 kΩ 2.7 0.6 15 35 V ns CURRENT SENSE COMPARATOR (OUTPUT SENSE) CS threshold (POS - NEG) (1) ILIM = open 40 50 60 ILIM = 3.3 V 80 100 120 ILIM = 0.75 V 60 75 90 ILIM = 0.25 V 15 25 35 Propagation delay from POS to OUT1 falling (1) ILIM = open, CS = threshold + 60 mV 90 Propagation delay from POS to CLF (1) ILIM = open, CS = threshold + 60 mV 100 mV ns As designed and characterized. Not 100% tested in production. 6 Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): UCD7230 UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS (continued) VDD = PVDD = 12 V, 4.7-mF from VDD to AGND, 1 mF from PVDD to PGND, 0.1 mF from CSBIAS to AGND, 0.22 mF from BST to SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX RDLY = 24.3 kΩ (CSBIAS-CS+) 170 235 300 RDLY = 49.9 kΩ (CSBIAS-CS+) 90 114 140 UNIT CURRENT SENSE COMPARATOR (INPUT SENSE) CS threshold CS blanking time (2) RDLY = 24.3 kΩ , IN rising to OUT1, IN falling to OUT2, VDD = 6 V 120 RDLY = 49.9 kΩ , IN rising to OUT1, IN falling to OUT2, VDD = 6 V 230 RDELAY range (2) Propagation delay from CS+ to OUT1 (2) Propagation delay from CS+ to CLF (2) mV ns 24.3 50.0 100.0 kΩ 80 CS = threshold + 60mV ns 70 CURRENT SENSE AMP VOO Output offset voltage I0 = OPEN; POS = NEG = 1.25 V; measure AO - IO Closed loop dc gain -100 0 100 mV I0 = FLOAT; VPOS = 1.26 V; VNEG = 1.25 V, RPOS = RNEG = 0 46 48 50 V/V Input impedance POS = 1.25 V, NEG = 1.29 V,R = (POS - NEG) / (IPOS - INEG) 5.5 8.3 12 kΩ VCM Input Common Mode Voltage Range VCM(max) is limited to (VDD-1.2V), RPOS = 0 5.6 V A0_Vol Minimum Output Voltage VPOS = 1.2 V; VNEG = 1.3 V; A0_ISINK = 250 mA A0_Voh Maximum Output Voltage VPOS =1.3 V; VNEG = 1.2 V; A0_ ISOURCE = 500 mA Input Bias Current, POS or NEG I0 = FLOAT; VPOS = VNEG = 0.8 V to 5.0 V, RPOS = RNEG = 0 0 0.15 0.3 3.1 3.5 V 3 -2 30 mA ZERO CURRENT REFERENCE (IO) IO (2) Reference voltage Measured at I0 0.54 0.6 0.66 V Input transition voltage With respect to IO reference 10 60 120 mV Output impedance IZERO = 0.6 V 10 15 21 kΩ As designed and characterized. Not 100% tested in production. 7 Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): UCD7230 UCD7230 SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = PVDD = 12 V, 4.7-mF from VDD to AGND, 1 mF from PVDD to PGND, 0.1 mF from CSBIAS to AGND, 0.22 mF from BST to SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW-SIDE OUTPUT DRIVER (OUT2) Source current (3) Sink current (3) Source current (3) Sink current VDD = 12 V, IN = high, OUT2 = 5 V 2.2 VDD = 12 V, IN = low, OUT2 = 5 V 3.5 VDD = 4.75 V, IN = high, OUT2 = 0 1.6 VDD = 4.75 V, IN = low, OUT2 = 4.75 V (3) A 2 Rise time (3) CLOAD = 2.2 nF, VDD = 12 V 15 Fall time (3) CLOAD = 2.2 nF, VDD = 12 V 15 Output with VDD