UCD7232RTJR

UCD7232 SLUSAH3 – MAY 2011 www.ti.com Digital Control Compatible Synchronous-Buck Gate Driver With Current Sense and Fault Protection Check for Samples: UCD7232 FEATURES 1 • • • • • • • • • • • • • • Dual High Current Drivers. Full Compatibility with TI Fusion Digital Power Supply Controllers, such as UCD91xx and UCD92xx Families Operational to 2 MHz Switching Frequency High-Side FET and Output Current Limit Protection with Independently Adjustable Thresholds Fast High-Side Overcurrent Sense Circuit with Fault Flag Output – Prevents Catastrophic Current Levels on a Cycle-by-Cycle Basis Differential High-Gain Current Sense Amplifier Voltage Proportional to Load Current Monitor Output Wide Input Voltage Range: 4.7 V to 15 V Operation to 2.2 V Input Supported with an External 4.5-6.5 V Bias Supply Onboard Regulated Supplies for Gate Drive and Internal Circuits Integrated Thermal Shutdown Selectable Operation Modes: – PWM plus Synchronous Rectifier Enable (SRE) with Automatic Dead-Time Control – Direct High-Gate and Low-Gate Inputs for Direct FET Control 3-State PWM Input for Power Stage Shutdown UVLO Housekeeping Circuit Rated from –40°C to +125°C Junction Temperature APPLICATIONS • • Digitally-Controlled Synchronous-Buck Power Stages for Single- and Multi-Phase Applications Digitally-Controlled Power Modules DESCRIPTION The UCD7232 high current driver is specifically designed for digitally-controlled, point-of-load, synchronous buck switching power supplies. Two driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven by an internally regulated VGG supply. The internal VGG regulator can be disabled to permit the user to supply their own gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 to 15 V. Internal under voltage lockout (UVLO) logic insures VGG is good before allowing chip operation. A drive logic block allows operation in one of two modes selected by the SRE Mode pin. In Synchronous Mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is automatically adjusted to prevent cross conduction. The Synchronous Rectifier Enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low. In Independent Mode, the PWM and SRE pins control the high-side and low-side gates directly. No anti-cross-conduction logic is used in this mode. On-board comparators monitor the voltage across the high side switch and the voltage across an external current sense element to safeguard the power stage from sudden high current loads. Blanking delay is set for the high side comparator by a single resistor in order to avoid false reports coincident with switching edge noise. In the event of a high-side fault or an over-current fault, the high-side FET turned off and the Fault Flag (FLT) is asserted to alert the digital controller. The fault thresholds are independently set by the HS Sense and ILIM pins. Output current is measured and monitored by a precision, high gain, switched capacitor differential amplifier that processes the voltage present across an external current sense element. The amplified signal is available for use by the digital controller on the IMON pin. The current sense amplifier has output offset of 0.5 V so that both positive (sourcing) and negative (sinking) current can be sensed. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated UCD7232 SLUSAH3 – MAY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) An on-chip temperature sense monitors the die temperature. If it exceeds approximately 165°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. The temperature fault automatically clears when the die temperatures falls by approximately 20°. FUNCTIONAL BLOCK DIAGRAM 9 VGG DIS 4 3 2 Vin HS Sense Bias + VGG Generator 13 10 16 BP3 UCD7232 PWM BST SRE 1 18 UVLO SRE Mode HS Gate 19 Digital Control FLT HS Fault SW RDLY 11 TSD VGG OC Fault Blanking Control LS Gate 20 17 15 Thermal Sense PGND 5 ILIM CSP 0.5 V 6 IMON G = 50 12 AGND PP CSN 14 8 7 PAD Figure 1. UCD7232 Block Diagram 2 Copyright © 2011, Texas Instruments Incorporated UCD7232 SLUSAH3 – MAY 2011 www.ti.com SIMPLIFIED APPLICATION DIAGRAM Vin 16 Vin 10 PWM HS Sense 1 From Controller BST 18 4 SRE HS Gate 19 2 FLT To Controller Vout SW 20 6 IMON UCD7232 VGG 17 3 SRE Mode LS Gate 15 9 BP3 GND PGND 14 5 ILIM 11 RDLY CSP 8 13 VGG DIS AGND 12 CSN 7 PAD PP Figure 2. Typical Synchronous Buck Power Stage SW HS Gate BST VG G Vin CONNECTION DIAGRAM 20 19 18 17 16 HS Sense 1 15 LS Gate FLT 2 14 PGND UCD7232 (QFN - RTJ) (4x4, 0.50) SRE Mode 3 13 VGG DIS 6 7 8 9 10 BP3 PWM 11 RDLY CSP ILIM 5 CSN 12 AGND IMO N SRE 4 ORDERING INFORMATION TEMPERATURE RANGE PACKAGE –40°C to +125°C Plastic QFN-20 (RTJ) Copyright © 2011, Texas Instruments Incorporated TAPE AND REEL QTY PART NUMBER 250 UCD7232RTJT 2500 UCD7232RTJR 3 UCD7232 SLUSAH3 – MAY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER Gate drive supply voltage Output gate drive voltage Switch node voltage MIN MAX –0.3 16 VBST DC –0.3 23 VBST Pulse (VSWat 20V < 400ns) –0.3 27 VBST Pulse (VSWat 22V < 64ns) –0.3 29 VBST Pulse (VSWat 30V < 16ns) –0.3 37 VGG (Externally supplied) –0.3 7 Supply voltage, VIN Bootstrap voltage VALUE HS Gate – SW –0.3 7 LS Gate PGND – 0.3 VGG+0.3 VSW DC –1 16 VSW Pulse < 400 ns, E = 20 µJ –2 20 VSW Pulse < 64 ns –5 22 UNIT V V V V V VSW Pulse < 16 ns –10 30 CSP, CSN, RDLY –0.3 5.6 ILIM –0.3 3.6 HS Sense –0.3 16 PWM, SRE, SRE Mode –0.3 5.6 VGG DIS –0.3 3.6 Analog outputs IMON –0.3 3.6 V Digital outputs FLT –0.3 3.6 V Analog inputs Digital inputs ESD Rating Human body model 2000 Charged device model 500 V V V Operating ambient temperature, TA –40 125 °C Operating junction temperature, TJ –40 150 °C Storage temperature, TSTG –65 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to AGND. Currents are positive into, negative out of the specified terminal. Consult company packaging information for thermal limitations and considerations of packages. THERMAL INFORMATION THERMAL METRIC (1) UCD7232 RTJ (20 PINS) θJA Junction-to-ambient thermal resistance 38.2 θJCtop Junction-to-case (top) thermal resistance 34.4 θJB Junction-to-board thermal resistance 15.7 ψJT Junction-to-top characterization parameter 0.4 ψJB Junction-to-board characterization parameter 15.7 θJCbot Junction-to-case (bottom) thermal resistance 5.9 (1) 4 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2011, Texas Instruments Incorporated UCD7232 SLUSAH3 – MAY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VIN Power Input Voltage (Internally generated VGG) 4.7 12 15 V VIN Power Input Voltage (Externally supplied VGG) 2.2 – 15 V VGG Externally supplied gate drive voltage 4.6 6 6.5 V TJ Operating junction temperature range –40 – 125 °C ELECTRICAL CHARACTERISTICS VIN = 12V, 4.7 µF from VGG to PGND, 1 µF from BP3 to AGND, 0.22 µF from BST to SW, TA = TJ = –40°C to 125°C, RDLY = 8.06kΩ, SRE Mode = 3.3V, VGG DIS tied to AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY SECTION Supply current Outputs not switching, VIN = 5 V, PWM = LOW 8 10 mA Supply current Outputs not switching, VIN = 15 V, PWM = LOW 8 10 mA 4.4 4.6 V GATE DRIVE UNDER-VOLTAGE LOCKOUT VGG UVLO OFF VGG rising VGG UVLO ON VGG falling VGG UVLO hysteresis 4.1 4.3 V 80 mV VGG SUPPLY GENERATOR VGG VIN ≥ 7 V, I_VGG ≤ 100 mA 5 VIN = 12 V, I_VGG ≤ 80 mA 5.6 V 6.2 VIN = 4.75 V, I_VGG ≤ 100 mA Dropout 6.8 V 350 mV DIGITAL INPUT SIGNALS (PWM, SRE) VIH_PWM Positive-going input threshold voltage VIL_PWM Negative-going input threshold voltage PWM Input voltage hysteresis, (VIH – VIL) VIH_SRE Positive-going input threshold voltage VIL_SRE Negative-going input threshold voltage SRE Input voltage hysteresis, (VIH – VIL) 1.8 0.80 Input current ISRE 1.5 0.9 (1) tHLD_R 3-state recovery time tmin PWM minimum pulse to force HS gate pulse (1) PWM frequency (1) (1) V 1.7 V V 0.45 V µA 70 –63 VSRE = 5 V 190 µA 12 –330 VSRE = 0 V 3-state hold-off time V 1.00 VPWM = 0 V VSRE = 3.3 V tHLD_R V 140 VPWM = 3.3 V Input current 0.90 0.90 VPWM = 5 V IPWM 2 VPWM transition from 0 V to 1.65 V, Time until VLS Gate falls to 0 V 450 600 750 ns VPWM transition from 1.65 V to 0 V, Time until VLS Gate rises to VGG 150 330 500 ns CL = 3 nF at HS gate, VPWM = 3.3 V 50 ns QgHS + QgLS < 46 nC, VGG = 6.4 V 2 MHz OUTPUT CURRENT LIMIT (ILIM) ILIM Input impedance (1) 250 ILIM set point range (1) 0.5 kΩ 3 V FLT output high level ILOAD = –2 mA FLT output low level (1) ILOAD = 2 mA 0.1 0.6 V tFAULT_HS Fault detection time. Delay until HS Gate falling. (1) V(ILIM) = 1.50 V, (CSP – CSN) = 20 mV, CSN = 1.80 V 100 150 ns tFAULT_LS Fault detection time. Delay until LS Gate rising. (1) V(ILIM) = 1.50 V, (CSP – CSN) = 20 mV, CSN = 1.80 V 150 200 ns (1) 2.7 3.3 V As designed and characterized. Not 100% tested in production. Copyright © 2011, Texas Instruments Incorporated 5 UCD7232 SLUSAH3 – MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, 4.7 µF from VGG to PGND, 1 µF from BP3 to AGND, 0.22 µF from BST to SW, TA = TJ = –40°C to 125°C, RDLY = 8.06kΩ, SRE Mode = 3.3V, VGG DIS tied to AGND (unless otherwise noted) PARAMETER tFAULT_FLT TYP MAX UNIT Fault detection time. Delay until FLT asserted (2) V(ILIM) = 1.50 V, (CSP – CSN) = 20 mV, CSN = 1.80 V TEST CONDITIONS MIN 85 170 ns Propagation delay from PWM to reset FLT (2) PWM falling to FLT falling after a current limit event is cleared. PWM pulse width ≥100 ns. 85 200 ns CURRENT SENSE BLANKING (RDLY, HS Sense) IRDLY RDLY source current 8.06 kΩ resistor from RDLY to AGND RDLY resistance range (2) 80 90 100 µA 7.5 8.06 10 kΩ 110 125 140 ns tBLANK HS blanking time RDLY = 8.06 kΩ. From SW rising to HS fault comparator enabled IHS Sense HS Sense sink current RHS 100 µA tHSFAULT_HS HS fault detection time. Delay after tBLANK until HS Gate falling (2) RDLY = 8.06 kΩ, RHS Sense = 2 kΩ to VIN, VIN = 12 V, VIN – VSW = 220 mV 20 ns tHSFAULT_LS HS fault detection time. Delay after tBLANK until LS Gate falling (2) RDLY = 8.06 kΩ, RHS Sense = 2 kΩ to VIN, VIN = 12 V, VIN – VSW = 220 mV 30 ns Sense = 2. kΩ to VIN, VIN = 12 V CURRENT SENSE AMPLIFER (IMON, CSP, CSN) V(IMON) at no load CSP = CSN = 1.8 V Closed loop DC gain CSP – CSN = 10 mV; 0.5 V ≤ CSN ≤ 3.3 V Gain with 2.49k resistors in series with CSP, CSN VCM Input impedance (2) Differential, CSP – CSN Input common mode voltage range (2) VCM(max) is limited to (VGG – 1.2 V) 460 500 540 mV 48 50.2 52.4 V/V 45.6 47.8 49.9 V/V 100 –0.3 V(IMON)MIN CSP = 1.2 V; CSN = 1.3 V; I(IMON) = –250 µA V(IMON)MAX CSP = 1.3 V; CSN = 1.2 V; I(IMON) = 500 µA 3 Sampling Rate (2) kΩ 5.6 V 0.1 0.15 V 3.2 3.3 V 5 Msps VGG = 6.2 V, PWM = Low, LS Gate = 3 V 6 A VGG = 6.2 V, PWM = High, LS Gate = 3 V 6 A CL = 6 nF, VIN = 12 V, VGG = 6.2 V 30 ns CL = 6 nF, VIN = 12 V, VGG = 6.2 V 20 ns LOW-SIDE OUTPUT DRIVER (LS Gate) Peak Source Current (2) Peak Sink Current tRL Rise Time (2) tFL Fall Time (2) (2) Output with VGG 100MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can exceed twice VIN. Care must be taken to not allow the peak ringing amplitude to exceed twice the value of the input voltage, even if that voltage amplitude is within the Absolute Maximum rating limit for the pin. In many cases, a series resistor and capacitor snubber network connected from the switching node to PGND can be helpful in damping the ringing and decreasing the peak amplitude. It is recommended that provisions for snubber network components be provided during the layout of the printed circuit board. If testing reveals that the ringing amplitude at the SW pin exceeds twice VIN, then the snubber components need to be populated. BST The BST pin provides the drive voltage for the high-side FET. A bootstrap capacitor is connected from this pin to the SW node. Internally, a diode connects the BST pin to the VGG supply. In normal operation, when the high-side FET is off and the low-side FET is on, the SW node is pulled to ground and, thus, holds one side of the bootstrap capacitor at ground potential. The other side of the bootstrap capacitor is clamped by the internal diode to VGG. The voltage across the bootstrap capacitor at this point is the magnitude of the gate drive voltage available to switch-on the high-side FET. The bootstrap capacitor should be a low ESR ceramic type, with a recommended minimum value of 0.22µF. A minimum voltage rating of 16V or higher is recommended. HS GATE The HS Gate signal directly drives the gate of the high-side power FET. It provides high current drive to charge the gate capacitance of the FET rapidly to insure that it makes the transition from off to on as quickly as possible to minimize switching losses. When commanded on, the HS Gate is driven to the BST pin potential. As the FET begins to turn on, the SW will quickly rise to the VIN potential. This voltage swing is coupled by the bootstrap capacitor to the BST pin. The net result is that the BST pin voltage, and thus the HS Gate voltage, is always equal to VSW + VGG. As the FET gate charges, the current return path for the driver is provided by the SW pin. When the HS Gate is commanded off, the driver pulls the pin to the SW potential. As the FET turns off, the SW pin will swing quickly to slightly below ground. Once again, this voltage swing is coupled to the BST pin by the bootstrap cap. The HS Gate circuitry is referenced to the SW pin and floats with the SW signal swing. The circuitry loop from the HS Gate pin to the gate of the FET and from the source of the high-side FET to the SW pin should kept as small and tight as possible to limit stray inductance. Likewise, the loop from the BST pin to the bootstrap capacitor and back to the SW pin should be kept small and tight. 10 Copyright © 2011, Texas Instruments Incorporated UCD7232 SLUSAH3 – MAY 2011 www.ti.com LS GATE The LS Gate signal directly drives the gate of the low-side power FET. It provides high current drive to quickly charge the gate capacitance of the FET, which is often considerably larger than the high-side FET. When commanded on, the LS Gate is driven to the VGG pin potential. The current return path for the driver is provided by the PGND pin. When commanded off, the LS Gate pin is driven to the PGND potential. The traces from the LS Gate and the PGND pins to the low-side FET gate and source pins should be short and wide to minimize parasitic inductance and resistance. CSP, CSN These pins are the input to the differential current sense amplifier. The Current Sense Positive (CSP) pin connects to the non-inverting input, the Current Sense Negative (CSN) connects to the inverting input. This amplifier provides the means to monitor and measure the output current of the power stage. The circuitry can be used with a discrete, low value, series current sense resistor, or can make use of the popular inductor DCR sense method. The DCR method is illustrated in Figure 3. A series resistor and capacitor network is added across the buck stage power inductor. It can be shown that when the value of L/DCR is equal to RC, then the voltage developed across the capacitor, C, is a replica of the voltage waveform the ideal current would induce in the dc resistance (DCR) of the inductor. This method does not detect changes in current due to changes in inductance value caused by saturation effects. The value used for C should be in the 0.1µF to 2.2µF range. This keeps the impedance of the sense network low, which reduces its susceptibility to noise pickup from the switching node. The trace lengths of the CSP and CSN signals should be kept short and parallel. To aid in rejection of high frequency common-mode noise, a series 2.49k resistor should be added to both the CSP and CSN signal paths, with the resistors being placed close to the pins at the package. This small amount of additional resistance slightly lowers the current sense gain. Power inductors are selected for the lowest possible DCR to minimize losses. Typical DCR values range from 0.5mΩ to 5mΩ. With a load current of 20A, the voltage presented across the CSP and CSN pins is only in the range of 10mV to 100mV. Keep in mind that this small differential signal is riding on a large common mode signal that is the dc output voltage. This makes the current sense signal challenging to process. L DCR SW Vout C R 2.49kW CSP 2.49kW CSN Figure 3. DCR Current Sense The UCD7232 uses switched capacitor technology to perform the differential to single-ended conversion of the sensed current signal. This technique offers excellent common mode rejection. The differential CSP-CSN signal is amplified by a factor of 97.8 and then a fixed 500mV pedestal voltage is added to the result. This signal is presented to the IMON pin. When using inductors with DCR values of 2mΩ or higher, it may be necessary to attenuate the input signal to prevent saturation of the current sense amplifier. This is easily accomplished through the addition of resistor R2 as shown in Figure 4. Copyright © 2011, Texas Instruments Incorporated 11 UCD7232 SLUSAH3 – MAY 2011 www.ti.com L DCR SW Vout C R1 R2 2.49 kW CSP 2.49 kW CSN Figure 4. Attenuating the DCR Sense Signal The amount of attenuation is equal to R2/(R1 + R2). The equivalent resistance value to use in the L/DCR = RC formula is the parallel combination of R1 and R2. Thus, when using the circuit of Figure 4, L/DCR = C × R1 × R2/(R1 + R2) (3) IMON The IMON signal is a voltage proportional to the output current delivered by the power stage. The voltage magnitude obeys the following equation when using the circuit of Figure 3. This equation takes into account the gain reduction caused by the series 2.49k resistors. V(IOUT) = 0.5 + 47.8 × DCR × ILOAD (4) If the calculated value of V(IMON) exceeds the range of the analog-to-digital converter (ADC) or, if used, the maximum fault comparator threshold limit of a controller monitoring this voltage, then the circuit of Figure 4 should be used. When using the circuit of Figure 4, the voltage on IMON obeys this modified equation: æ R2 ö V(IOUT ) = 0.5 + 47.8 ´ DCR ´ ILOAD ´ ç ÷ è R1 + R2 ø (5) In either case, the output voltage is 500mV at no load. Current that is sourced to the load causes the IMON voltage to rise above 500mV. Current that is forced into the power stage (sinking current) is considered “negative” current and will cause the IMON voltage to fall below 500mV. The usable dynamic range of the IMON signal is approximately 100mV to 3.1V. Keep in mind that this signal swing could exceed not just the maximum range of an analog to digital converter (ADC) that may be used to read or monitor the IMON signal, but also the maximum programmable limit for the fault OC threshold. For example, the UCD92xx family of digital controllers has maximum limit of 2.5V for the ADC converter and 2.0V for the fault OC threshold, even though the input pin can tolerate voltages up to 3.3V. The IMON voltage is internally fed to the non-inverting input of the output over-current fault comparator. Good practice dictates that the over-current threshold should be set at approximately 150% of the rated power stage output current plus one half of the peak-to-peak inductor ripple current. This mandates that the IMON signal should remain within its linear dynamic range at this threshold load current level. This requirement may force the use of the attenuation circuit of Figure 4. Note that the IMON voltage (that goes to the output over-current fault comparator) is held during the blanking interval set by the resistor on the RDLY pin. This means that the IMON pin will not reflect output current changes during the blanking interval, and that a fault will not be flagged until the blanking interval terminates. ILIM The ILIM pin feeds the inverting input of the output over-current fault comparator. The voltage applied to this pin sets the over-current fault threshold. When the voltage on the IMON pin exceeds the voltage on this pin, a fault is flagged. The voltage on this pin can be set by a voltage divider, a DAC, or by a filtered PWM output. The usable voltage range of the ILIM pin is approximately 0.6V to 3.1V. This represents the linear range of the IMON signal for sourced output current. When using a voltage divider to set the threshold, a (0.01µF) capacitor to BP3 can be added to improve noise immunity. 12 Copyright © 2011, Texas Instruments Incorporated UCD7232 www.ti.com SLUSAH3 – MAY 2011 RDLY The RDLY pin sets the blanking time of the high-side fault detection comparator. A resistor to AGND sets the blanking time according to the following formula, where tBLANK is in nanoseconds and RDLY is in kΩ. Values of RDLY of greater than 25kΩ should not be used. t - 33 RDLY = BLANK 11.413 (6) To calculate the nominal blanking time for a given value of resistance, use the formula below. tBLANK = 11.413 × RDLY + 33 (7) The blanking interval begins on the rising edge of SW. During the blanking time the high-side fault comparator is held off. A high-side fault is flagged when the voltage drop across the high-side FET exceeds the threshold set by the HS Sense pin. Blanking is required because the high amplitude ringing that occurs on the rising edge of SW would otherwise cause false triggering of the fault comparator. The required amount of blanking time is a function of the high-side FET, the PCB layout, and whether or not a snubber network is being used. A value of 125ns is a typical starting point. An RDLY of 8.06kΩ will provide 125ns of blanking. The blanking interval should be kept as short as possible, consistent with reliable fault detection. The blanking interval sets the minimum duty cycle pulse width where high-side fault detection is possible. When the duty cycle of the PWM pulses are narrower than the blanking time, the high-side fault detection comparator is held off for the entire on-time and is, therefore, blind to any high-side faults. Internally, the RDLY pin is fed by a 90µA current source. When using the default value of 8.06kΩ, the voltage observed on the RDLY pin will be approximately 725mV. HS SENSE A resistor from the HS Sense pin to the drain of the high-side FET sets the high-side fault detection threshold. When the high-side FET is on, the current flow in the FET produces a voltage drop across the device. The magnitude of this voltage is equal to the RDS(ON) times the current through the FET. An absolute maximum current level can be set during the design stage and the resultant voltage drop across the FET can be calculated. This maximum voltage drop, ΔVMAX, sets the high-side fault threshold. Internally, a high speed comparator monitors the voltage between the SW pin and the HS Sense pin when the high-side FET is on. Whenever the voltage on the SW pin is lower than the voltage on the HS Sense pin, a fault is flagged. To prevent false tripping during the ringing that accompanies the rising edge of SW, the output of the comparator is held off (blanked) for a time interval set by the RDLY pin. The voltage on the HS Sense pin is set by a resistor connected from the pin to the high-side FET drain. The HS Sense resistor value is calculated from the following formula, where ΔVMAX is in mV, and RHS Sense is in kilohms. RHS Sense = ΔVMAX / 100 (8) For example, if ΔVMAX is 100mV, then RHS Sense is 1kΩ. The equation can be restated as follows, with RHS Sense in kilohms, RDS(ON) in milliohms, and IMAX in amps: RHS Sense = RDS(ON)HOT × IMAX) / 100 (9) The value of IMAX should be set to approximately 150% of the expected maximum steady-state current. This allows some headroom to avoid nuisance fault events due to transient load currents and the inductor ripple current. Also, keep in mind that the RDS(ON) of a FET has a large positive temperature coefficient of approximately 4000ppm/°C. The junction temperature of the FET will be elevated when operating at currents near the IMAX threshold. In the equation above, use a value of RDS(ON)HOT that is approximately 140% of its typical room temperature value. When using the internal VGG gate drive supply, the FET, when turned on, is driven to a VGS enhancement voltage of approximately 6V. Most FET data sheets provide RDS(ON) values for VGS values of 4.5V and 10V. Do not use the VGS = 10V value for the room temperature RDS(ON) value. Some manufacturers provide a graph of RDS(ON) vs VGS. If provided, use the VGS = 6V value for the room temperature RDS(ON) value. A 100µA current sink pulls current through RHS Sense. This sets up a reference voltage drop equal to ΔVMAX. It is important to connect the far end of the RHS Sense resistor directly to the drain of the high-side FET. This should be made with a separate, non-current-carrying trace. This insures that only the RDS(ON) of the FET influences the fault threshold and not the resistance of the pc board traces. Copyright © 2011, Texas Instruments Incorporated 13 UCD7232 SLUSAH3 – MAY 2011 www.ti.com FLT The Fault Flag (FLT) is a digital output pin that is asserted when a significant fault is detected. It is meant to alert the host controller to an event that has interrupted power conversion. The FLT pin is held low in normal operation. When a fault is detected it is asserted high (3.3V). There are four events that can trigger the FLT signal: output over-current, high-side over-current, UVLO and thermal shutdown. The operation of the device during fault conditions is described in the Fault Behavior section. When asserted in response to an over-current fault, the FLT signal is reset low upon the falling edge of a subsequent PWM pulse, provided no faults are detected during the on-time of the pulse. If the fault is still present, the flag will remain asserted. When asserted in response to an UVLO or thermal shutdown event, the FLT pin will automatically de-assert itself when the UVLO or thermal event has passed. If the on-time of the PWM pulse is less than 100ns, then more than one pulse may be required to reset the flag. BP3 The BP3 pin provides a connection point for a bypass capacitor that quiets the internal 3.3V voltage rail. Connect a 1µF (or greater) ceramic capacitor from this pin to analog ground. Do not draw current from this pin. It is not intended to be a significant source of 3.3V. It can, however, be used to as a source of 3.3V for an ILIM voltage divider and a tie point for the SRE Mode pin. Current draw should be limited to 100µA or less. FAULT BEHAVIOR When faults are detected, the device reacts immediately to minimize power dissipation in the FETs and protect the system. The type of fault influences the behavior of the gate drive signals. When a thermal shutdown fault occurs, both HS Gate and LS Gate are immediately forced low. They will stay low, regardless of the state of PWM and SRE, for the duration of the thermal shutdown. A UVLO fault occurs when the voltage on the VGG pin is less than the UVLO threshold. During this time both the HS Gate and LS Gate are driven low, regardless of the state of PWM and SRE. The fault is automatically cleared when the VGG voltage rises above the UVLO threshold. When either a high-side fault or an output over-current fault is detected, the FLT pin is asserted high, and both gate signals are immediately pulled low. During a high-side fault, a high-side gate pulse will be issued with each incoming PWM pulse. If the fault is still present, the HS Gate signal will again be truncated. This behavior repeats on a cycle-by-cycle basis until the fault is gone or the PWM input is held low. This behavior is illustrated in Figure 5. PWM Fault Detected FLT HS Gate LS Gate Figure 5. High-Side Over-Current Fault Response When a high-side fault and output over-current fault are detected concurrently, then both FET drives are immediately turned off and held off. If the output over-current fault is still present at the next PWM rising edge, then no HS Gate pulse will be issued and both gates will continue to be held off. Unlike the high-side fault detection circuitry, the output over-current fault circuitry is not reset on a cycle-by-cycle basis. The output current must fall below the over-current threshold before switching will resume. 14 Copyright © 2011, Texas Instruments Incorporated UCD7232 SLUSAH3 – MAY 2011 www.ti.com FLT RESET With the exception of a UVLO fault or a thermal shutdown fault, the FLT flag, once asserted, is cleared by subsequent PWM pulses. The FLT flag will be cleared on the falling edge of the next PWM pulse, provided a fault condition is not asserted during the entire on-time of the PWM pulse. If a fault is present or detected during the on-time interval, the FLT pin will remain asserted. This behavior is illustrated in Figure 6. PWM Fault Detected Internal Fault Signal FLT Fault Still Present No fault present during entire PWM high interval . FLT reset on PWM falling edge Figure 6. FLT Reset Sequence Whenever the voltage on the VGG pin is below the UVLO falling threshold, as at the time of initial power-up, for example, the FLT pin will be asserted. When the voltage on the VGG pin rises above the UVLO rising threshold, the FLT pin will be cleared automatically. This permits the FLT pin to be used as a “Power Not Good” signal at initial power-up to signify that there is insufficient gate drive voltage available to permit proper power conversion. When FLT goes low, it is an indication of “Gate Drive Power Good” and power conversion can commence. After initial power-up, the assertion of the FLT flag should be interpreted that power conversion has stopped or has been limited by a fault condition. THERMAL SHUTDOWN If the junction temperature exceeds approximately 165°C, the device will enter thermal shutdown. This will assert the FLT pin and both gate drivers will be turned off. When the junction temperature cools by approximately 20°C, the device will exit thermal shutdown. The FLT flag is reset upon exiting thermal shutdown. Gate driver temperature will be strongly influenced by the switching frequency being used, the value of VIN and VGG, and the total capacitive load on the HS Gate and LS Gate pins. The driver junction temperature is not normally strongly affected by load current. However, a rise in the PCB substrate temperature due to load current induced power dissipation in nearby components will raise the junction temperature and contribute to a possible thermal shutdown event. Copyright © 2011, Texas Instruments Incorporated 15 UCD7232 SLUSAH3 – MAY 2011 www.ti.com APPLICATION INFORMATION EXAMPLE 20A POWER STAGE A partial schematic of a 20A power conversion stage designed for 500kHz operation is shown in Figure 7. Vin (6V - 14V) C11 0.1mF 16 Vin HS Sense 1 10 PWM From controller BST 18 4 SRE HS Gate 19 2 FLT To controller 6 I MON SW 20 U1 UCD7232 VGG 17 3 SRE Mode 9 BP3 R5 10.0kW C12 1mF 5 ILIM C3 0.22mF R9 0W (Opt ) Q1 CSD16322Q5 L1 1mH, 1.2mW R11 1W Vout D1 B0540W C4 4.7uF C5 PGND 14 11 RDLY CSP 8 8.06kW 13 VGGDIS CSN 7 AGND PAD 12 PP R8 3.01W 0.5W R10 0 W (Opt) R3 2.49kW R1 768W R2 2200pF LS Gate 15 R6 31.6kW R7 C1 22mF C2 22mF R12 1.65kW Opt C7 C8 C9 47mF 47mF 330mF GND Q2 CSD16401Q5 C6 1mF R4 2.49kW Figure 7. Example 20A Power Stage This power stage has been designed to operate with a nominal input voltage of 12V. It will perform well with input voltages from 6V to 14V. The output voltage range is assumed to be 3.3V or lower. It has been configured to use the internal VGG supply and operate strictly in synchronous mode. The controller and voltage feedback components are not shown. This design works well with any of the UCD92xx family of Digital Power Controllers. The first step in designing the power stage is selecting a nominal operating frequency. Lower switching frequencies will reduce FET switching losses and driver gate currents, but will require higher inductor values to keep inductor ripple current within reasonable values. Higher switching frequencies allow for smaller inductor values, which likely reduces their physical size and DCR, but higher FET switching losses and gate drive power may offset the efficiency gains achieved from reduced inductor DCR. 500kHz is a good starting point for power stages in the 15A to 25A range. INDUCTOR SELECTION Once a switching frequency has been selected, an appropriate inductance value can now be selected. Ripple current and saturation current are the two key parameters that drive inductor value selection. Ripple current is the ac variation of the current through the inductor. It is superimposed on the average dc (load) current flowing through the inductor. High values of ripple current cause increased core losses in the inductor, and require more low ESR capacitance to keep the output ripple voltage to acceptable levels. Limit the inductor ripple current to approximately 30% of the rated dc load current. The peak-to-peak ripple current in an inductor determined by the voltage across the inductor, the time duration of that applied voltage, and the value of the inductor. ΔIPP = VL × Δt / L (10) In a switching regulator, this equation can be rewritten to use the duty-cycle and switching frequency of the high-side FET to calculate the ripple current. ΔIPP = [(VIN – VOUT) × VOUT] / (VIN × FSW × L) 16 (11) Copyright © 2011, Texas Instruments Incorporated UCD7232 www.ti.com SLUSAH3 – MAY 2011 For a synchronous buck regulator, the ripple current is highest at 50% duty cycle, or when Vout is one half of Vin. At higher or lower duty cycles, the ripple current decreases. For this design, the maximum output current is targeted to be 20A. If the 30% ripple current rule is applied, the maximum allowable ripple current is 6APP. The previous equation can be rearranged to use this value to compute a minimum inductance value that will meet our criteria. LMIN = [(VIN – VOUT) × VOUT] / (VIN × FSW × ΔIMAX) (12) For this design, the maximum ripple occurs when Vin = 14V and Vout is at the highest targeted output voltage of 3.3V. This produces a value for LMIN of 0.84µH. This value is rounded up to 1µH, which is a popular value that is available from inductor vendors. Now that the inductance value has been determined, the current handling capacity of the inductor drives the next step in the selection process. The inductor saturation limit and DCR heating limit are two key parameters. At full load, the peak current in the inductor is equal to the load current plus one half of the ΔIPP value. For this design, the peak inductor current is approximately 23A. The inductor must have a saturation current rating, ISAT, of at least 23A. The inductor saturation rating is the current level at which the inductance value falls by 20 or 30% (depending on the vendor) from its no-load value. As current increases above this value, the inductance value may fall sharply, depending on the core material and construction of the inductor. Operating an inductor in its saturated region causes the current through it to increase rapidly, causing potentially damaging levels of current to flow in the high-side FET. Good engineering practice dictates that there be should be 15% or more headroom in the inductor saturation limit to allow for transient currents and surges that will be encountered in normal operation. For this design, an ISAT rating of at least 1.15 × 23A = 26.5A would be required. For highest efficiency, an inductor with the lowest DCR will always have the lowest I2R losses. However, low resistance requires wire with a large cross section. This forces the inductor to be physically larger than a higher DCR device. The DCR of the inductor will limit its current handling capacity due to the heating it will cause when current flows through it. Inductor manufacturers typically give a maximum current rating for an inductor based on the current that produces a 40°C rise in the device temperature. Keep in mind that in an 85°C ambient environment, a 40°C rise will result in a device temperature of 125°C. Every inductor has two maximum current ratings: one is the 40°C rise rating, the other is the ISAT rating. The maximum usable current rating for the inductor is the lower of the two values. In a well designed inductor, the 40°C rise rating and ISAT are approximately equal. The 40°C rise rating should be at least equal to the maximum steady state load current of the power stage. Headroom above the steady state 40°C rise rating is not required. Momentary surge currents above the rating value will not cause a significant temperature rise due to the thermal mass of the part. The last key inductor consideration is the choice of core material. Core material affects cost, power dissipation due to core loss, and saturation characteristics. There are three popular core materials used in power inductors: powdered iron, ferrite, and powdered alloy. Powder iron is inexpensive and has a desirable soft saturation characteristic that makes it tolerant of surge and transient currents. However, at high values of ripple current and higher switching frequencies (500kHz and up), core losses become quite large. The heating due to core loss is in addition to the I2R heating due to the winding DCR. Excessive core loss can cause the core temperature to rise dramatically. In some cases, this can lead to permanent degradation of the core. Powdered iron cores are best used at switching frequencies at or below 350kHz. Ferrite has the lowest core losses, making it ideal for higher switching frequencies. Ferrite saturates easily, so ferrite based inductors are produced with some form of air gap that lowers their effective permeability and extends their saturation limit. However, once the core reaches saturation, the falloff in inductance is quite steep. This dictates the selection of a device that has some extra ISAT headroom to allow for transient current surges. Ferrite is also the most costly core material. Powdered alloy cores are an improved version of powdered iron cores. By using more exotic metal mixtures in the core, alloy cores exhibit lower core loss at high frequencies and ripple currents compared to powered iron. In some cases, they approach the performance of ferrite. The powdered alloy cores retain the desirable soft saturation characteristic of powdered iron cores. Cost wise, powdered alloy usually falls between powdered iron and ferrite. Now that the key inductor requirements are known, a device can be selected. In this design, a BI Technologies HM00-08822LFTR device, for example, meets the requirements. This is a 0.95µH device, with 1.2mΩ DCR. It uses a ferrite core with an ISAT rating of 29A. Copyright © 2011, Texas Instruments Incorporated 17 UCD7232 SLUSAH3 – MAY 2011 www.ti.com CALCULATING THE DCR CURRENT SENSE COMPONENTS With an inductor selected, the next step is to calculate the value of the DCR current sensing components. While the inductor has a nominal room temperature resistance of 1.2mΩ, when in use, the winding temperature will be elevated. Copper has a positive temperature coefficient of 3800ppm/°C. If we assume a typical temperature rise of 20°, then the winding resistance will increase by 7.6% to approximately 1.3mΩ. This DCR value will be used in the following calculations. With 20A of load current through the inductor, the voltage drop due to the DCR will be 1.3 × 20 = 26mV. This will be amplified by a factor of 48 by the current sense amplifier within the UCD7232. This will boost the signal to 1.25V. The internal circuitry then adds a 0.5V pedestal to the amplified signal which results in 1.75V at the IMON pin. This voltage is within the 2.0V dynamic range of the current measurement and fault detection circuitry of the controller, so the design can make use of the current sense network shown in Figure 3. No attenuation of the signal is necessary. R2 in Figure 7 is not required and does not have to be loaded. (If a higher DCR inductor were selected, attenuation of the current sense signal might be required, and, in that case, R2 would be populated.) The values for the current sense RC network (R1 and C6) around the inductor can now be calculated. The requirement is L/DCR = RC. Let C = 1µF. Using 1µH for L and the warm DCR value of 1.3mΩ for DCR, the calculated value for R is 769Ω. The nearest standard 1% value is 768Ω. Thus, C6 = 1µF and R1 = 768Ω. The CSP and CSN pins are sensitive to noise pickup. Signal traces to these pins should be kept short and away from the switching node and the gate drive traces. They should be shielded by ground planes and adjacent ground fingers if possible. Series 2.49kΩ resistors R3 and R4 are added close to the CSP and CSN pins to help attenuate noise. Further reduction in noise can be achieved by placing the current sense capacitor, C6, close to R3 and R4. FET SELECTION At a minimum, the FETs used in the power stage must have a VDS breakdown rating of at least 1.5 times the maximum input voltage. This headroom is required since the peak voltage on the switching node is always higher than the input voltage due to ringing caused by energy storage in the parasitic inductance of the FETs and the PCB traces. With good layout practices and the use of a snubber network, the peak voltage on the FETs can be limited to 1.5 times Vin. In this example, a minimum VDS rating of 21V is required to accommodate a 14V input voltage. The high-side FET should be selected to handle current pulses equal to twice the steady state current rating of the power stage. This allows headroom for ripple current, load transients, and brief over-current events. Note that this is a pulsed current requirement, not a continuous current requirement. The average current in the high-side FET is roughly equal to the load current times the duty cycle. For this example, an ID peak current rating of 40A or higher is the target. The average current in the FET will be highest at full load, at the lowest input voltage and highest output voltage. In this example, VIN(min) is 6V and Vout(max) is 3.3V. At full load, the average FET current will be 11A. Adding a 20% safety margin to this value produces a 13.2A steady state drain current requirement. When converting power from input voltages of approximately 8V and higher, switching losses begin to dominate over conduction losses in the high-side FET. That means RDS(ON) is not the primary specification that drives high-side FET selection. Low gate charge (Qg), low gate-to-drain charge (Qgd), and low gate resistance (Rg) become more important parameters. One of the most useful figures of merit is the product of on-resistance and gate charge (Qg × RDS(ON)). The lower the number, the better the FET. FETs are characterized at several standard gate enhancement voltages. The most popular are VGS voltages are 4.5V and 10V. Since our design is using approximately 6V of gate drive, the datasheet values of RDS(ON) at 4.5VGS will be of greatest interest. Be cautious of FETs that are characterized at 2.5VGS. These are low-threshold FETs that are useful when converting power at input voltages below 6V. However, due to subtle, but serious, side effects of the low threshold voltage, they are best avoided when converting power at voltages above 6V. For this design the TI CSD16322Q5 is an excellent choice for the high-side FET (Q1). It has low charge, an impressive figure of merit, and low Qgd. It exhibits low switching losses. It is produced in an industry standard, thermally enhanced, 5 × 6mm package. It has more than enough current handling capability for this 20A design. 18 Copyright © 2011, Texas Instruments Incorporated UCD7232 www.ti.com SLUSAH3 – MAY 2011 Low-side FET selection is driven primarily by RDS(ON). The lower the value, the higher the efficiency. Lower RDS(ON) requires a larger die size, which increases total gate charge and device cost. For a given RDS(ON) value, the part with the lowest Qg is likely to be the best choice. At higher input voltages and narrower duty cycles, the low-side FET is conducting current for the majority of switching cycle. A thermally enhanced package is a must. The continuous current rating of the FET should at least be equal to the current rating of the power stage. The TI CSD16401Q5 is used as the low-side FET (Q2) in this design. It has an RDS(ON) of 1.5mΩ, with only 21nC of Qg at 4.5V. It has more than enough current handling capacity. Its 25V minimum BVDSS rating beats our minimum voltage criteria. It comes in the same 5 × 6mm package as Q1. In rare instances, the addition of a series gate resistor can be of some benefit when dealing with high amplitude ringing. Usually, however, the addition of series gate resistance increases switching losses and increases the risk of cross-conduction between the high-side and low-side FETs. A tight, low stray inductance PCB layout, or a snubber network are the preferred methods for reducing ringing. Resistors R9 and R10 are shown as placeholders in Figure 7. They can be added to the PCB layout to allow for the possibility that series gate resistance may be needed. In most cases they are not required and can be considered optional. If they are added to the design, the default value of 0Ω should initially be used. SW NODE CLAMP At higher output currents, the switching node can momentarily swing more than a 1V below ground. This condition can interfere with the proper operation of the chip. To prevent the SW pin from being subjected to excessive negative voltage swings, a Schottky diode clamp and current limiting resistor, D1 and R11, are inserted between the actual switching node and the SW pin (pin 20). Diode D1 should be a power Schottky device rated at a minimum of 0.5A of current and at least 30V breakdown voltage. The device shown in Figure 7 is a 0.5A, 40V device in a SOD123 package. The diode should be placed as close as possible to the UCD7232 and be connected between the SW pin and PGND pin by short, wide traces. Small-signal Schottky diodes should not be used. Their forward voltage drop at higher currents is too high to provide effective clamping. Use a value of 1Ω for R11. Larger values will interfere with the anti-cross conduction logic used to control the turn-on and turn-off of the high-side FET, Q1. SNUBBER NETWORK Energy stored in the parasitic inductance in the source and drain leads of the power FETs is released when the FETs abruptly turn on and off. The parasitic inductance interacts with the output capacitance COSS) of the FETs to form a resonant circuit. The end result is high amplitude, high frequency ringing on the switching node that is most prominent just after the high-side FET is turned on. The frequency of the ringing is commonly in the 100MHz range. Its peak amplitude can be as much as twice the input voltage. If nothing is done to damp the ringing, it can cause avalanche breakdown of the low-side FET, increase radiated EMI levels, and, most important for this discussion, interfere with the detection of an over-current condition. When left undamped, the ringing on the switching node can take several hundreds of nanoseconds to die out. A simple series RC network connected to the switching node is commonly used to dampen or “snub” the ringing. The capacitor couples the high frequency content to the resistor, and the resistor dissipates the energy. With the correct values, the ringing can be made to decay to negligible levels in 100ns or less. C5 (2200pF) and R8 (3.01Ω) perform this function in the example circuit. R8 must be capable of dissipating several hundred milliwatts of power. The amount of power dissipated in R8 is proportional to the switching frequency and the value of C5. With the values shown, R8 will dissipate approximately 125mW at 500kHz. This will double if the switching frequency is increased to 1MHz. It is recommended that a 500mW rated resistor be used for R8. The optimum values of the snubber R and C are device and layout dependant. Some experimentation may be needed to achieve the optimum trade-off between damping time and power lost in the damping resistor. In most cases, the value of R is between 1Ω and 10Ω, and C is between 1000pF and 4700pF. Higher values of C cause more current to flow in R which increases the power dissipated. Copyright © 2011, Texas Instruments Incorporated 19 UCD7232 SLUSAH3 – MAY 2011 www.ti.com COMPUTING VALUES FOR RDLY and RHS Sense RDLY sets the amount of blanking time for the high speed comparator that monitors the voltage drop across the high-side FET during its on-time. This comparator fires when the high-side FET is conducting too much current. Because of the time it takes for ringing to decay on the switching node, the comparator “decision” should be delayed for a short amount of time after the high-side FET is turned on. With a proper snubber network, a delay time of 100ns should be sufficient to allow for proper over-current detection. Using the formula in the RDLY section, value of 8.03kΩ produces a 100ns delay. The nearest standard value is 8.06kΩ, so this is the value used for R7. Note that when the duty cycle is of shorter duration than the blanking time, the high-side fault sensing circuit is blanked for the entire time. Thus there is no high-side FET protection when the duty cycle duration is shorter than the RDLY blanking time. This condition commonly occurs during soft-start, when the output voltage is being ramped up from zero, or when operating at high switching frequencies and attempting to produce low output voltages from high input voltages. Keep this in mind when setting operating frequency and input to output voltage ratios. The first step in selecting a value for RHS Sense, is to determine what is the maximum allowable voltage drop across the high-side FET. This is calculated from the RDS(ON) of the FETs, taking into account its likely junction temperature when operating at the maximum current point, and by the maximum allowable FET current. The RDS(ON) value on the data sheet is specified at 25°C and at a particular VGS voltage, typically 4.5V and 10V. In this case, neither value is correct, since this design will applying approximately 6.2V to the gate. Additionally, FET RDS(ON) has a high, positive temperature coefficient of typically 4000ppm/°C. This means for a 100°C rise in junction temperature, the on-resistance will go up by 40%. For a fault condition, using a 125°C junction temperature is a reasonable assumption. A valid estimate of the RDS(ON) with 6V of enhancement at 125°C of the CSD16322Q5 is 5mΩ. The second step is to calculate a maximum current value for the high-side FET. Use 150% of the rated output current value, plus one half of the peak-to-peak inductor ripple current. For this example this gives a value of 1.5 × 20 × ½ × 5 = 32.5A. This level of current provides headroom for transients, start-up surge currents, and the increase in inductor ripple current as the inductance falls with increasing current. The maximum allowable voltage drop can now be calculated as just the product of the maximum current value and the “hot” RDS(ON). This produces a value of 162.5mV for this design. This should not be regarded as a precision value. Keep in mind that the high-side FET protection is meant to be the last protection for the power stage to prevent catastrophic damage to the power train. The maximum voltage drop value should be set high enough to prevent nuisance trips of the protection circuitry under normal operation. The value for RHS Sense can now be calculated. Its resistance, in kΩ, is equal to the maximum high-side voltage drop, in mV, divided by 100. In our example this produces a value of 1.63kΩ. Rounding this up to the nearest standard value of 1.65kΩ gives the value for R12. SETTING THE ILIM THRESHOLD The primary fault protection mechanism in the UCD7232 is the output current detection circuitry. An internal comparator monitors the voltage on the ILIM and IMON pins. When the voltage on IMON exceeds the voltage on ILIM, the FLT pin is asserted and power conversion stops. If a UCD92xx controller is used to drive the power stage, it can also monitor the voltage on IMON and detect an over current condition. The threshold for the fault trip point is easily set by firmware, making it flexible. The maximum current sense input voltage that can be correctly digitally sampled by a UCD92xx controller is 2.5V. (The maximum programmable limit for the fast OC threshold is 2V.) For this design it was decided to use this 2.5V level as the threshold for the ILIM comparator. In this way the digitally programmable controller will detect a slowly changing OC fault, and the ILIM comparator in the driver will protect the system from a sudden increase in current. This corresponds to an output current of approximately 31A. All that needs to be done is to set up a voltage divider that will produce 2.5V at the ILIM pin. The BP3 pin provides a convenient source of clean, regulated 3.3V. The value of R5 was arbitrarily set to 10kΩ. Simple math produces a value of 31.6kΩ for R6. These values produce the desired 2.5V on ILIM. The voltage divider only draws 80μA from the BP3 pin, which is within the allowable limits. 20 Copyright © 2011, Texas Instruments Incorporated UCD7232 www.ti.com SLUSAH3 – MAY 2011 INPUT AND OUTPUT CAPACITORS At the drain of the high-side FET, current is drawn in fast, brief, rectangular pulses. It is important to provide low impedance, high frequency energy storage right at the drain of the FET. For this 20A power stage, two 22µF, 16V or 25V ceramic capacitors are recommended. C1 and C2 should be placed as close to the drain of Q1 as possible. The ground side of the capacitors should be connected as close as possible to the source lead of Q2. If designing a multiphase power supply, these capacitors should be present at each power stage. Bulk input bypass capacitance may also be required to minimize voltage variations during transient loads. This bulk capacitance is not shown on Figure 7, but it is typically required. Bulk capacitance can be shared among multiple power stages. The inductor ripple current must be absorbed by the output capacitors. The ripple current is triangular in shape and contains significant energy at the switching frequency and its harmonics. To keep the ripple voltage amplitude to a minimum, low ESR and low ESL capacitors must be used. Multilayer ceramic capacitors are ideal devices. While bulk capacitance is also required to provide energy storage during transient events, the bulk capacitors do not typically handle much ripple current because their higher ESL and ESR make them look inductive at the ripple frequencies. The output ripple voltage is directly proportional to the inductor ripple current. The inductor ripple current varies widely with input voltage and duty cycle. That makes it difficult to come up with a one-size-fits-all recommendation for the proper amount of ceramic output capacitance. A good starting point is approximately 100µF. In this design two 47µF capacitors are used (C7 and C8). These capacitors should be placed close to the inductor, L1, and the ground side of these caps should be connected as close as possible to the source lead of the low-side FET, Q2. Bulk capacitance is used not only for short term transient energy storage, but also as a frequency response tailoring element in the power supply feedback loop. Several hundred microfarads, at a minimum, are commonly used in a power stage of this current capability. In this example, 330µF is being used (C9). More capacitance may be required depending on the transient response requirements of the load. BYPASS AND BOOTSTRAP CAPACITORS In this design, the bypass capacitors on BP3 (C12), VGG (C4), and the bootstrap capacitor (C3) use the recommended values. A high frequency 0.1µF bypass capacitor, C11, has also been added at the Vin pin of the UCD7232. This cap attenuates the high frequency noise that is present on the Vin rail. It should be placed as close as possible to pin 16 and connect to analog ground with a short, direct trace. LAYOUT RECOMMENDATIONS Proper component placement and trace routing can have a significant impact on overall power stage efficiency and reduce noise coupling into nearby circuits. The following are some key layout considerations. • Locate the driver as close as possible to the power FETs, but do not place it directly under either FET. The driver is a power device and needs its own thermal cooling path. Clustering multiple hot parts too close together can increase the risk of excessive temperature rise and potentially cause a thermal shutdown event. • Locate the VGG bypass and bootstrap capacitors as close as possible to the driver. • Pay special attention to the GND trace. The ground side of the input bypass capacitors, the ground side of the output capacitors, the low-side FET source leads, and the PGND connection to the driver should connected together in a tight “single point” ground, using wide, low inductance traces and few, if any vias. Use of a ground plane is strongly encouraged. • Connect the power-pad on the bottom of the driver to analog ground. The power-pad is not intended to be a high current carrying connection. The analog ground and power ground should be connected together at one point, near the AGND pin. Care should be taken to insure that heavy currents are not pulled through the analog ground traces. • The switching node trace should be kept short and compact. This is the noisiest node in the system with high dV/dt slew rates. • Use wide traces for the HS Gate and LS Gate signals closely following the associated switching node and ground traces. Use 0.050” to 0.080” (1.27 to 2.03 mm) wide traces if possible. Use at least two vias if the gate drive trace has to be routed from one layer to another. • Keep the low level input and output traces away from the switching node. The high dV/dt signal present there can induce significant noise into the relatively high impedance nodes. Pay particular attention to the routing of the CSP and CSN traces. Copyright © 2011, Texas Instruments Incorporated 21 UCD7232 SLUSAH3 – MAY 2011 www.ti.com INDUCTOR CURRENT SENSE TRACE LAYOUT Since matching of the L/DCR to RC time constants is important to obtain an accurate replica of the inductor current, the PCB layout must be done correctly to insure that the voltage drop across the inductor is sensed properly. For best results, the current sensing connections should be made by separate, non-current-carrying traces that connect directly to the inductor solder pads. The sensing connections should not be made to current carrying traces that lead to the switching node or the output capacitors. An example of a correct and incorrect layout is given in Figure 8. Inductor PCB pads Inductor PCB pads To current sense circuitry To current sense circuitry Right! Wrong! Figure 8. Inductor Current Sense Trace Layout The current carrying traces have finite resistance that exhibit an additional voltage drop which will contaminate the sensed readings. It represents an additional DCR that is not taken into account in the current sensing equations. The trace resistance varies with the thickness of the PCB copper used on the board. This thickness can vary from batch to batch of pc boards, so the additional resistance of the traces is not a tightly controlled value. Even a short length of PCB trace can introduce a significant amount of added resistance. Remember, milliohms matter. By making a Kelvin connection to the inductor pads, the effects of PCB trace resistance can be minimized. LIMITATIONS OF DCR CURRENT SENSING The accuracy of the DCR current sense method is limited by the stability of the DCR and L values of the power inductor. In practice, the inductance value of the power inductor decreases with increasing load current. Most inductors will exhibit a 20% to 30% reduction in inductance as load current changes from no load to full rated current. The DCR sense method cannot detect inductor saturation or a cracked core, both of which cause greatly increased ac current to flow in the inductor. The resistance of the inductor windings is strongly affected by temperature. Most inductors use copper wire, and copper has a resistance temperature coefficient of approximately +3800ppm/°C. This means that if the winding temperature of the inductor rises by 40°C, its DCR will increase by 15.2%. This will cause the sensed voltage at CSP and CSN to increase by 15.2% as well for the same current flow. If high accuracy of measured current is important, then some form of temperature correction needs to be applied to the DCR sensed reading. This requires some form of temperature sensing and a method to correlate the sensed temperature to the actual winding temperature. Since it is impractical to place a temperature sensor inside the inductor to sense the winding temperature, a practical alternative is to sense the high-side FET device temperature. Tests have shown that a small analogoutput temperature sensor placed under the high-side FET on the back side of the board works well as a substitute. Its temperature output correlates strongly to the inductor winding temperature. The voltage proportional to temperature can be fed to the Temp input of the UCD92xx family of Digital Power Controllers. The firmware internal to the controller can use the temperature reading to correct for the temperature effects on the DCR current sense readings. 22 Copyright © 2011, Texas Instruments Incorporated UCD7232 SLUSAH3 – MAY 2011 www.ti.com RELATED PRODUCTS DESCRIPTION LITERATURE NUMBER UCD9240 DEVICE Digital Point of Load System Controller SLUS766C UCD9220 Digital PWM System Controller SLUS904 UCD9112 Digital Dual-Phase Synchronous Buck Controller SLVS711C RELATED LITERATURE DESCRIPTION LITERATURE NUMBER QFN/SON PCB Attachment SLUA271A Quad Flatpack No-Lead Logic Packages SCBA017D Reducing Ringing Through PCB Layout Techniques SLPA005 Copyright © 2011, Texas Instruments Incorporated 23 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCD7232RTJR ACTIVE QFN RTJ 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD7232 UCD7232RTJT ACTIVE QFN RTJ 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD7232 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of