Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
UCD9090 10-rail power supply sequencer and monitor with ACPI support
1 Features
•
1
•
•
•
•
•
•
•
•
Monitor and sequence 10 voltage rails
– All rails sampled every 400 μs
– 12-bit ADC with 2.5-V, 0.5% internal VREF
– Sequence based on time, rail and pin
dependencies
– Four programmable undervoltage and
overvoltage thresholds per monitor
Nonvolatile error and peak-value logging per
monitor (up to 30 fault detail entries)
Closed-loop margining for 10 rails
– Margin output adjusts rail voltage to match
user-defined margin thresholds
Programmable watchdog timer and system reset
Flexible digital I/O configuration
Pin-selected rail states
Cascading multiple devices
Multi-phase PWM clock generator
– Clock frequencies from 15.259 kHz to
125 MHz
– Capability to configure independent clock
outputs for synchronizing switch-mode power
supplies
JTAG and I2C/SMBus/PMBus™ interfaces
2 Applications
•
•
•
•
Industrial and ATE
Telecommunications and networking equipment
Servers and storage systems
Any system requiring sequencing and monitoring
of multiple power rails
3 Description
2
The UCD9090 is a 10-rail PMBus/I C addressable
power-supply sequencer and monitor. The device
integrates a 12-bit ADC for monitoring up to 10
power-supply voltage inputs. Twenty-three GPIO pins
can be used for power supply enables, power-on
reset signals, external interrupts, cascading, or other
system functions. Ten of these pins offer PWM
functionality. Using these pins, the UCD9090 offers
support for margining, and general-purpose PWM
functions.
Specific power states can be achieved using the pinselected rail states feature. This feature allows with
the use of up to 3 GPIs to enable and disable any
rail. This is useful for implementing system low-power
modes and the Advanced Configuration and Power
Interface (ACPI) specification that is used for
hardware devices.
The TI Fusion Digital Power™ designer software
provides device configuration. This PC-based user
interface (UI) offers an intuitive interface for
configuring, storing, and monitoring all system
operating parameters.
Device Information(1)
PART NUMBER
PACKAGE
UCD9090
BODY SIZE (NOM)
VQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
12-V OUT
VOUT 12 V
TEMP12V
VIN 12 V
3.3-V Supply
INA196
Temp IC
V33A
V33D
VOUT 12 V
VMON
GPIO
VOUT
3.3 V
UCD9090
GPIO
VOUT 3.3 V
VOUT 1.8 V
VOUT 0.8 V
VIN 0.8
Temp 0.8 V
VIN 12 V
Temp 12 V
DC-DC1
VMON
VMON
VMON
VMON
VMON
VMON
VMON
WDI from main
processor
GPIO
WDO
GPIO
POWER_GOOD
GPIO
WARN_OV_ 0.8 V
or
WARN_OV_12 V
GPIO
SYSTEM_RESET
Other
sequencer done
(cascade input)
EN
VIN
VOUT
VFB
VIN
GPIO
EN
VOUT
VOUT
1.8 V
LDO1
TEMP0.8V
GPIO
EN
EN
GPIO
VIN
VOUT
VOUT
0.8 V
I0.8V
DC-DC2
VFB
INA196
2
I C/PMBus
2 MHz
JTAG
VMARG
PWM
Closed loop margining
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6
6
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C/Smbus/PMBus Timing Requirements .................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 17
7.5 Programming........................................................... 37
8
Application and Implementation ........................ 41
8.1 Application Information............................................ 41
8.2 Typical Application ................................................. 42
9 Power Supply Recommendations...................... 45
10 Layout................................................................... 45
10.1 Layout Guidelines ................................................. 45
10.2 Layout Example .................................................... 46
11 Device and Documentation Support ................. 48
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
48
48
48
48
48
48
12 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2016) to Revision D
Page
•
Changed Bus free time between start and stop specifications minimum from "4.7 μs" to "1.3 μs" in
I2C/Smbus/PMBus Timing Requirements section ................................................................................................................. 8
•
Changed Hold time after (repeated) start, Repeated-start setup time, Stop setup time, and Clock high period
specifications minimum from "0.26 μs" to "0.6 μs" in I2C/Smbus/PMBus Timing Requirements section............................... 8
•
Changed Data setup time specification minimum from "50 ns" to "100 ns" in I2C/Smbus/PMBus Timing
Requirements section ............................................................................................................................................................. 8
•
Changed Clock low period specification minimum from "0.5 μs" to "1.3 μs" in I2C/Smbus/PMBus Timing
Requirements section ............................................................................................................................................................. 8
•
Changed Clock/data fall time specification maximum from "120 ns" to "300 ns" in I2C/Smbus/PMBus Timing
Requirements section ............................................................................................................................................................. 8
•
Added Total capacitance of one bus line specification to I2C/Smbus/PMBus Timing Requirements section........................ 8
•
Clarified instructions in Programming section ..................................................................................................................... 37
•
Updated Table 10 ................................................................................................................................................................. 40
•
Clarified Full Configuration Update While in Normal Mode section ..................................................................................... 40
•
Added steps 6 through 9 in Design Requirements section .................................................................................................. 43
Changes from Revision B (December 2015) to Revision C
Page
•
Added Cascading multiple devices feature to Features section............................................................................................. 1
•
Updated Fault Responses and Alert Processing section ..................................................................................................... 22
•
Added Cascading Multiple Devices section ........................................................................................................................ 28
•
Updated Device Reset section ............................................................................................................................................. 36
•
Added Receiving Notification of Documentation Updates section ...................................................................................... 48
2
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
Changes from Revision A (August 2011) to Revision B
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
•
Changed minimum storage temperature from –40 to –55...................................................................................................... 6
•
Changed the Functional Block Diagram ............................................................................................................................... 10
•
Deleted the second paragraph under Monitoring section..................................................................................................... 19
•
Updated Voltage Monitoring section..................................................................................................................................... 19
•
Updated pin numbers in GPIO Pin Configuration Options table. ......................................................................................... 25
•
Updated first item in the GPI Special Functions section. ..................................................................................................... 28
•
Updated last sentence in Power-Supply Enables section. ................................................................................................... 28
•
Updated JTAG INTERFACE section. ................................................................................................................................... 37
•
Updated Programming section. ............................................................................................................................................ 39
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
3
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
5 Pin Configuration and Functions
NOTE
The number of configurable rails is a maximum of 10. The number of configurable general
purpose input (GPI) pins is a maximum of 8. The number of configurable Boolean logic
general purpose output (GPO) pins is a maximum of 10.
MON11
MON3
MON4
MON5
MON6
MON7
PMBUS_ADDR1
PMBUS_ADDR0
MON8
MON9
AVSS2
MON10
RGZ Package
48-Pin VQFN With Thermal Pad
Top View
MON1
48 47 46 45 44 43 42 41 40 39 38 37
1
36
AVSS1
MON2
2
35
BPCAP
RESET
3
34
V33A
GPIO1
4
33
V33D
GPIO2
5
32
DVSS
GPIO3
6
31
TRST
7
30
TMS/GPIO21
8
29
TDI/GPIO20
PMBUS_DATA
9
28
TDO/GPIO19
FPWM1/GPIO5
10
27
TCK/GPIO18
FPWM2/GPIO6
11
26
GPIO17
FPWM3/GPIO7
12
25
13 14 15 16 17 18 19 20 21 22 23 24
GPIO16
PWM2/GPI2
PWM1/GPI1
GPIO14
PMBUS_CNTRL
GPIO13
PMBUS_ALERT
FPWM8/GPIO12
FPWM7/GPIO11
FPWM6/GPIO10
FPWM5/GPIO9
FPWM4/GPIO8
Thermal
Pad
GPIO15
GPIO4
PMBUS_CLK
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
ANALOG MONITOR INPUTS
MON1
1
I
Analog input (0 V – 2.5 V)
MON2
2
I
Analog input (0 V – 2.5 V)
MON3
38
I
Analog input (0 V – 2.5 V)
MON4
39
I
Analog input (0 V – 2.5 V)
MON5
40
I
Analog input (0 V – 2.5 V)
MON6
41
I
Analog input (0 V – 2.5 V)
MON7
42
I
Analog input (0 V – 2.5 V)
MON8
45
I
Analog input (0 V – 2.5 V)
MON9
46
I
Analog input (0 V – 2.5 V)
MON10
48
I
Analog input (0 V – 2.5 V)
4
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
MON11
37
I
GPIO1
4
I/O
General-purpose discrete input-output
GPIO2
5
I/O
General-purpose discrete input-output
GPIO3
6
I/O
General-purpose discrete input-output
GPIO4
7
I/O
General-purpose discrete input-output
GPIO13
18
I/O
General-purpose discrete input-output
GPIO14
21
I/O
General-purpose discrete input-output
GPIO15
24
I/O
General-purpose discrete input-output
GPIO16
25
I/O
General-purpose discrete input-output
GPIO17
26
I/O
General-purpose discrete input-output
FPWM1/GPIO5
10
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM2/GPIO6
11
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM3/GPIO7
12
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM4/GPIO8
13
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM5/GPIO9
14
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM6/GPIO10
15
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM7/GPIO11
16
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM8/GPIO12
17
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
PWM1/GPI1
22
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM2/GPI2
23
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
Analog input (0.2 V – 2.5 V)
GPIO
PWM OUTPUTS
PMBus COMM INTERFACE
PMBus_CLK
8
I/O
PMBus clock (must have pullup to 3.3 V)
PMBus_DATA
9
I/O
PMBus data (must have pullup to 3.3 V)
PMBus_ALERT
19
O
PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)
PMBus_CNTRL
20
I
PMBus control
PMBus_ADDR0
44
I
PMBus analog address input. Least-significant address bit
PMBus_ADDR1
43
I
PMBus analog address input. Most-significant address bit
TCK/GPIO18
27
I/O
Test clock or GPIO
TDO/GPIO19
28
I/O
Test data out or GPIO
TDI/GPIO20
29
I/O
Test data in (tie to Vdd with 10-kΩ resistor) or GPIO
TMS/GPIO21
30
I/O
Test mode select (tie to Vdd with 10-kΩ resistor) or GPIO
TRST
31
I
JTAG
Test reset – tie to ground with 10-kΩ resistor
INPUT POWER AND GROUNDS
RESET
3
—
Active-low device reset input. Hold low for at least 2 μs to reset the device.
V33A
34
—
Analog 3.3-V supply. Refer to the Layout Guidelines section.
V33D
33
—
Digital core 3.3-V supply. Refer to the Layout Guidelines section.
BPCap
35
—
1.8-V bypass capacitor. Refer to the Layout Guidelines section.
AVSS1
36
—
Analog ground
AVSS2
47
—
Analog ground
DVSS
32
—
Digital ground
—
Tie to ground plane.
Thermal pad
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
5
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Voltage applied at V33D to DVSS
–0.3
3.8
V
Voltage applied at V33A to AVSS
–0.3
3.8
V
–0.3
V33A + 0.3
V
–55
150
°C
Voltage applied to any other pin
(2)
Storage temperature (Tstg)
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Supply voltage during operation (V33D, V33DIO, V33A)
Operating free-air temperature, TA
MIN
NOM
MAX
3
3.3
3.6
V
110
°C
125
°C
–40
Junction temperature, TJ
UNIT
6.4 Thermal Information
UCD9090
THERMAL METRIC
(1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
25
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
8.9
°C/W
RθJB
Junction-to-board thermal resistance
5.5
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
1.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.7
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
SUPPLY CURRENT
IV33A
VV33A = 3.3 V
8
mA
IV33DIO
VV33DIO = 3.3 V
2
mA
VV33D = 3.3 V
40
mA
VV33D = 3.3 V, storing configuration parameters in
flash memory
50
mA
Supply current (1)
IV33D
IV33D
ANALOG INPUTS (MON1–MON13)
VMON
Input voltage range
MON1–MON10
MON11
0
2.5
0.2
2.5
V
V
INL
ADC integral nonlinearity
–4
4
LSB
DNL
ADC differential nonlinearity
-2
2
LSB
Ilkg
Input leakage current
3 V applied to pin
IOFFSET
Input offset current
1-kΩ source impedance
MON1–MON10, ground reference
RIN
Input impedance
CIN
Input capacitance
tCONVERT
ADC sample period
12 voltages sampled, 3.89 μs/sample
ADC 2.5 V, internal reference accuracy
0°C to 125°C
VREF
MON11, ground reference
100
–5
nA
5
μA
8
0.5
MΩ
1.5
3
MΩ
10
pF
400
μs
–0.5%
0.5%
–40°C to 125°C
–1%
1%
9
11
2.26
ANALOG INPUT (PMBus_ADDRx)
IBIAS
Bias current for PMBus Addr pins
VADDR_OPEN
Voltage – open pin
PMBus_ADDR0, PMBus_ADDR1 open
VADDR_SHORT
Voltage – shorted pin
PMBus_ADDR0, PMBus_ADDR1 short to ground
μA
V
0.124
V
Dgnd +
0.25
V
DIGITAL INPUTS AND OUTPUTS
VOL
Low-level output voltage
IOL = 6 mA (2), V33DIO = 3 V
VOH
High-level output voltage
IOH = –6 mA (3), V33DIO = 3 V
VIH
High-level input voltage
V33DIO = 3 V
VIL
Low-level input voltage
V33DIO = 3.5 V
V33DIO
– 0.6
V
2.1
3.6
V
1.4
V
MARGINING OUTPUTS
TPWM_FREQ
MARGINING-PWM frequency
FPWM1-8
PWM1-2
DUTYPWM
MARGINING-PWM duty cycle range
15.260
125000
0.001
7800
0%
100%
kHz
SYSTEM PERFORMANCE
VDDSlew
Minimum VDD slew rate
VDD slew rate between 2.3 V and 2.9 V
VRESET
Supply voltage at which device comes
out of reset
For power-on reset (POR)
tRESET
Low-pulse duration needed at RESET pin To reset device during normal operation
f(PCLK)
Internal oscillator frequency
TA = 125°C, TA = 25°C
240
tretention
Retention of configuration parameters
TJ = 25°C
100
Years
Write_Cycles
Number of nonvolatile erase/write cycles
TJ = 25°C
20
K cycles
(1)
(2)
(3)
0.25
V/ms
2.4
V
260
MHz
2
μS
250
Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins.
The maximum total current, IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
The maximum total current, IOHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
7
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
6.6 I2C/Smbus/PMBus Timing Requirements
TA = –40°C to 85°C, 3 V < VDD < 3.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
FSMB
SMBus/PMBus operating frequency
Slave mode, SMBC 50% duty cycle
10
400
kHz
FI2C
I2C operating frequency
Slave mode, SCL 50% duty cycle
10
400
kHz
t(BUF)
Bus free time between start and stop
1.3
μs
t(HD:STA)
Hold time after (repeated) start
0.6
μs
t(SU:STA)
Repeated-start setup time
0.6
μs
t(SU:STO)
Stop setup time
0.6
μs
t(HD:DAT)
Data hold time
0
ns
t(SU:DAT)
Data setup time
t(TIMEOUT)
Error signal/detect
t(LOW)
Clock low period
Receive mode
100
t(HIGH)
Clock high period
See
t(LOW:SEXT)
Cumulative clock low slave extend time
See
(3)
tf
Clock/data fall time
See
(4)
tr
Clock/data rise time
See
(5)
Cb
Total capacitance of one bus line
(3)
(4)
(5)
35
1.3
(2)
(1)
(2)
ns
See (1)
ms
μs
0.6
μs
25
ms
20 +
0.1 Cb
300
ns
20 +
0.1 Cb
300
ns
400
pF
The device times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
Fall time tf = 0.9 VDD to (VILMAX – 0.15)
Rise time tr = (VILMAX – 0.15) to (VIHMIN + 0.15)
Figure 1. I2C/SMBus Timing Diagram
Start
Stop
TLOW:SEXT
TLOW:MEXT
TLOW:MEXT
TLOW:MEXT
PMB_Clk
Clk ACK
Clk ACK
PMB_Data
Figure 2. Bus Timing in Extended Mode
8
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
6.7 Typical Characteristics
1.2
2.5
1
0.8
2.496
0.6
2.494
DNL (LSB)
ADC Reference Voltage (V)
2.498
2.492
2.49
0.4
DNLmin
DNL max
0.2
0
-0.2
2.488
-0.4
2.486
-0.6
2.484
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
-0.8
-40
-20
0
20
D001
Figure 3. ADC Reference Voltage vs Temperature
40
60
80
Temperature (°C)
100
120
140
D001
Figure 4. ADC Differential Nonlinearity vs Temperature
3
2.5
INL (LSB)
2
1.5
INL min
INL max
1
0.5
0
-0.5
-1
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D001
Figure 5. ADC Integral Nonlinearity vs Temperature
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
9
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
7 Detailed Description
7.1 Overview
Electronic systems that include CPU, DSP, micro-controller, FPGA, ASIC, and so forth can have multiple voltage
rails and require certain power on/off sequences in order to function correctly. The UCD9090 can control up to 10
voltage rails and ensure correct power sequences during normal condition and fault conditions.
In addition to sequencing, UCD9090 can continuously monitor rail voltages, currents, temperatures, fault
conditions, and report the system health information to a PMBus host, improving systems’ long term reliability.
Also, UCD9090 can protect electronic systems by responding to power system faults. The fault responses are
conveniently configured by users through the user interface of the TI Fusion Digital Power Designer software.
Fault events are stored in on-chip nonvolatile flash memory with time stamp in order to assist failure analysis.
System reliability can be improved through four-corner testing during system verification. During four-corner
testing, each voltage rail is required to operate at the minimum and maximum output voltages, commonly known
as margining. UCD9090 can perform closed-loop margining for up to 10 voltage rails. During normal operation,
UCD9090 can also actively trim DC output voltages using the same margining circuitry.
UCD9090 supports both PMBus-based and pin-based control environments. UCD9090 functions as a PMBus
slave. It can communicate with PMBus host with PMBus commands, and control voltage rails accordingly. Also,
UCD9090 can be controlled by up to 8 GPIO configured GPI pins. The GPIs can be used as Boolean logic input
to control up to 10 logic GPO outputs. Each Logic GPO has a flexible Boolean logic builder. Input signals of the
Boolean logic builder can include GPIs, other logic GPO outputs, and selectable system flags such as
POWER_GOOD, faults and warnings. A simple state machine is also available for each logic GPO pin.
UCD9090 provides additional features such as pin-selected states, system watchdog, system reset, runtime
clock, peak value log, reset counter, and so on. Pin-selected states feature allows users to use up to 3 GPIs to
define up to 8 rail states. These states can implement system low-power modes as set out in the Advanced
Configuration and Power Interface (ACPI) specification. Other features will be introduced in the following sections
of this data sheet.
7.2 Functional Block Diagram
Comparators
JTAG or GPIO
General Purpose I/O
(GPIO)
2
I C/PMBus
6
23
Sequencing Engine
11
Rail Enables (10 max)
Monitor Inputs
12-bit, 200 ksps,
ADC
(0.5% internal
reference)
Digital Outputs (10 max)
Digital Inputs (8 max)
FLASH Memory
User Data, Fault
and Peak Logging
BOOLEAN
Logic Builder
Multi-phase PWM (8 max)
Margining Outputs (10 max)
Copyright © 2016, Texas Instruments Incorporated
10
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
7.3 Feature Description
7.3.1 TI Fusion User Interface (UI)
The Texas Instruments Fusion Digital Power Designer provides device configuration. This PC-based graphical
user interface (GUI) offers an intuitive I2C/PMBus interface to the device. It allows the design engineer to
configure the system operating parameters for the application without directly using PMBus commands, store the
configuration to on-chip nonvolatile memory, and observe system status (voltage, etc). Fusion Digital Power
Designer is referenced throughout the data sheet as Fusion GUI and many sections include screenshots. The
Fusion GUI can be downloaded from www.ti.com.
7.3.2 PMBus Interface
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
interface that is built on the I2C physical specification. The UCD9090 supports revision 1.1 of the PMBus
standard. Wherever possible, standard PMBus commands are used to support the function of the device. For
unique features of the UCD9090, MFR_SPECIFIC commands are defined to configure or activate those features.
These commands are defined in the UCD90xxx Sequencer and System Health Controller PMBus Command
Reference (SLVU352). The most current UCD90xxx PMBus™ Command Reference can be found within the TI
Fusion Digital Power Designer software via the Help Menu (Help, Documentation & Help Center, Sequencers
tab, Documentation section).
This document makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power
System Management Protocol Specification Part II – Command Language, Revision 1.1, dated 5 February 2007.
The specification is published by the Power Management Bus Implementers Forum and is available from
www.PMBus.org.
The UCD9090 is PMBus compliant, in accordance with the Compliance section of the PMBus specification. The
firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT function.
The hardware can support either 100-kHz or 400-kHz PMBus operation.
7.3.3 Rail Configuration
A rail includes voltage, a power-supply enable and a margining output. At least one must be included in a rail
definition. Once the user has defined how the power-supply rails should operate in a particular system, analog
input pins and GPIOs can be selected to monitor and enable each supply (Figure 6).
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
11
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Feature Description (continued)
Figure 6. Fusion GUI Pin-Assignment Tab
12
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
Feature Description (continued)
After the pins have been configured, other key monitoring and sequencing criteria are selected for each rail from
the Vout Config tab (Figure 7):
• Nominal operating voltage (Vout)
• Undervoltage (UV) and overvoltage (OV) warning and fault limits
• Margin-low and margin-high values
• Power-good on and power-good off limits
• PMBus or pin-based sequencing control (On/Off Config)
• Rails and GPIs for Sequence On dependencies
• Rails and GPIs for Sequence Off dependencies
• Turn-on and turn-off delay timing
• Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled
or disabled
• Other rails to turn off in case of a fault on a rail (fault-shutdown slaves)
Figure 7. Fusion GUI VOUT-Config Tab
The Synchronize margins/limits/PG to Vout checkbox is an easy way to change the nominal operating voltage
of a rail and also update all of the other limits associated with that rail according to the percentages shown to the
right of each entry.
The plot in the upper left section of Figure 7 shows a simulation of the overall sequence-on and sequence-off
configuration, including the nominal voltage, the turnon and turnoff delay times, the power-good on and powergood off voltages and any timing dependencies between the rails.
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
13
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Feature Description (continued)
After a rail voltage has reached its POWER_GOOD_ON voltage and is considered to be in regulation, it is
compared against two UV and two OV thresholds in order to determine if a warning or fault limit has been
exceeded. If a fault is detected, the UCD9090 responds based on a variety of flexible, user-configured options.
Faults can cause rails to restart, shut down immediately, sequence off using turnoff delay times or shut down a
group of rails and sequence them back on. Different types of faults can result in different responses.
Fault responses, along with a number of other parameters including user-specific manufacturing information and
external scaling and offset values, are selected in the different tabs within the Configure function of the Fusion
GUI. Once the configuration satisfies the user requirements, it can be written to device SRAM if Fusion GUI is
connected to a UCD9090 using an I2C/PMBus. SRAM contents can then be stored to data flash memory so that
the configuration remains in the device after a reset or power cycle.
The Fusion GUI Monitor page has a number of options, including a device dashboard and a system dashboard,
for viewing and controlling device and system status.
Figure 8. Fusion GUI Monitor Page
The UCD9090 also has status registers for each rail and the capability to log faults to flash memory for use in
system troubleshooting. This is helpful in the event of a power-supply or system failure. The status registers
(Figure 9) and the fault log (Figure 10) are available in the Fusion GUI. See the UCD90xxx Sequencer and
System Health Controller PMBus Command Reference (SLVU352) and the PMBus Specification for detailed
descriptions of each status register and supported PMBus commands.
14
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
Feature Description (continued)
Figure 9. Fusion GUI Rail-Status Register
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
15
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Feature Description (continued)
Figure 10. Fusion GUI Flash-Error Log (Logged Faults)
16
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
7.4 Device Functional Modes
7.4.1 Power-Supply Sequencing
The UCD9090 can control the turn-on and turn-off sequencing of up to 10 voltage rails by using a GPIO to set a
power-supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a
sequence-on event by asserting the PMBus_CNTRL pin or by sending the OPERATION command over the I2C
serial bus. In pin-based designs, the PMBus_CNTRL pin can also be used to sequence-on and sequence-off.
The auto-enable setting ignores the OPERATION command and the PMBus_CNTRL pin. Sequence-on is started
at power up after any dependencies and time delays are met for each rail. A rail is considered to be on or within
regulation when the measured voltage for that rail crosses the power-good on (POWER_GOOD_ON (6)) limit.
The rail is still in regulation until the voltage drops below power-good off (POWER_GOOD_OFF). In the case that
there in no voltage monitoring set for a given rail, that rail is considered ON if it is commanded on (either by
OPERATION command, PMBus CNTRL pin, or auto-enable) and (TON_DELAY + TON_MAX_FAULT_LIMIT)
time passes. Also, a rail is considered OFF if that rail is commanded OFF and (TOFF_DELAY +
TOFF_MAX_WARN_LIMIT) time passes.
7.4.1.1 Turn-On Sequencing
The following sequence-on options are supported for each rail:
• Monitor only – do not sequence-on
• Fixed delay time (TON_DELAY) after an OPERATION command to turn on
• Fixed delay time after assertion of the PMBus_CNTRL pin
• Fixed time after one or a group of parent rails achieves regulation (POWER_GOOD_ON)
• Fixed time after a designated GPI has reached a user-specified state
• Any combination of the previous options
The maximum TON_DELAY time is 3276 ms.
7.4.1.2 Turn-Off Sequencing
The following sequence-off options are supported for each rail:
• Monitor only – do not sequence-off
• Fixed delay time (TOFF_DELAY) after an OPERATION command to turn off
• Fixed delay time after deassertion of the PMBus_CNTRL pin
• Fixed time after one or a group of parent rails drop below regulation (POWER_GOOD_OFF)
• Fixed delay time in response to an undervoltage, overvoltage, or max turn-on fault on the rail
• Fixed delay time in response to a fault on a different rail when set as a fault shutdown slave to the faulted rail
• Fixed delay time in response to a GPI reaching a user-specified state
• Any combination of the previous options
The maximum TOFF_DELAY time is 3276 ms.
(6)
In this document, configuration parameters such as Power-Good-On are referred to using Fusion GUI names. The UCD90xxx
Sequencer and System Health Controller PMBus Command Reference name is shown in parentheses (POWER_GOOD_ON) the first
time the parameter appears.
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
17
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Device Functional Modes (continued)
Rail 1 and Rail 2 are both sequenced “ON”
and “OFF” by the PMBUS_CNTRL pin
only
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as an “OFF” dependency
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
POWER_GOOD_ON[1]
POWER_GOOD_OFF[1]
RAIL 1 VOLTAGE
TOFF_DELAY[2]
TON_DELAY[2]
RAIL 2 EN
RAIL 2 VOLTAGE
TON_MAX_FAULT_LIMIT[2]
TOFF_MAX_WARN_LIMIT[2]
Figure 11. Sequence-On and Sequence-Off Timing
7.4.1.3 Sequencing Configuration Options
In addition to the turn-on and turn-off sequencing options, the time between when a rail is enabled and when the
monitored rail voltage must reach its power-good-on setting can be configured using max turn-on
(TON_MAX_FAULT_LIMIT). Max turn-on can be set in 1-ms increments. A value of 0 ms means that there is no
limit and the device can try to turn on the output voltage indefinitely.
Rails can be configured to turn off immediately or to sequence-off according to rail and GPI dependencies, and
user-defined delay times. A sequenced shutdown is configured by selecting the appropriate rail and GPI
dependencies, and turn-off delay (TOFF_DELAY) times for each rail. The turn-off delay times begin when the
PMBus_CNTRL pin is deasserted, when the PMBus OPERATION command is used to give a soft-stop
command, or when a fault occurs on a rail that has other rails set as fault-shutdown slaves.
Shutdowns on one rail can initiate shutdowns of other rails or controllers. In systems with multiple UCD9090s, it
is possible for each controller to be both a master and a slave to another controller.
7.4.2 Pin-Selected Rail States
This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing
system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used
for operating system directed power management in servers and PCs. In up to 8 system states, the power
system designer can define which rails are on and which rails are off. If a new state is presented on the input
pins, and a rail is required to change state, it will do so with regard to its sequence-on or sequence-off
dependencies.
The OPERATION command is modified when this function causes a rail to change its state. This means that the
ON_OFF_CONFIG for a given rail must be set to use the OPERATION command for this function to have any
effect on the rail state. The first 3 pins configured with the GPI_CONFIG command are used to select 1 of 8
system states. Whenever the device is reset, these pins are sampled and the system state, if enabled, will be
used to update each rail state. When selecting a new system state, changes to the status of the GPIs must not
take longer than 1 microsecond. See the UCD90xxx Sequencer and System Health Controller PMBus Command
Reference for complete configuration settings of PIN_SELECTED_RAIL_STATES.
Table 1. GPI Selection of System States
18
GPI 2 STATE
GPI 1 STATE
GPI 0 STATE
SYSTEM
STATE
NOT Asserted
NOT Asserted
NOT Asserted
0
NOT Asserted
NOT Asserted
Asserted
1
NOT Asserted
Asserted
NOT Asserted
2
NOT Asserted
Asserted
Asserted
3
Asserted
NOT Asserted
NOT Asserted
4
Asserted
NOT Asserted
Asserted
5
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
Table 1. GPI Selection of System States (continued)
GPI 2 STATE
GPI 1 STATE
GPI 0 STATE
SYSTEM
STATE
Asserted
Asserted
NOT Asserted
6
Asserted
Asserted
Asserted
7
7.4.3 Monitoring
The UCD9090 has 11 monitor input pins (MONx) that are multiplexed into a 2.5V referenced 12-bit ADC. The
monitor pins can be configured so that they can measure voltage signals to report voltage, current and
temperature type measurements. A single rail can include all three measurement types, each monitored on
separate MON pins. If a rail has both voltage and current assigned to it, then the user can calculate power for the
rail. Digital filtering applied to each MON input depends on the type of signal. Voltage inputs have no filtering.
Current and temperature inputs have a low-pass filter.
7.4.3.1 Voltage Monitoring
Up to 11 voltages can be monitored using the analog input pins. The input voltage range is 0 V – 2.5 V for all
MONx inputs except MON11 (pin 37) which has a range of 0.2V–2.5V. Any voltage between 0 V and 0.2 V on
this pin is read as 0.2 V. External resistors can be used to attenuate voltages higher than 2.5 V.
The ADC operates continuously, requiring 3.89 μs to convert a single analog input. Each rail is sampled by the
sequencing and monitoring algorithm every 400 μs. The maximum source impedance of any sampled voltage
should be less than 4 kΩ. The source impedance limit is particularly important when a resistor-divider network is
used to lower the voltage applied to the analog input pins.
MON1 - MON6 can be configured using digital hardware comparators, which can be used to achieve faster fault
responses. Each hardware comparator has four thresholds (two UV (Fault and Warning) and two OV (Fault and
Warning)). The hardware comparators respond to UV or OV conditions in about 80 μs (faster than 400 µs for the
ADC inputs) and can be used to disable rails or assert GPOs. The only fault response available for the hardware
comparators is to shut down immediately.
An internal 2.5-V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and
125°C and a tolerance of ±1% between –40°C and 125°C. An external voltage divider is required for monitoring
voltages higher than 2.5 V. The nominal rail voltage and the external scale factor can be entered into the Fusion
GUI and are used to report the actual voltage being monitored instead of the ADC input voltage. The nominal
voltage is used to set the range and precision of the reported voltage according to Table 2.
MON1 – MON6
MON1
MON2
.
.
.
.
MON13
M
U
X
Analog
Inputs
(12)
Fast Digital
Comparators
12-bit
SAR ADC
200ksps
MON1 – MON13
Glitch
Filter
Internal
2.5Vref
0.5%
Figure 12. Voltage Monitoring Block Diagram
Table 2. Voltage Range and Resolution
VOLTAGE RANGE (V)
RESOLUTION (mV)
0 to 127.99609
3.90625
0 to 63.99805
1.95313
0 to 31.99902
0.97656
0 to 15.99951
0.48824
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
19
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Table 2. Voltage Range and Resolution (continued)
VOLTAGE RANGE (V)
RESOLUTION (mV)
0 to 7.99976
0.24414
0 to 3.99988
0.12207
0 to 1.99994
0.06104
0 to 0.99997
0.03052
Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of
610 μV is fixed by the 2.5-V reference and the 12-bit ADC.
7.4.3.2 Current Monitoring
Current can be monitored using the analog inputs. External circuitry, see Figure 13, must be used in order to
convert the current to a voltage within the range of the UCD9090 MONx input being used.
If a monitor input is configured as a current, the measurements are smoothed by a sliding-average digital filter.
The current for 1 rail is measured every 200μs. If the device is programmed to support 10 rails (independent of
current not being monitored at all rails), then each rail's current will get measured every 2ms. The current
calculation is done with a sliding average using the last 4 measurements. The filter reduces the probability of
false fault detections, and introduces a small delay to the current reading. If a rail is defined with a voltage
monitor and a current monitor, then monitoring for undercurrent warnings begins once the rail voltage reaches
POWER_GOOD_ON. If the rail does not have a voltage monitor, then current monitoring begins after
TON_DELAY.
The device supports multiple PMBus commands related to current, including READ_IOUT, which reads external
currents from the MON pins; IOUT_OC_FAULT_LIMIT, which sets the overcurrent fault limit;
IOUT_OC_WARN_LIMIT, which sets the overcurrent warning limit; and IOUT_UC_FAULT_LIMIT, which sets the
undercurrent fault limit. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference
contains a detailed description of how current fault responses are implemented using PMBus commands.
IOUT_CAL_GAIN is a PMBus command that allows the scale factor of an external current sensor and any
amplifiers or attenuators between the current sensor and the MON pin to be entered by the user in milliohms.
IOUT_CAL_OFFSET is the current that results in 0 V at the MON pin. The combination of these PMBus
commands allows current to be reported in amperes. The example below using the INA196 would require
programming IOUT_CAL_GAIN to Rsense(mΩ)×20.
UCD9090
MONx
VOUT
Vin+
AVSS1
Rsense
GND
Vin3.3V
Current Path
INA196
V+
Gain = 20V/V
Figure 13. Current Monitoring Circuit Example Using the INA196
20
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
7.4.3.3 Remote Temperature Monitoring and Internal Temperature Sensor
The UCD9090 has support for internal and remote temperature sensing. The internal temperature sensor
requires no calibration and can report the device temperature via the PMBus interface. The remote temperature
sensor can report the remote temperature by using a configurable gain and offset for the type of sensor that is
used in the application such as a linear temperature sensor (LTS) connected to the analog inputs.
External circuitry must be used in order to convert the temperature to a voltage within the range of the UCD9090
MONx input being used.
If an input is configured as a temperature, the measurements are smoothed by a sliding average digital filter. The
temperature for 1 rail is measured every 100ms. If the device is programmed to support 10 rails (independent of
temperature not being monitored at all rails), then each rail's temperature will get measured every 1s. The
temperature calculation is done with a sliding average using the last 16 measurements. The filter reduces the
probability of false fault detections, and introduces a small delay to the temperature reading. The internal device
temperature is measured using a silicon diode sensor with an accuracy of ±5°C and is also monitored using the
ADC. Temperature monitoring begins immediately after reset and initialization.
The device supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1,
which reads the internal temperature; READ_TEMPERATURE_2, which reads external temperatures; and
OT_FAULT_LIMIT and OT_WARN_LIMIT, which set the overtemperature fault and warning limit. The UCD90xxx
Sequencer and System Health Controller PMBus Command Reference contains a detailed description of how
temperature-fault responses are implemented using PMBus commands.
TEMPERATURE_CAL_GAIN is a PMBus command that allows the scale factor of an external temperature
sensor and any amplifiers or attenuators between the temperature sensor and the MON pin to be entered by the
user in °C/V. TEMPERATURE_CAL_OFFSET is the temperature that results in 0 V at the MON pin. The
combination of these PMBus commands allows temperature to be reported in degrees Celsius.
UCD9090
TMP20
MONx
VOUT
AVSS1
GND
3.3V
V+
Vout = -11.67mV/°C x T + 1.8583
at -40°C < T < 85°C
Figure 14. Remote Temperature Monitoring Circuit Example Using the TMP20
7.4.3.4 Temperature by Host Input
If the host system has the option of not using the temperature-sensing capability of the UCD9090, it can still
provide the desired temperature to the UCD9090 through PMBus. The host may have temperature
measurements available through I2C or SPI interfaced temperature sensors. The UCD9090 would use the
temperature given by the host in place of an external temperature measurement for a given rail. The temperature
provided by the host would still be used for detecting overtemperature warnings or faults, logging peak
temperatures, input to Boolean logic-builder functions, and feedback for the fan-control algorithms. To write a
temperature associated with a rail, the PMBus command used is the READ_TEMPERATURE_2 command. If the
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
21
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
host writes that command, the value written will be used as the temperature until another value is written. This is
true whether a monitor pin was assigned to the temperature or not. When there is a monitor pin associated with
the temperature, once READ_TEMPERATURE_2 is written, the monitor pin is not used again until the part is
reset. When there is not a monitor pin associated with the temperature, the internal temperature sensor is used
for the temperature until the READ_TEMPERATURE_2 command is written.
UCD9090
Faults and
Warnings
REMOTE
TEMP
SENSOR
I2C
I2C or SPI
HOST
Logged Peak
Temperatures
READ_TEMPERATURE_2
Boolean Logic
Figure 15. Temperature Provided by Host
7.4.4 Fault Responses and Alert Processing
The UCD9090 monitors whether the rail stays within a window of normal operation.. There are two
programmable warning levels (under and over) and two programmable fault levels (under and over). When any
monitored voltage goes outside of the warning or fault window, the PMBALERT pin is asserted immediately, and
the appropriate bits are set in the PMBus status registers (see Figure 9). Detailed descriptions of the status
registers are provided in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference
and the PMBus Specification.
A programmable glitch filter can be enabled or disabled for each MONx input pin. A glitch filter for an input
defined as a voltage can be set between 0 ms and 102 ms with 400-μs resolution. The glitch filter applies to fault
responses only. A fault condition that is filtered by the glitch filter is still recorded in the fault log.
Fault-response decisions are based on results from the 12-bit ADC. The device cycles through the ADC results
and compares them against the programmed limits. When the event occurs within the ADC conversion cycle and
the selected fault response determines the time to respond to an individual event.
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
TIME BETWEEN
RESTARTS
MAX_GLITCH_TIME +
TOFF_DELAY[1]
MAX_GLITCH_TIME +
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
VOUT_OV_FAULT _LIMIT
VOUT_UV_FAULT _LIMIT
RAIL 1 VOLTAGE
RAIL 2 EN
POWER_GOOD_ON[1]
MAX_GLITCH_TIME
MAX_GLITCH_TIME
TOFF_DELAY[1]
MAX_GLITCH_TIME
TON_DELAY[2]
TOFF_DELAY[2]
RAIL 2 VOLTAGE
Rail 1 and Rail 2 are both sequenced “ON” and
“OFF” by the PMBUS_CNTRL pin only
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as a Fault Shutdown Slave
Rail 1 is set to use the glitch filter for UV or OV events
Rail 1 is set to RESTART 3 times after a UV or OV event
Rail 1 is set to shutdown with delay for a OV event
Figure 16. Sequencing and Fault-Response Timing
22
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
PMBUS_CNTRL PIN
TON_DELAY[1]
RAIL 1 EN
Rail 1 and Rail 2 are both sequenced
“ON” and “OFF” by the PMBUS_CNTRL
pin only
Time Between Restarts
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 is set to shutdown immediately
and RESTART 1 time in case of a Time
On Max fault
POWER_GOOD_ON[1]
POWER_GOOD_ON[1]
RAIL 1 VOLTAGE
TON_MAX_FAULT_LIMIT[1]
TON_DELAY[2]
TON_MAX_FAULT_LIMIT[1]
RAIL 2 EN
RAIL 2 VOLTAGE
Figure 17. Maximum Turn-On Fault
The configurable fault limits are:
TON_MAX_FAULT – Flagged if a rail that is enabled does not reach the POWER_GOOD_ON limit within the
configured time
VOUT_UV_WARN – Flagged if a voltage rail drops below the specified UV warning limit after reaching the
POWER_GOOD_ON setting
VOUT_UV_FAULT – Flagged if a rail drops below the specified UV fault limit after reaching the
POWER_GOOD_ON setting
VOUT_OV_WARN – Flagged if a rail exceeds the specified OV warning limit at any time during startup or
operation
VOUT_OV_FAULT – Flagged if a rail exceeds the specified OV fault limit at any time during startup or operation
MAX_TOFF_WARN – Flagged if a rail that is commanded to shut down does not reach 12.5% of the nominal rail
voltage within the configured time
Faults are more serious than warnings. The PMBALERT# pin is always asserted immediately if a warning or fault
occurs. If a warning occurs, the following takes place:
Warning Actions
— Immediately assert the PMBALERT# pin
— Status bit is flagged
— Assert a GPIO pin (optional)
— Warnings are not logged to flash
A number of fault response options can be chosen from:
Fault Responses
— Continue Without Interruption: Flag the fault and take no action
— Shut Down Immediately: Shut down the faulted rail immediately and restart according to the rail
configuration
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
23
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
— Shut Down using TOFF_DELAY: If a fault occurs on a rail, exhaust whatever retries are
configured. If the rail does not come back, schedule the shutdown of this rail and all faultshutdown slaves. All selected rails, including the faulty rail, are sequenced off according to their
sequence-off dependencies and T_OFF_DELAY times. If Do Not Restart is selected, then
sequence off all selected rails when the fault is detected.
Restart
— Do Not Restart: Do not attempt to restart a faulted rail after it has been shut down.
— Restart Up To N Times: Attempt to restart a faulted rail up to 14 times after it has been shut down.
The time between restarts is measured between when the rail enable pin is deasserted (after any
glitch filtering and turn-off delay times, if configured to observe them) and then reasserted. It can
be set between 0 and 1275 ms in 5-ms increments.
— Restart Continuously: Same as Restart Up To N Times except that the device continues to restart
until the fault goes away, it is commanded off by the specified combination of PMBus
OPERATION command and PMBus_CNTRL pin status, the device is reset, or power is removed
from the device.
— Shut Down Rails and Sequence On (Re-sequence): Shut down selected rails immediately or after
continue-operation time is reached and then sequence-on those rails using sequence-on
dependencies and T_ON_DELAY times.
7.4.5 Shut Down All Rails and Sequence On (Resequence)
In response to a fault, or a RESEQUENCE command, the UCD9090 can be configured to turn off a set of rails
and then sequence them back on. To sequence all rails in the system, then all rails must be selected as faultshutdown slaves of the faulted rail. The rails designated as fault-shutdown slaves will do soft shutdowns
regardless of whether the faulted rail is set to stop immediately or stop with delay. Shut-down-all-rails and
sequence-on are not performed until retries are exhausted for a given fault.
While waiting for the rails to turn off, an error is reported if any of the rails reaches its TOFF_MAX_WARN_LIMIT.
There is a configurable option to continue with the resequencing operation if this occurs. After the faulted rail and
fault-shutdown slaves sequence-off, the UCD9090 waits for a programmable delay time between 0 and 1275 ms
in increments of 5 ms and then sequences-on the faulted rail and fault-shutdown slaves according to the start-up
sequence configuration. This is repeated until the faulted rail and fault-shutdown slaves successfully achieve
regulation or for a user-selected 1, 2, 3, 4 or unlimited times. If the resequence operation is successful, the
resequence counter is reset if all of the rails that were resequenced maintain normal operation for one second.
Once shut-down-all-rails and sequence-on begin, any faults on the fault-shutdown slave rails are ignored. If there
are two or more simultaneous faults with different fault-shutdown slaves, the more conservative action is taken.
For example, if a set of rails is already on its second resequence and the device is configured to resequence
three times, and another set of rails enters the resequence state, that second set of rails is only resequenced
once. Another example – if one set of rails is waiting for all of its rails to shut down so that it can resequence,
and another set of rails enters the resequence state, the device now waits for all rails from both sets to shut
down before resequencing.
7.4.6 GPIOs
The UCD9090 has 21 GPIO pins that can function as either inputs or outputs. Each GPIO has configurable
output mode options including open-drain or push-pull outputs that can be actively driven to 3.3 V or ground.
There are an additional two pins that can be used as either inputs or PWM outputs but not as GPOs. Table 3
lists possible uses for the GPIO pins and the maximum number of each type for each use. GPIO pins can be
dependents in sequencing and alarm processing. They can also be used for system-level functions such as
external interrupts, power-goods, resets, or for the cascading of multiple devices. GPOs can be sequenced up or
down by configuring a rail without a MONx pin but with a GPIO set as an enable.
24
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
Table 3. GPIO Pin Configuration Options
PIN NAME
PIN
RAIL EN
(10 MAX)
GPI
(8 MAX)
GPO
(10 MAX)
PWM OUT
(10 MAX)
MARGIN PWM
(10 MAX)
FPWM1/GPIO5
10
X
X
X
X
X
FPWM2/GPIO6
11
X
X
X
X
X
FPWM3/GPIO7
12
X
X
X
X
X
FPWM4/GPIO8
13
X
X
X
X
X
FPWM5/GPIO9
14
X
X
X
X
X
FPWM6/GPIO10
15
X
X
X
X
X
FPWM7/GPIO11
16
X
X
X
X
X
FPWM8/GPIO12
17
X
X
X
X
X
GPI1/PWM1
22
X
X
X
GPI2/PWM2
23
X
X
X
GPIO1
4
X
X
X
GPIO2
5
X
X
X
GPIO3
6
X
X
X
GPIO4
7
X
X
X
GPIO13
18
X
X
X
GPIO14
21
X
X
X
GPIO15
24
X
X
X
GPIO16
25
X
X
X
GPIO17
26
X
X
X
TCK/GPIO18
27
X
X
X
TDO/GPIO19
28
X
X
X
TDI/GPIO20
29
X
X
X
TMS/GPIO21
30
X
X
X
7.4.7 GPO Control
The GPIOs when configured as outputs can be controlled by PMBus commands or through logic defined in
internal Boolean function blocks. Controlling GPOs by PMBus commands (GPIO_SELECT and GPIO_CONFIG)
can be used to have control over LEDs, enable switches, etc. with the use of an I2C interface. See the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference for details on controlling a
GPO using PMBus commands.
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
25
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
7.4.8 GPO Dependencies
GPIOs can be configured as outputs that are based on Boolean combinations of up to two ANDs all ORed
together (Figure 18). Inputs to the logic blocks can include the first 8 defined GPOs, GPIs and rail-status flags.
One rail status type is selectable as an input for each AND gate in a Boolean block. For a selected rail status, the
status flags of all active rails can be included as inputs to the AND gate. _LATCH rail-status types stay asserted
until cleared by a MFR PMBus command or by a specially configured GPI pin. The different rail-status types are
shown in Table 4. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for
complete definitions of rail-status types. The GPO response can be configured to have a delayed assertion or
deassertion.
Sub block repeated for each of GPI(1:7)
GPI_INVERSE(0)
GPI_POLARITY(0)
GPI_ENABLE(0)
1
AND_INVERSE(0)
_GPI(0)
GPI(0)
_GPI(1:7)
_STATUS(0:8)
_STATUS(9)
_GPO(1:7)
There is one STATUS_TYPE_SELECT for each of the two AND
gates in a boolean block
STATUS_TYPE_SELECT
STATUS(0)
OR_INVERSE(x)
Status Type 1
STATUS(1)
Sub block repeated for each of STATUS(0:8)
GPOx
STATUS_INVERSE(9)
Status Type 31
ASSERT_DELAY(x)
STATUS_ENABLE(9)
STATUS(9)
1
AND_INVERSE(1)
DE-ASSERT_DELAY(x)
_GPI(0:7)
_STATUS(0:9)
_GPO(0:7)
Sub block repeated for each of GPO(1:7)
GPO_INVERSE(0)
GPO_ENABLE(0)
1
GPO(0)
_GPO(0)
Figure 18. Boolean Logic Combinations
Figure 19. Fusion Boolean Logic Builder
26
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
Table 4. Rail-Status Types For Boolean Logic
Rail-Status Types
POWER_GOOD
IOUT_UC_FAULT
TOFF_MAX_WARN_LATCH
MARGIN_EN
TEMP_OT_FAULT
SEQ_ON_TIMEOUT_LATCH
MRG_LOW_nHIGH
TEMP_OT_WARN
SEQ_OFF_TIMEOUT_LATCH
VOUT_OV_FAULT
SEQ_ON_TIMEOUT
SYSTEM_WATCHDOG_TIMEOUT_LATCH
VOUT_OV_WARN
SEQ_OFF_TIMEOUT
IOUT_OC_FAULT_LATCH
VOUT_UV_WARN
SYSTEM_WATCHDOG_TIMEOUT
IOUT_OC_WARN_LATCH
VOUT_UV_FAULT
VOUT_OV_FAULT_LATCH
IOUT_UC_FAULT_LATCH
TON_MAX_FAULT
VOUT_OV_WARN_LATCH
TEMP_OT_FAULT_LATCH
TOFF_MAX_WARN
VOUT_UV_WARN_LATCH
TEMP_OT_WARN_LATCH
IOUT_OC_FAULT
VOUT_UV_FAULT_LATCH
IOUT_OC_WARN
TON_MAX_FAULT_LATCH
7.4.8.1 GPO Delays
The GPOs can be configured so that they manifest a change in logic with a delay on assertion, deassertion, both
or none. GPO behavior using delays will have different effects depending if the logic change occurs at a faster
rate than the delay. On a normal delay configuration, if the logic for a GPO changes to a state and reverts back
to previous state within the time of a delay then the GPO will not manifest the change of state on the pin. In
Figure 20 the GPO is set so that it follows the GPI with a 3ms delay at assertion and also at de-assertion. When
the GPI first changes to high logic state, the state is maintained for a time longer than the delay allowing the
GPO to follow with appropriate logic state. The same goes for when the GPI returns to its previous low logic
state. The second time that the GPI changes to a high logic state it returns to low logic state before the delay
time expires. In this case the GPO does not change state. A delay configured in this manner serves as a glitch
filter for the GPO.
3ms
3ms
GPI
GPO
1ms
Figure 20. GPO Behavior When Not Ignoring Inputs During Delay
The Ignore Input During Delay bit allows to output a change in GPO even if it occurs for a time shorter than the
delay. This configuration setting has the GPO ignore any activity from the triggering event until the delay expires.
Figure 21 represents the two cases for when ignoring the inputs during a delay. In the case in which the logic
changes occur with more time than the delay, the GPO signal looks the same as if the input was not ignored.
Then on a GPI pulse shorter than the delay the GPO still changes state. Any pulse that occurs on the GPO when
having the Ignore Input During Delay bit set will have a width of at least the time delay.
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
27
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
3ms
www.ti.com
3ms
3ms
3ms
GPI
GPO
1ms
Figure 21. GPO Behavior When Ignoring Inputs During Delay
7.4.8.2 State Machine Mode Enable
When this bit within the GPO_CONFIG command is set, only one of the AND path will be used at a given time.
When the GPO logic result is currently TRUE, AND path 0 will be used until the result becomes FALSE. When
the GPO logic result is currently FALSE, AND path 1 will be used until the result becomes TRUE. This provides a
very simple state machine and allows for more complex logical combinations.
7.4.9 GPI Special Functions
There are five special input functions for which GPIs can be used. There can be no more than one pin assigned
to each of these functions.
•
•
•
•
GPI Fault Enable - When set, the de-assertion of the GPI is treated as a fault.
Latched Statuses Clear Source - When a GPO uses a latched status type (_LATCH), you can configure a
GPI that will clear the latched status.
Input Source for Margin Enable - When this pin is asserted, all rails with margining enabled will be put in a
margined state (low or high).
Input Source for Margin Low/Not-High - When this pin is asserted all margined rails are set to margin low
as long as the margin enable is asserted. When this pin is de-asserted the rails will be set to Margin High.
The polarity of GPI pins can be configured to be either active low or active high. The first 3 GPIs that are defined
regardless of their main purpose will be used for the PIN_SELECTED_RAIL_STATES command.
7.4.10 Power-Supply Enable Pins
Each GPIO can be configured as a rail-enable pin with either active-low or active-high polarity. Output mode
options include open-drain or push-pull outputs that can be actively driven to 3.3 V or ground. During reset, the
GPIO pins are high-impedance except for FPWM/GPIO pins (pin 10 through pin 17), which are driven low.
External pull-down resistors or pull-up resistors can be tied to the enable pins to hold the power supplies OFF
during reset. The UCD9090 can support a maximum of 10 enable pins.
NOTE
GPIO pins that have FPWM capability (pin 10 through pin 17) must be used only as
power-supply enable signals if the signal is active high.
7.4.11 Cascading Multiple Devices
7.4.11.1 Connecting the GPIO Pin to a PMBus_CNTRL Pin
A GPIO pin can be used to coordinate multiple controllers by using it as a power-good output from one device
and connecting it to the PMBus_CNTRL input pin of another device. This configuration creates a master-slave
relationship among multiple devices. During the startup operation, the slave controllers initiate the start
sequences after the master controller has completed its start sequence and all rails have reached regulation
voltages. During the shutdown operation, as soon as the master starts to sequence-off, it sends the shut-down
signal to its slaves.
28
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
A shutdown event on one or more of the master rails can initiate shutdown events of the slave devices. The
master shutdowns can be initiated intentionally or by a fault condition. This method coordinates multiple
controllers, but it does not enforce interdependency between rails within a single controller.
7.4.11.2 Connecting the GPIO Pin to a MON Pin
Another method to cascade multiple devices is to connect the power-good output of the first device to a MON pin
of the second device, connect the power-good output of the second device to a MON pin of the third device, and
so on. As an option, connect the power-good output of the last device to a MON pin of the first device. The rails
controlled by a device have dependency on the power-good output of the previous device. This method allows
the rails controlled by multiple devices to be sequenced.
The de-assertion of a power-good output can trigger an undervoltage fault of the next device in the chain. The
undervoltage fault response can be configured to shut down other rails controlled by the same device. This
process ensures that when one rail has fault shutdown, other rails controlled by other devices can be shut down
in the same way.
The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are
regulating at their programmed voltage. The UCD9090 allows GPIOs to be configured to respond to a desired
subset of power-good signals.
7.4.12 PWM Outputs
7.4.12.1 FPWM1-8
Pins 10-17 can be configured as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to
125 MHz. FPWMs can be configured as closed-loop margining outputs, fan controllers or general-purpose
PWMs.
Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a
PWM output and the other pin can be used as a general purpose output (GPO). The FPWM pins are actively
driven low from reset when used as GPOs.
The frequency settings for the FPWMs apply to pairs of pins:
• FPWM1 and FPWM2 – same frequency
• FPWM3 and FPWM4 – same frequency
• FPWM5 and FPWM6 – same frequency
• FPWM7 and FPWM8 – same frequency
If an FPWM pin from a pair is not used while its companion is set up to function as a PWM, it is recommended to
configure the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the
system. By setting an FPWM, it automatically enables the other FPWM within the pair if it was not configured for
any other functionality.
The frequency for the FPWM is derived by dividing down a 250MHz clock. To determine the actual frequency to
which an FPWM can be set, must divide 250MHz by any integer between 2 and (214-1).
The FPWM duty cycle resolution is dependent on the frequency set for a given FPWM. Once the frequency is
known the duty cycle resolution can be calculated as Equation 1.
Change per Step (%)FPWM = frequency / (250 × 106 × 16) × 100
(1)
Take for an example determining the actual frequency and the duty cycle resolution for a 75MHz target
frequency.
1.
2.
3.
4.
Divide 250 MHz by 75 MHz to obtain 3.33.
Round off 3.33 to obtain an integer of 3.
Divide 250 MHz by 3 to obtain actual closest frequency of 83.333 MHz.
Use Equation 1 to determine duty cycle resolution to obtain 2.0833% duty cycle resolution.
7.4.12.2 PWM1-2
Pins 22 and 23 can be used as GPIs or PWM outputs. These PWM outputs have an output frequency of 0.93 Hz
to 7.8125 MHz.
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
29
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
The frequency for PWM1 and PWM2 is derived by dividing down a 15.625-MHz clock. To determine the actual
frequency to which these PWMs can be set, must divide 15.625 MHz by any integer between 2 and (224-1). The
duty cycle resolution will be dependent on the set frequency for PWM1 and PWM2.
The PWM1 or PWM2 duty cycle resolution is dependent on the frequency set for the given PWM. Once the
frequency is known the duty cycle resolution can be calculated as Equation 2
Change per Step (%)PWM1/2 = frequency / 15.625 × 106 × 100
(2)
To determine the closest frequency to 1MHz that PWM1 can be set to calculate as the following:
1.
2.
3.
4.
Divide 15.625 MHz by 1 MHz to obtain 15.625.
Round off 15.625 to obtain an integer of 16.
Divide 15.625 MHz by 16 to obtain actual closest frequency of 976.563 kHz.
Use Equation 2 to determine duty cycle resolution to obtain 6.25% duty cycle resolution.
All frequencies below 238 Hz will have a duty cycle resolution of 0.0015%.
7.4.13 Programmable Multiphase PWMs
The FPWMs can be aligned with reference to their phase. The phase for each FPWM is configurable from 0° to
360°. This provides flexibility in PWM-based applications such as power-supply controller, digital clock
generation, and others. See an example of four FPWMs programmed to have phases at 0°, 90°, 180° and 270°
(Figure 22).
Figure 22. Multiphase PWMs
7.4.14 Margining
Margining is used in product validation testing to verify that the complete system works properly over all
conditions, including minimum and maximum power-supply voltages, load range, ambient temperature range,
and other relevant parameter variations. Margining can be controlled over PMBus using the OPERATION
command or by configuring two GPIO pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG
command in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference describes
different available margining options, including ignoring faults while margining and using closed-loop margining to
trim the power-supply output voltage one time at power up.
7.4.14.1 Open-Loop Margining
Open-loop margining is done by connecting a power-supply feedback node to ground through one resistor and to
the margined power supply output (VOUT) through another resistor. The power-supply regulation loop responds to
the change in feedback node voltage by increasing or decreasing the power-supply output voltage to return the
feedback voltage to the original value. The voltage change is determined by the fixed resistor values and the
voltage at VOUT and ground. Two GPIO pins must be configured as open-drain outputs for connecting resistors
from the feedback node of each power supply to VOUT or ground.
30
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
MON(1:10)
3.3V
UCD9090
POWER
SUPPLY
10k W
GPIO(1:10)
VOUT
/EN
3.3V
Vout
VFB
Rmrg_HI
V FB
GPIO
GPIO
“0” or “1”
VOUT
“0” or “1”
Rmrg_LO
3. 3V
POWER
SUPPLY
10k W
/EN
Vout
VOUT
VFB
VFB
Rmrg_HI
VOUT
.
3.3V
Rmrg_LO
Open Loop Margining
Figure 23. Open-Loop Margining
7.4.14.2 Closed-Loop Margining
Closed-loop margining uses a PWM or FPWM output for each power supply that is being margined. An external
RC network converts the FPWM pulse train into a DC margining voltage. The margining voltage is connected to
the appropriate power-supply feedback node through a resistor. The power-supply output voltage is monitored,
and the margining voltage is controlled by adjusting the PWM duty cycle until the power-supply output voltage
reaches the margin-low and margin-high voltages set by the user. The voltage setting resolutions will be the
same that applies to the voltage measurement resolution (Table 2). The closed loop margining can operate in
several modes (Table 5). Given that this closed-loop system has feed back through the ADC, the closed-loop
margining accuracy will be dominated by the ADC measurement. The relationship between duty cycle and
margined voltage is configurable so that voltage increases when duty cycle increases or decreases. For more
details on configuring the UCD9090 for margining, see the Voltage Margining Using the UCD9012x application
note (SLVA375).
Table 5. Closed Loop Margining Modes
MODE
DESCRIPTION
DISABLE
Margining is disabled.
ENABLE_TRI_STATE
When not margining, the PWM pin is set to high impedance state.
ENABLE_ACTIVE_TRIM
When not margining, the PWM duty-cycle is continuously adjusted to keep the voltage at
VOUT_COMMAND.
ENABLE_FIXED_DUTY_CYCLE
When not margining, the PWM duty-cycle is set to a fixed duty-cycle.
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
31
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
MON(1:10)
3.3V
UCD9090
POWER
SUPPLY
/EN
VOUT
10k W
GPIO
Vout
VFB
250 kHz – 1MHz
FPWM 1
R1
VFB
Vmarg
R3
R4
C1
Closed Loop
Margining
R2
Figure 24. Closed-Loop Margining
7.4.15 Run Time Clock
The Run-Time clock is given in milliseconds and days. Both are 32-bit numbers. This value is saved in
nonvolatile memory whenever a STORE_DEFAULT_ALL command is issued. It can also be saved when a
power-down condition is detected (See Brownout Function).
The Run-Time clock may also be written. This allows the clock to be periodically corrected by the host. It also
allows the clock to be initialized to the actual, absolute time in years (e.g., March 23, 2010). The user must
translate the absolute time to days and milliseconds.
The three usage scenarios for the Run-Time Clock are:
1. Time from restart (reset or power-on) – the Run-Time Clock starts from 0 each time a restart occurs
2. Absolute run-time, or operating time – the Run-Time Clock is preserved across restarts, so you can keep
up with the total time that the device has been in operation (Note: “Boot time” is not part of this. Only normal
operation time is captured here.)
3. Local time – an external processor sets the Run-Time Clock to real-world time each time the device is
restarted.
The Run-Time clock value is used to timestamp any faults that are logged.
7.4.16 System Reset Signal
The UCD9090 can generate a programmable system-reset pulse as part of sequence-on. The pulse is created
by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach
their respective POWER_GOOD_ON levels plus a programmable delay time. The system-reset delay duration
can be programmed as shown in Table 6. See an example of two SYSTEM RESET signals Figure 25. The first
SYSTEM RESET signal is configured so that it de-asserts on Power Good On and it asserts on Power Good Off
after a given common delay time. The second SYSTEM RESET signal is configured so that it sends a pulse after
a delay time once Power Good On is achieved. The pulse width can be configured between 0.001s to 32.256s.
See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for pulse width
configuration details.
Power Good On
Power Good On
Power Good Off
POWER GOOD
Delay
Delay
Delay
SYSTEM RESET
configured without pulse
Pulse
Pulse
SYSTEM RESET
configured with pulse
Figure 25. System Reset With and Without Pulse Setting
32
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
UCD9090
www.ti.com
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
The system reset can react to watchdog timing. In Figure 26 The first delay on SYSTEM RESET is for the initial
reset release that would get a CPU running once all necessary voltage rails are in regulation. The watchdog is
configured with a Start Time and a Reset Time. If these times expire without the WDI clearing them then it is
expected that the CPU providing the watchdog signal is not operating. The SYSTEM RESET is toggled either
using a Delay or GPI Tracking Release Delay to see if the CPU recovers.
Power Good On
POWER GOOD
WDI
Watchdog
Start Time
Watchdog
Reset Time
Watchdog
Start Time
Delay
Watchdog
Reset Time
SYSTEM RESET
Delay or
GPI Tracking Release Delay
Figure 26. System Reset With Watchdog
Table 6. System-Reset Delay
DELAY
0 ms
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1.02 s
2.05 s
4.10 s
8.19 s
16.38 s
32.8 s
7.4.17 Watch Dog Timer
A GPI and GPO can be configured as a watchdog timer (WDT). The WDT can be independent of power-supply
sequencing or tied to a GPIO functioning as a watchdog output (WDO) that is configured to provide a systemreset signal. The WDT can be reset by toggling a watchdog input (WDI) pin or by writing to
SYSTEM_WATCHDOG_RESET over I2C. The WDI and WDO pins are optional when using the watchdog timer.
The WDI can be replaced by SYSTEM_WATCHDOG_RESET command and the WDO can be manifested
through the Boolean Logic defined GPOs or through the System Reset function.
The WDT can be active immediately at power up or set to wait while the system initializes. Table 7 lists the
programmable wait times before the initial timeout sequence begins.
Submit Documentation Feedback
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
33
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Table 7. WDT Initial Wait Time
WDT INITIAL WAIT TIME
0 ms
100 ms
200 ms
400 ms
800 ms
1.6 s
3.2 s
6.4 s
12.8 s
25.6 s
51.2 s
102 s
205 s
410 s
819 s
1638 s
The watchdog timeout is programmable from 0.001s to 32.256s. See the UCD90xxx Sequencer and System
Health Controller PMBus Command Reference for details on configuring the watchdog timeout. If the WDT times
out, the UCD9090 can assert a GPIO pin configured as WDO that is separate from a GPIO defined as systemreset pin, or it can generate a system-reset pulse. After a timeout, the WDT is restarted by toggling the WDI pin
or by writing to SYSTEM_WATCHDOG_RESET over I2C.
WDI