VCA2617
SBOS326 −AUGUST 2005
Dual, Variable Gain Amplifier
FEATURES
DESCRIPTION
D INDEPENDENT CHANNEL CONTROLS:
The VCA2617 is a dual-channel, continuously variable,
voltage-controlled gain amplifier well-suited for a variety of
ultrasound systems as well as applications in proximity
detectors and test equipment. The VCA2617 uses a true
variable-gain amplifier architecture, achieving very good
noise performance at low gains, while not sacrificing high gain
distortion performance.
− Gain Range: 48dB
− Clamping Levels
− Post-Gain: 0, +6dB
D
D
D
D
D
D
D
D
LOW NOISE: 4.1nV//Hz
LOW POWER: 52mW/Channel
BANDWIDTH: 50MHz
HARMONIC DISTORTION: −53dBc at 5MHz
CROSSTALK: −61dB at 5MHz
5V SINGLE SUPPLY
POWER-DOWN MODE
Following a linear-in-dB response, the VCA2617 gain can be
varied over a 48dB range with a 0.2V to 2.3V control voltage.
Two separate high-impedance control inputs allow for a
channel independent variation of the gains. Each channel of
the VCA2617 can be configured to provide a gain range of
−10dB to 38dB, or −16dB to 32dB, depending on the gain
select pin (HG). This post-gain feature allows the user to
optimize the output swing of VCA2617 for a variety of
high-speed analog-to-digital converters (ADC). As a means to
improve system overload recovery time, the VCA2617 also
provides an internal clamping circuitry where an externally
applied voltage sets the desired output clamping level.
SMALL QFN-32 PACKAGE (5x5mm)
APPLICATIONS
D MEDICAL AND INDUSTRIAL ULTRASOUND
D
D
SYSTEMS
− Suitable for 10-Bit and 12-Bit Systems
TEST EQUIPMENT
SONAR
The VCA2617 operates on a single +5V supply while
consuming only 52mW per channel. It is available in a small
QFN-32 package (5x5mm).
RELATED PRODUCTS
V CNTLA
PART NUMBER
DESCRIPTION
VCA2615
Dual, Low-Noise, Variable-Gain Amplifier with
Preamp
V CLMPA
Gain
Select A
C EXTA
Out A+
In A+
V−I
Clamping
Circuitry
I−V
Out A−
In A−
Out B+
In B+
V−I
Clamping
Circuitry
I−V
Out B−
In B−
V CNTLB
V CLMPB
Gain
Select B
C EXTB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright 2005, Texas Instruments Incorporated
! !
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SBOS326 −AUGUST 2005
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
VCA2617 Analog Input . . . . . . . . . . . . . . . . . −0.3V to (+VS + 0.3V)
Logic Input . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to (+VS + 0.3V)
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −40°C to +150°C
(1) Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
This integrated circuit can be damaged by ESD.
Texas Instruments recommends that all
integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
VCA2617
QFN−32
RHB
−40°C to +85°C
VCA2617
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
VCA2617RHBT
Tape and Reel, 250
VCA2617RHBR
Tape and Reel, 3000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
2
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SBOS326 −AUGUST 2005
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, VDD = 5V, load resistance = 500Ω on each output to ground, differential output (1VPP), CA, CB = 3.9µF,
single-ended input configuration, fIN = 5MHz, HG = Low (High-Gain Mode), VCNTL = 2.3V, unless otherwise noted.
VCA2617
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VARIABLE GAIN AMPLIFIER
Input Resistance
Input Capacitance
Maximum Input Voltage
Differential
Single-Ended
Input Voltage Noise
Input Current Noise
Noise Figure
Input Common-Mode Voltage
Bandwidth
Clipping Voltage Range (VCLMP)
Clipping Voltage Variation
Maximum Capacitive Output Loading
Slew Rate
Maximum Output Signal(1)
Output Common-Mode Voltage
Output Impedance
Output Short-Circuit Current
2nd-Harmonic Distortion
3rd-Harmonic Distortion
Overload Distortion (2nd-Harmonic)
Crosstalk
Delay Matching
Single-Ended
300
8
kΩ
pF
2.0
1.0
4.1
1
13.3
2.5
50
0.25 to 2.6
±75
80
100
6
2.5
3
60
−53
−62
−40
−61
±1
VPP
VPP
nV/√Hz
pA/√Hz
dB
V
MHz
V
mV
pF
V/µs
VPP
V
Ω
mA
dBc
dBc
dBc
dB
ns
Linear Operation(1); Each Input
Gain = 45dB, RS = 0Ω
Independent of Gain
Internal
VCLMP = 0.5V, VCAOUT = 1.0VPP
50Ω in Series
at 5MHz, Single-Ended, Either Output
VOUT = 1VPP, VCNTL = 1.5V
VOUT = 1VPP, VCNTL = 1.5V
Input Signal = 1VPP, VCNTL = 2V
−43
−43
ACCURACY
Gain Slope
Gain Error(2)
Gain Range
Gain Range (HG)
Output Offset Voltage, Differential
Channel-to-Channel Gain Matching
VCNTL = 0.4V to 2.0V
VCNTL = 0.4V to 2.0V
VCNTL = 0.2V to 2.3V
VCNTL = 0.4V to 2.0V
HG = 0 (+6dB); VGA High Gain; VCNTL = 0.2V to 2.3V
HG = 1 (0dB); VGA Low Gain; VCNTL = 0.2V to 2.3V
VCNTL = 0.4V to 2.0V
22
±0.9
48
35.5
−10 to +38
−16 to +32
±50
±0.8
42dB Gain Change; to 90% Signal Level
0.2 to 2.3
1
0.5
−2
+2
dB/V
dB
dB
dB
dB
dB
mV
dB
GAIN CONTROL INTERFACE (VCNTL)
Input Voltage Range
Input Resistance
Response Time
V
MΩ
µs
DIGITAL INPUTS(3), (4)
(HGA, HGB, PD)
VIH, High-Level Input Voltage
VIL, Low-Level Input Voltage
Input Resistance
Input Capacitance
2.0
0.8
1
5
V
V
MΩ
pF
POWER SUPPLY
Supply Voltage
Power Dissipation
Power-Down
Power-Up Response Time
Power-Down Response Time
4.75
5.0
105
22
25
2
5.25
125
V
mW
mW
µs
µs
+85
°C
°C/W
°C/W
THERMAL CHARACTERISTICS
Temperature Range
Thermal Resistance, qJA
qJC
Ambient, Operating
Soldered Pad; Four-Layer PCB with Thermal Vias
−40
36.7
4.0
(1) 2nd, 3rd-harmonic distortion less than or equal to −30dBc.
(2) Referenced to best fit dB-linear curve.
(3) Parameters ensured by design; not production tested.
(4) Do not leave inputs floating; no internal pull-up/pull-down resistors.
3
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SBOS326 −AUGUST 2005
INA−
NC
CA2
CA1
VDDA
GNDA
Out A−
Out A+
32
31
30
29
28
27
26
25
PIN CONFIGURATION
INA +
1
24
VCNTLA
NC
2
23
VCLMPA
VDDR
3
22
HGA
21
NC
20
PD
VCA2617
(Thermal Pad tied to
Ground Potential)
16
VCNTLB
OutB+
17
15
8
OutB−
INB+
14
VCLMPB
GNDB
18
13
7
VDDB
NC
CB1
HGB
12
19
11
6
CB2
GNDR
10
5
NC
VCM
9
4
INB−
VB
PIN DESCRIPTIONS
4
PIN
DESIGNATOR
1
INA+
PIN
DESIGNATOR
Channel A +Input
DESCRIPTION
17
VCNTLB
Channel B Gain Control Voltage Input
No Internal Connection
18
VCLMPB
Channel B Clamp Voltage
Reference Supply
19
HGB
Bias Voltage, 0.1µF Bypass Capacitor
20
PD
Power Down (Active High)
Common-mode Voltage, 0.1µF Bypass Capacitor
21
NC
No Internal Connection
Internal Reference Ground
22
HGA
No Internal Connection
23
2
NC
3
4
VDDR
VB
5
VCM
6
GNDR
7
NC
8
INB+
Channel B+ Input
24
VCLMPA
VCNTLA
DESCRIPTION
Channel B High/Low Output Gain (High = Low Gain)
Channel A High/Low Output Gain (High = Low Gain)
Channel A Clamp Voltage
Channel A Gain Control Voltage Input
9
INB−
Channel B− Input
25
OutA+
Channel A+ Output
10
NC
No Internal Connection
26
OutA−
Channel A− Output
11
CB2
Channel B, External Coupling Capacitor
27
GNDA
Channel A Ground
12
CB1
Channel B, External Coupling Capacitor
28
VDDA
Channel A Supply
13
VDDB
Channel B Supply
29
CA1
Channel A; External Coupling Capacitor
14
GNDB
Channel B Ground
30
CA2
Channel A; External Coupling Capacitor
15
OutB−
Channel B− Output
31
NC
No Internal Connection
16
OutB+
Channel B+ Output
32
INA−
Channel A− Input
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS
GAIN vs VCNTL
GAIN ERROR vs VCNTL
2.0
1.5
HG = 0
1.0
HG = 0
HG = 1
Gain Error (dB)
0.5
0
HG = 1
−0.5
−1.0
VCNTL (V)
40
1.5
30
1.0
GAIN vs VCNTL vs TEMPERATURE
2.0
1.9
1.8
1.7
1.6
1.5
1.4
2.0
1.9
1.8
1.7
1.6
1.4
GAIN ERROR vs VCNTL vs TEMPERATURE
2.0
1.5
−40_ C
20
+25_ C
+85_ C
−40_C
1.0
Gain Error (dB)
30
25
+25_C
0.5
0
+85_C
−0.5
0
−5
−10
−1.0
−15
−2.0
VCNTL (V)
Figure 5
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
−1.5
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
Gain (dB)
1.3
Figure 4
35
10
5
1.2
VCNTL (V)
Figure 3
15
1.1
1.0
0.9
0.8
0.7
−2.0
0.6
−1.5
VCNTL (V)
45
40
1.3
1MHz
2MHz
5MHz
10MHz
−1.0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
−10
−0.5
1.5
1MHz
2MHz
5MHz
10MHz
0
0.5
10
0.5
0.4
20
−20
GAIN ERROR vs VCNTL vs FREQUENCY
2.0
Gain Error (dB)
Gain (dB)
Figure 2
GAIN vs VCNTL vs FREQUENCY
0
1.2
VCNTL (V)
Figure 1
50
1.1
1.0
0.9
0.8
0.7
0.6
−2.0
0.5
−1.5
0.4
60
55
50
45
40
35
30
25
20
15
10
5
0
−5
−10
−15
−20
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
Gain (dB)
All specifications at TA = +25°C, VDD = 5V, load resistance = 500Ω on each output to ground, differential output (1VPP), CA, CB = 3.9µF,
single-ended input configuration, fIN = 5MHz, HG = Low (High-Gain Mode), VCNTL = 2.3V, unless otherwise noted.
VCNTL (V)
Figure 6
5
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VDD = 5V, load resistance = 500Ω on each output to ground, differential output (1VPP), CA, CB = 3.9µF,
single-ended input configuration, fIN = 5MHz, HG = Low (High-Gain Mode), VCNTL = 2.3V, unless otherwise noted.
GAIN MATCHING, CHA to CHB
GAIN MATCHING, CHA to CHB
70
100
VCNTL = 0.4V
VCNTL = 2.0V
90
60
80
70
60
40
Units
Units
50
30
50
40
30
20
20
10
10
0
−1.92
−1.76
−1.60
−1.44
−1.28
−1.12
−0.96
−0.80
−0.64
−0.48
−0.32
−0.16
0.00
0.16
0.32
0.48
0.64
0.80
0.96
1.12
1.28
1.44
1.60
1.76
1.92
−1.80
−1.65
−1.50
−1.35
−1.20
−1.05
−0.90
−0.75
−0.60
−0.45
−0.30
−0.15
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
1.65
1.80
0
Delta Gain (dB)
Delta Gain (dB)
Figure 7
Figure 8
GAIN vs FREQUENCY
GAIN vs FREQUENCY
40
45
3.9µF
HG = 0, VCNTL = 2.3V
40
39
0.1µF
35
38
HG = 1, VCNTL = 2.3V
37
25
Gain (dB)
Gain (dB)
30
20
15
10
HG = 0, VCNTL = 0.7V
36
4700pF
0.022µF
35
34
5
33
0
32
−5
HG = 1, VCNTL = 0.7V
−10
0.1
1
10
31
0.1
100
1
OUTPUT−REFERRED NOISE vs VCNTL
INPUT−REFERRED NOISE vs VCNTL
1000
1000
100
HG = 1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
10
VCNTL (V)
Figure 11
HG = 1
100
HG = 0
10
1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
HG = 0
Noise (nV/√Hz)
Noise (nV/√Hz)
100
Figure 10
Figure 9
6
10
Frequency (MHz)
Frequency (MHz)
VCNTL (V)
Figure 12
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VDD = 5V, load resistance = 500Ω on each output to ground, differential output (1VPP), CA, CB = 3.9µF,
single-ended input configuration, fIN = 5MHz, HG = Low (High-Gain Mode), VCNTL = 2.3V, unless otherwise noted.
INPUT−REFERRED NOISE vs FREQUENCY
(Hi VGA Gain)
NOISE FIGURE vs VCNTL
100
10
Noise (nV/√Hz)
Noise nV/√Hz
HG = 1
HG = 0
10
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
1
−50
1
Frequency (MHz)
Figure 13
Figure 14
DISTORTION vs FREQUENCY
(2nd−Harmonic, VCNTL = 2.3V)
DISTORTION vs FREQUENCY
(3rd−Harmonic, VCNTL = 2.3V)
−50
−52
−52
−54
−54
HG = 1
−56
Distortion (dB)
Distortion (dB)
10
VCNTL (V)
−58
−60
−62
−64
HG = 0
−66
−56
−60
−62
−64
−66
−68
−68
−70
−70
1
10
−25
HG = 1
−58
HG = 0
1
10
Frequency (MHz)
Frequency (MHz)
Figure 15
Figure 16
DISTORTION vs VCNTL
(Lo VGA Gain)
DISTORTION vs VCNTL
(Hi VGA Gain)
−40
−30
Distortion (dB)
−40
−45
−50
−55
2nd−Harmonic
−50
−55
−60
3rd−Harmonic
−60
VCNTL (V)
VCNTL (V)
Figure 17
Figure 18
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
−65
0.8
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
3rd−Harmonic
0.9
−65
0.8
Distortion (dB)
−45
2nd−Harmonic
−35
7
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VDD = 5V, load resistance = 500Ω on each output to ground, differential output (1VPP), CA, CB = 3.9µF,
single-ended input configuration, fIN = 5MHz, HG = Low (High-Gain Mode), VCNTL = 2.3V, unless otherwise noted.
DISTORTION vs RESISTIVE LOAD
DISTORTION vs VCA OUTPUT
−40
−40
−45
−45
Distortion (dB)
Distortion (dB)
−50
−55
2nd−Harmonic
−60
−65
−50
2nd−Harmonic
−55
−60
−70
3rd−Harmonic
−75
VCNTL (V)
VCNTL (V)
Figure 21
Figure 22
TOTAL POWER vs TEMPERATURE
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
2.3
2.2
2.1
2.0
1.9
1.8
1.7
−75
1.6
600
550
1MHz
2MHz
5MHz
10MHz
−71
−75
1.4
500
−69
−73
1.3
450
−67
−73
1.2
750
HG = 1
1.1
700
−69
−65
2.0
−67
−63
1.9
HG = 0
1.0
2.3
−61
0.9
650
−61
0.8
2.2
−59
Crosstalk (dB)
−57
−59
−71
CROSSTALK vs VCNTL
−55
−57
1.5
Crosstalk (dB)
Figure 20
CROSSTALK vs VCNTL
−65
2.1
Figure 19
−63
400
Resistance (Ω)
VCA Output (VPP)
−55
350
300
250
200
150
100
50
−70
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
3rd−Harmonic
0.5
−80
−65
DISTORTION vs TEMPERATURE
−80
105.8
105.7
−75
3rd−Harmonic
105.5
Distortion (dB)
Power (mW)
105.6
105.4
105.3
105.2
105.1
10
20 30
40
Temperature (_C)
Figure 23
8
−65
−60
105.0
104.9
−40 −30 −20 −10 0
−70
50 60
70 80
2nd−Harmonic
−55
−40 −30 −20 −10 0 10
20 30
40
Temperature (_C)
Figure 24
50 60
70 80
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VDD = 5V, load resistance = 500Ω on each output to ground, differential output (1VPP), CA, CB = 3.9µF,
single-ended input configuration, fIN = 5MHz, HG = Low (High-Gain Mode), VCNTL = 2.3V, unless otherwise noted.
VCLMP vs VOUT
(150mVPP, S/E Input)
2ND−HARMONIC DISTORTION
−20
−28
VOUT (PP)
−32
−36
−40
−44
0.50
0.75
1.00
VCLMP (V)
VIN (VPP)
Figure 25
Figure 26
2ND−HARMONIC DISTORTION vs VCNTL
(Differential Input)
−45
−45
−50
−50
VOUT (PP)
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
HG = 1
1.3
−75
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.1
1.0
0.9
0.8
−75
−70
3rd−Harmonic
0.9
−70
−65
1.2
−65
HG = 0
−60
0.8
−60
−55
1.1
2nd−Harmonic
1.0
Distortion (dBc)
−55
1.2
Distortion (dBc)
DISTORTION vs VOUT
(Differential Input)
1.5
−48
0.25
1.4
Distortion (dB)
−24
6.2
5.8
5.4
5.0
4.6
4.2
HG = 0
3.8
3.4
3.0
2.6
2.2
1.8
1.4
HG = 1
1.0
0.6
0.2
−0.2
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VCNTL (V)
Figure 27
Figure 28
3RD−HARMONIC DISTORTION vs VCNTL
(Differential Input)
DISTORTION vs RESISTIVE LOAD
(Differential)
−45
−30
HG = 1
−35
−50
2nd−Harmonic
Distortion (dB)
−55
−60
−65
−50
−55
VCNTL (V)
Figure 29
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
−65
0.9
−75
−45
−60
HG = 0
−70
0.8
Distortion (dBc)
−40
−70
3rd−Harmonic
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750
Resistance (Ω)
Figure 30
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VDD = 5V, load resistance = 500Ω on each output to ground, differential output (1VPP), CA, CB = 3.9µF,
single-ended input configuration, fIN = 5MHz, HG = Low (High-Gain Mode), VCNTL = 2.3V, unless otherwise noted.
OUTPUT IMPEDANCE vs FREQUENCY
GROUP DELAY vs FREQUENCY
100
25
Group Delay (ns)
ROUT (Ω)
23
10
21
19
17
1
15
0.1
1
10
100
1
Frequency (MHz)
Figure 32
Figure 31
2V
0V
1VPP
VGA Output (V)
VCNTL (V)
GAIN CONTROL TRANSIENT RESPONSE
Time (0.4µs/div)
Figure 33
10
10
Frequency (MHz)
100
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Table 1. Gain and Noise Performance of Various
VCA Blocks
THEORY OF OPERATION
The VCA2617 is a dual-channel variable gain amplifier
(VGA) with each channel being independant. The VGA is
a true variable-gain amplifier, achieving lower noise output
at lower gains. The output amplifier has two gains, allowing
for further optimization with different analog-to-digital
converters. Figure 34 shows a simplified block diagram of
a single channel of the dual-channel system. The VGA can
be powered down in order to conserve system power when
necessary.
BLOCK
GAIN (Loss) dB
NOISE nV/√Hz
Buffer
0
3.9
Attenuator (VCA2619)
0
2.2
Attenuator (VCA2619)
−40
2.2
VCA1 (VCA2617)
40
4.1
VCA1 (VCA2617)
0
90
VCA1 (VCA2619)
40
3.9
When the block diagram shown in Figure 34 has a gain of
40dB, the noise referred to the input (RTI) is:
Total Noise (RTI) + 4.1nVń ǸHz
(1)
VGA
Figure 34. Simplified Block Diagram of VCA2617
When the block diagram shown in Figure 35 has the
combined gain of 60dB, the noise referred to the input
(RTI) is given by the expression:
Total Noise (RTI) +
Ǹ(Buffer Noise)2 ) (ATTEN Noise)2 ) (VCA Noise)2
VGA—OVERVIEW
+
The VGA that is used with the VCA2617 is a true
variable-gain amplifier; as the gain is reduced, the noise
contribution from the VGA itself is also reduced. This
design is in contrast with another popular device
architecture (used by the VCA2619), where an effective
VCA characteristic is obtained by a voltage-variable
attenuator succeeded by a fixed-gain amplifier. At the
highest gain, systems with either architecture are
dominated by the noise produced at the input to either the
fixed or variable gain amplifier. At low gains, however, the
noise output is dominated by the contribution from the
VGA. Therefore, the overall system with lower VGA gain
will produce less noise.
The following example will illustrate this point. Figure 34
shows a block diagram of the variable-gain amplifier;
Figure 35 shows a block diagram of a variable attenuation
attenuator followed by a fixed gain amplifier. For purposes
of this example, let us assume the performance
characteristics shown in Table 1; these values are the
typical performance data of the VCA2617 and the
VCA2619.
Buffer
ATTENUATOR
Ǹ(3.9)2 ) (2.2)2 ) (3.9)2
+ 5.9nVń ǸHz
(2)
Repeating the above measurements for both VCA
configurations when the overall gain is 10dB yields the
following results:
For the VCA with a variable gain amplifier (Figure 34):
Total Noise (RTI) + 90nVń ǸHz
(3)
For the VCA with a variable attenuation attenuator
(Figure 35):
Total Noise +
Ǹ(3.9)2 ) (2.2) 2 ) (2.0ń0.10)2
+ 14nVń ǸHz
(4)
The VGA has a continuously-variable gain range of 48dB
with the ability to select either of two options. The gain of
the VGA can either be varied from −10dB to 38dB, or from
−16dB to 32dB. The VGA output can be programmed to
clip at a predetermined voltage that is selected by the user.
When the user applies a voltage to the VCLMP-pin, the
output will have a peak-to-peak voltage that is given by the
graph shown in Figure 26.
Amplifier
Figure 35. Block Diagram of Older VCA Models
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VOLTAGE-CONTROLLED AMPLIFIER (VCA)—
DETAIL
is fixed, will not show diminished noise in this manner.
Refer to Table 2, which shows a comparison between the
noise performance at different gains for the VCA2617 and
the older VCA2619.
Figure 36 shows a simplified schematic of the VCA. The
VCA2617 is a true voltage-controlled amplifier, with the
gain expressed in dB directly proportional to a control
signal. This architecture compares to the older VCA
products where a voltage-controlled attenuator was
followed by a fixed-gain amplifier. With a variable-gain
amplifier, the output noise diminishes as the gain reduces.
A variable-gain amplifier, where the output amplifier gain
Table 2. Noise vs Gain (RG = 0)
NOISE RTI (nV/√Hz)
PRODUCT
GAIN (dB)
VCA2617
40
4.1
VCA2617
0
100
VCA2619
40
5.9
VCA2619
0
500
Clipping Program
Circuitry
VDD
HGA/B
R1
Q1
Q5
Q7
Q9
R2
+IN
Q2
D1
D2
D3
D4
A1
Q3
A2
VCM
Q4
Q6
External
Capacitor
Q8
VCNTL
Q10
Q12
Q14
Q16
Q18
Q20
Q22
Q24
C1
VCA
Program
Circuitry
C
C2
Q11
Q13
Q15
Q17
Q19
Q21
Q23
Q25
Voltage−Controlled
Resistor Network
Q26
Q30
Control Signal
Q32
VCM
Q27
D5
D6
D7
D8
A4
A3
R3
Q28
−IN
R4
Q29
Q31
Q33
Q34
VDD
Clipping Program
Circuitry
VCLMP
Figure 36. Block Diagram of VCA
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The VCA accepts a differential input at the +IN and −IN
terminals. Amplifier A1, along with transistors Q2 and Q3,
forms a voltage follower that buffers the +IN signal to be
able to drive the voltage-controlled resistor. Amplifier A3,
along with transistors Q27 and Q28, plays the same role
as A1. The differential signal applied to the
voltage-controlled resistor network is converted to a
current that flows through transistors Q1 through Q4.
Through the mirror action of transistors Q1/Q5 and Q4/Q6,
a copy of this same current flows through Q5 and Q6.
Assuming that the signal current is less than the
programmed clipping current (that is, the current flowing
through transistors Q7 and Q8), the signal current will then
go through the diode bridge (D1 through D4) and be sent
through either R2 or R1, depending upon the state of Q9.
This signal current multiplied by the feedback resistor
associated with amplifier A2, determines the signal
voltage that is designated −OUT. Operation of the circuitry
associated with A3 and A4 is identical to the operation of
the previously described function to create the signal
+OUT.
A1 and its circuitry form a voltage-to-current converter,
while A2 and its circuitry form a current-to-voltage
converter. This architecture was adapted because it has
excellent signal-handling capability. A1 has been
designed to handle a large voltage signal without
overloading, and the various mirroring devices have also
been sized to handle large currents. Good overload
capability is achieved as both the input and output
amplifier are not required to amplify voltage signals.
Voltage amplification occurs when the input voltage is
converted to a current; this current in turn is converted
back to a voltage as amplifier A2 acts as a transimpedance
amplifier. The overall gain of the output amplifier A2 can be
altered by 6dB by the action of the HG signal. This enables
more optimum performance when the VCA interfaces with
either a 10-bit or 12-bit analog-to-digital converter (ADC).
An external capacitor (C) is required to provide a low
impedance connection to join the two sections of the
resistor network. Capacitor C could be replaced by a
short-circuit. By providing a DC connection, the output
offset will be a function of the gain setting. Typically, the
offset at this point is ±10mV; thus, if the gain varies from
1 to 100, the output offset would vary from ±10mV to
±100mV.
VARIABLE GAIN CHARACTERISTICS
Transistors Q10, Q12, Q14, Q16, Q18, Q20, Q22, and Q24
form a variable resistor network that is programmed in an
exponential manner to control the gain. Transistors Q11,
Q13, Q15, Q17, Q19, Q21, Q23, and Q25 perform the
same function. These two groups of FET variable resistors
are configured in this manner to balance the capacitive
loading on the total variable-resistor network. This
balanced configuration is used to keep the second
harmonic component of the distortion low. The common
source connection associated with each group of FET
variable resistors is brought out to an external pin so that
an external capacitor can be used to make an AC
connection. This connection is necessary to achieve an
adequate low-frequency bandwidth because the coupling
capacitor would be too large to include within the
monolithic chip. The value of this variable resistor ranges
in value from 15Ω to 5000Ω to achieve a gain range of
about 48dB. The low-frequency bandwidth is then given by
the formula:
Low Frequency BW + 1ń2pRC
(5)
where:
R is the value of the attenuator.
C is the value of the external coupling capacitor.
For example, if a low-frequency bandwidth of 500kHz was
desired and the value of R was 10Ω, then the value of the
coupling capacitor would be 0.05µF.
One of the benefits of this method of gain control is that the
output offset is independent of the variable gain of the
output amplifier. The DC gain of the output amplifier is
extremely low; any change in the input voltage is blocked
by the coupling capacitor, and no signal current flows
through the variable resistor. This method also means that
any offset voltage existing in the input is stored across this
coupling capacitor; when the resistor value is changed, the
DC output will not change. Therefore, changes in the
control voltage do not appear in the output signal.
Figure 37 shows the output waveform resulting from a step
change in the control voltage, and Figure 38 shows the
output voltage resulting when the control voltage is a
full-scale ramp.
Channel 1
VCNTL
(2V/div)
Channel 2
Output
(20mV/div)
Time (400ns/div)
Figure 37. Response to Step Change of VCNTL
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When FETs used as variable resistors are placed in
parallel, the attenuation characteristic that is created
behaves according to this same exponential characteristic
at discrete points as a function of the control voltage.
It does not perfectly obey an ideal exponential
characteristic at other points; however, an 8-section
approximation yields a ±1dB error to an ideal curve.
Channel 1
VCNTL
(2V/div)
PROGRAMMABLE CLIPPING
Channel 2
Output
(20mV/div)
Time (400ns/div)
Figure 38. Response to Ramp Change of VCNTL
The exponential gain control characteristic is achieved
through a piecewise approximation to a perfectly smooth
exponential curve. Eight FETs, operated as variable
resistors whose value is progressively 1/2 of the value of
the adjacent parallel FET, are turned on progressively, or
their value is lowered to create the exponential gain
characteristic. This characteristic can be shown in the
following way. An exponential such as y = ex increases in
the y dimension by a constant ratio as the x dimension
increases by a constant linear amount. In other words, for
a constant (x1 − x2), the ratio ex1/ex2 remains the same.
The clipping level of the VCA2617 can be programmed to
a desired output. The programming feature is useful when
matching the clipped level from the output of the VCA to
the full-scale range of a subsequent VCA, in order to
prevent the VCA from generating false spectral signals;
see the circuit diagram shown in Figure 39. The signal
node at the drain junction of Q5 and Q6 is sent to the diode
bridge formed by diode-connected transistors, D1 through
D4. The diode bridge output is determined by the current
that flows through transistors Q7 and Q8. The maximum
current that can then flow into the summing node of A2 is
this same current; consequently, the maximum voltage
output of A2 is this same current multiplied by the feedback
resistor associated with A2. The maximum output voltage
of A2, which would be the clipped output, can then be
controlled by adjusting the current that flows through Q7
and Q8; see the circuit diagram shown in Figure 36. The
circuitry of A1, R1, and Q1 converts the clamp voltage
(VCLMP) to a current that controls equal and opposite
currents flowing through transistors Q5 and Q6.
VDD
R1
Q9
Q1
A1
Q7
Q5
From
Buffered
Input
Q2
Clip Adjust
Input
R2
D1
D2
D3
D4
VCM
HGA/B
A2
Output
Amplifier
Q6
Q8
Figure 39. Clipping Level Adjust Circuitry
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When HG = 0, the previously described circuitry is
designed so that the value of the VCLMP signal is equal to
the peak differential signal developed between +VOUT and
−VOUT. When HG = 1, the differential output will be equal
to the clamp voltage. This method of controlled clipping
also achieves fast and clean settling waveforms at the
output of the VCA, as shown in Figure 40 through
Figure 43. The sequence of waveforms demonstrate the
clipping performance during various stages of overload.
In a typical application, the VCA2617 will drive an
anti-aliasing filter, which in turn will drive an ADC. Many
modern ADCs, such as the ADS5270, are well-behaved
with as much as 2x overload. This means that the clipping
level of the VCA should be set to overcome the loss in the
filter such that the clipped input to the ADC is just slightly
over the full-scale input. By setting the clipping level in this
manner, the lowest harmonic distortion level will be
achieved without interfering with the overload capability of
the ADC.
Input
(0.5V/div)
Input
(0.5V/div)
Differential
Output
(0.5V/div)
Differential
Output
(0.5V/div)
VCNTL = 1.0V
Time (200ns/div)
Figure 40. Before Overload (630mVPP Input)
VCNTL = 1.0V
Figure 42. Overload (1.5VPP Input)
Input
(0.5V/div)
Input
(2V/div)
Differential
Output
(0.5V/div)
Differential
Output
(1V/div)
VCNTL = 1.0V
Time (200ns/div)
Figure 41. Approaching Overload
(700mVPP Input)
Time (200ns/div)
VCNTL = 1.0V
Time (200ns/div)
Figure 43. Extreme Overload (3.8VPP Input)
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
VCA2617RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
VCA
2617
VCA2617RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
VCA
2617
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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