VCA5807
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SLOS727 – DECEMBER 2012
Fully Integrated, 8-Channel Voltage Controlled Amplifier for Ultrasound with Passive CW
Mixer, 0.75 nV/rtHz, 99 mW/CH
Check for Samples: VCA5807
FEATURES
DESCRIPTION
•
The VCA5807 is an integrated Voltage Controlled
Amplifier (VCA) specifically designed for ultrasound
systems in which high performance and small size
are required. The VCA5807 integrates a complete
time-gain-control (TGC) imaging path and a
continuous wave Doppler (CWD) path. It also enables
users to select one of various power/noise
combinations to optimize system performance.
Therefore, the VCA5807 is a suitable ultrasound
analog front end solution not only for high-end
systems, but also for portable systems.
1
•
•
•
•
•
•
•
•
•
•
•
8-Channel Voltage Controlled Amplifier
– LNA, VCAT, PGA, LPF, and CW Mixer
Programmable Low-Noise Amplifier (LNA)
– 24/18/12 dB Gain
– 0.25/0.5/1 VPP Linear Input Range
– 0.63/0.7/0.9 nV/rtHz Input Referred Noise
– Programmable Active Termination
40 dB Low Noise Voltage Controlled
Attenuator (VCAT)
24/30 dB Programmable Gain Amplifier (PGA)
3rd Order Linear Phase Low-Pass Filter (LPF)
– 10, 15, 20, 30 MHz
– Butterworth Characteristics
Noise/Power Optimizations (Full Chain)
– 99 mW/CH at 0.75 nV/rtHz
– 56 mW/CH at 1.1 nV/rtHz
– 80 mW/CH at CW Mode
Excellent Device-to-Device Gain Matching
– ±0.5 dB (typical) and ±1.05 dB (max)
Low Harmonic Distortion
Fast and Consistent Overload Recovery
Low Frequency Sonar Signal Processing
Passive Mixer for Continuous Wave Doppler
(CWD)
– Low Close-in Phase Noise –156 dBc/Hz at 1
KHz off 2.5 MHz Carrier
– Phase Resolution of 1/16λ
– Support 32X,16X, 8X, 4X and 1X CW Clocks
– 12dB Suppression on 3rd and 5th Harmonics
– Flexible Input Clocks
14mm x 14mm, 100-pin TQFP
APPLICATIONS
•
•
•
The VCA5807 contains eight channels of voltage
controlled amplifier (VCA), and CW mixer. The VCA
includes Low noise Amplifier(LNA), Voltage controlled
Attenuator (VCAT), Programmable Gain Amplifier
(PGA), and Low-Pass Filter (LPF). The LNA gain is
programmable to support 250 mVPP to 1 VPP input
signals. Programmable active termination is also
supported by the LNA. The ultra-low noise VCAT
provides an attenuation control range of 40dB and
improves overall low gain SNR which benefits
harmonic imaging and near field imaging. The PGA
provides gain options of 24 dB and 30 dB. Before the
ADC, a LPF can be configured as 10 MHz, 15 MHz,
20 MHz, or 30 MHz to support ultrasound
applications with different frequencies. In addition, the
signal chain of the VCA5807 can handle signal
frequency lower than 100 KHz, which enables it to be
used not only in ultrasound applications but also in
sonar applications.
The VCA5807 integrates a low power passive mixer
and a low noise summing amplifier to accomplish onchip CWD beamformer. 16 selectable phase-delays
can be applied to each analog input signal.
Meanwhile a unique 3rd and 5th order harmonic
suppression filter is implemented to enhance CW
sensitivity.
The VCA5807 is available in a 14mm x 14mm, 100pin TQFP package and it is specified for operation
from -40°C to 85°C.
Medical Ultrasound Imaging
Nondestructive Evaluation Equipments
Sonar Imaging
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
VCA5807
SLOS727 – DECEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SPI
VCA5807
1 of 8 Channels
SPI Logic
LNA OUT
LNA
LNA IN
16X CLK
1X CLK
(Syc)
16 Phases
Generator
VCAT
PGA
0 to -40 dB
24, 30dB
CW Mixer
16X1 Multiplexer
3rd LP Filter
10, 15, 20, 30
MHz
Differential
Outputs
Summing
Amplifier/ Filter
Reference
CW I/Q
Vout
Differential
TGC Vcntl
1X CLK
Figure 1. Block Diagram
PACKAGING/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE TYPE
OPERATING
ORDERING NUMBER
PACKAGE QUANTITY
VCA5807
TQFP
-40°C to 85°C
VCA5807PZP
90
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
Supply voltage range
UNIT
MIN
MAX
AVDD
–0.3
3.9
V
AVDD_5V
–0.3
6
V
–0.3
Voltage at analog inputs and digital inputs
min [3.6,AVDD+0.3]
V
Peak solder temperature (2)
260
°C
Maximum junction temperature (TJ), any condition
105
°C
Storage temperature range
–55
150
°C
Operating temperature range
-40
85
°C
HBM
2000
V
CDM
500
V
ESD Ratings
(1)
(2)
2
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
Device complies with JSTD-020D.
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SLOS727 – DECEMBER 2012
THERMAL INFORMATION
VCA5807
THERMAL METRIC (1)
TQFP
UNITS
100 PINS
θJA
Junction-to-ambient thermal resistance
25.0
θJCtop
Junction-to-case (top) thermal resistance
6.1
θJB
Junction-to-board thermal resistance
7.7
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
7.6
θJCbot
Junction-to-case (bottom) thermal resistance
0.2
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
MAX
AVDD
3.15
3.6
AVDD_5V
4.75
5.5
V
-40
85
°C
Ambient Temperature, TA
UNIT
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VCA5807
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PINOUT INFORMATION
TQFP PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN
DESCRIPTION
NO.
NAME
2, 5, 8, 11, 14,
17, 20, 23
ACT1...ACT8
Active termination input pins for CH1~8.1 μF capacitors are recommended.
27, 28, 29, 43,
78, 88, 96, 97,
98, 100
AVDD
3.3V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks.
50
AVDD_5V
5V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks.
26, 31, 32, 37,
42, 44, 58, 63,
68, 79, 82. 89,
92, 95, 99
AVSS
Analog ground.
93
CLKM_16X
Negative input of differential CW 16X clock. Tie to GND when the CMOS clock mode is enabled. In the
4X, 8X, and 32X CW clock modes, this pin becomes the 4X, 8X, or 32X CLKM input. In the 1X CW
clock mode, this pin becomes the quadrature-phase 1X CLKM for the CW mixer. Can be floated if CW
mode is not used. Please see CW Clock Selection.
94
CLKP_16X
Positive input of differential CW 16X clock. In 4X, 8X, and 32X clock modes, this pin becomes the 4X,
8X, or 32X CLKP input. In the 1X CW clock mode, this pin becomes the quadrature-phase 1X CLKP
for the CW mixer. Can be floated if CW mode is not used. Please see CW Clock Selection.
4
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SLOS727 – DECEMBER 2012
PIN FUNCTIONS (continued)
PIN
DESCRIPTION
NO.
NAME
90
CLKM_1X
Negative input of differential CW 1X clock. Tie to GND when the CMOS clock mode is enabled (Refer
to Figure 94 for details). In the 1X clock mode, this pin is the In-phase 1X CLKM for the CW mixer.
Can be floated if CW mode is not used. Please see CW Clock Selection.
91
CLKP_1X
Positive input of differential CW 1X clock. In the 1X clock mode, this pin is the In-phase 1X CLKP for
the CW mixer. Can be floated if CW mode is not used. Please see CW Clock Selection.
30
CM_BYP
Bias voltage and bypass to ground. ≥ 1µF is recommended. To suppress ultra low frequency noise,
10µF can be used.
34
CW_IP_AMPINM
Negative differential input of the In-phase summing amplifier. External LPF capacitor has to be
connected between CW_IP_AMPINM and CW_IP_OUTP. This pin becomes the CH7 PGA negative
output when PGA test mode is enabled. Can be floated if not used.
35
CW_IP_AMPINP
Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be
connected between CW_IP_AMPINP and CW_IP_OUTM. This pin becomes the CH7 PGA positive
output when PGA test mode is enabled. Can be floated if not used.
36
CW_IP_OUTM
Negative differential output for the In-phase summing amplifier. External LPF capacitor has to be
connected between CW_IP_AMPINP and CW_IP_OUTPM. Can be floated if not used.
33
CW_IP_OUTP
Positive differential output for the In-phase summing amplifier. External LPF capacitor has to be
connected between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used.
39
CW_QP_AMPIN
M
Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to
be connected between CW_QP_AMPINM and CW_QP_OUTP. This pin becomes CH8 PGA negative
output when PGA test mode is enabled. Can be floated if not used.
40
Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be
CW_QP_AMPINP connected between CW_QP_AMPINP and CW_QP_OUTM. This pin becomes CH8 PGA positive
output when PGA test mode is enabled. Can be floated if not used.
41
CW_QP_OUTM
Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor has to
be connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used.
38
CW_QP_OUTP
Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor has to
be connected between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used.
25, 48, 49, 51,
52, 53, 73, 74,
75, 76, 77
NC
Do not connect. Must leave floated
3, 6, 9, 12, 15,
18, 21, 24
INM1…INM8
CH1~8 complimentary analog inputs. Bypass to ground with ≥ 0.015µF capacitors. The HPF response
of the LNA depends on the capacitors. Please see LOW-NOISE AMPLIFIER (LNA).
1, 4, 7, 10, 13,
16, 19, 22
INP1...INP8
CH1~8 analog inputs. AC couple to inputs with ≥ 0.1µF capacitors.
81
PDN_FAST
VCA partial (fast) power down control pin with an internal pull down resistor of 20kΩ. Active High.
80
PDN_GLOBAL
Global (complete) power-down control pin for the entire chip with an internal pull down resistor of
20kΩ. Active High.
54, 56, 59, 61,
64, 66, 69, 71
PGA_OUTMx
Negative PGA output
55, 57, 60, 62,
65, 67, 70, 72
PGA_OUTPx
Positive PGA output
87
RESET
Hardware reset pin with an internal pull-down resistor of 20kΩ. Active high.
86
SCLK
Serial interface clock input with an internal pull-down resistor of 20kΩ
85
SDATA
Serial interface data input with an internal pull-down resistor of 20kΩ
83
SDOUT
Serial interface data readout. High impedance when readout is disabled.
84
SEN
Serial interface enable with an internal pull up resistor of 20kΩ. Active low.
46
VCNTLM
Negative differential attenuation control pin.
47
VCNTLP
Positive differential attenuation control pin
45
VHIGH
Bias voltage; bypass to ground with ≥1µF. To suppress ultra low frequency noise, 10µF can be used.
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VCA5807
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ELECTRICAL CHARACTERISTICS
AVDD_5V = 5V, AVDD = 3.3V, AC-coupled with 0.1µF at INP and bypassed to ground with 15nF at INM, No active
termination, VCNTL= 0V, fIN= 5MHz, LNA = 18dB, PGA = 24dB, LPF Filter = 15MHz, low noise mode, VOUT= –1dBFS (1.8VPP),
single-ended VCNTL mode, VCNTLM = GND, 2 kΩ load (ADC Rin), internal 500Ω CW feedback resistor, CMOS CW clocks,
at ambient temperature TA = 25°C, unless otherwise noted. Min and max values are specified across full-temperature range
with AVDD_5V=5V, AVDD=3.3V
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
TGC FULL SIGNAL CHANNEL (LNA+VCAT+LPF)
en (RTI)
en (RTI)
NF
Input voltage noise over LNA Gain(low
noise mode)
RS = 0Ω, f = 2MHz, LNA =24/18/12dB, PGA = 24dB
0.76/0.83/1.16
RS = 0Ω, f = 2MHz, LNA = 24/18/12dB, PGA = 30dB
0.75/0.86/1.12
Input voltage noise over LNA Gain(low
power mode)
RS = 0Ω, f = 2MHz, LNA = 24/18/12dB, PGA = 24dB
1.1/1.2/1.45
RS = 0Ω, f = 2MHz, LNA = 24/18/12dB, PGA = 30dB
1.1/1.2/1.45
Input Voltage Noise over LNA
Gain(Medium Power Mode)
RS = 0Ω, f = 2MHz, LNA = 24/18/12dB, PGA = 24dB
1/1.05/1.25
RS = 0Ω, f = 2MHz, LNA = 24/18/12dB, PGA = 30dB
0.95/1.0/1.2
Input voltage noise at low frequency
f = 100 KHz, INM Cap = 1uF, PGA integrator disabled (0x33[4]=1)
Input referred current noise
Low Noise Mode/Medium Power Mode/Low Power Mode
Noise figure
NF
nV/rtHz
nV/rtHz
nV/rtHz
0.9
nV/rtHz
2.7/2.1/2
pA/rtHz
RS = 200Ω, 200Ω active termination, PGA = 24dB, LNA = 12/18/24dB
3.85/2.4/1.8
dB
RS = 100Ω, 100Ω active termination, PGA = 24dB, LNA = 12/18/24dB
5.3/3.1/2.3
dB
Rs = 500 Ω/1KΩ, no terminaiton, Low NF mode is enabled (Reg53[9]=1)
0.94/1.08
dB
Rs=50Ω/200Ω, no terminaiton, Low noise mode (Reg53[9]=0)
2.35/1.05
dB
Noise figure
VINMAX
Maximum Linear Input Voltage
LNA gain = 24/18/12dB
250/500/1000
VCLAMP
Clamp Voltage
Reg52[10:9] = 0, LNA = 24/18/12dB
350/600/1150
Low noise mode
mVPP
24/30
PGA Gain
dB
Medium/Low power mode
Total gain
VOUTMAX
24/28.5
LNA = 24dB, PGA = 30dB, Low noise mode
54
LNA = 24dB, PGA = 30dB, Med power mode
52.5
LNA = 24dB, PGA = 30dB, Low power mode
52.5
Maximum Linear Output Voltage
Defined as 0 dBFS
2
Ch-CH Noise Correlation Factor without
Signal (1)
Summing of 8 channels
0
Full band (VCNTL = 0/0.8)
0.15/0.17
1MHz band over carrier (VCNTL= 0/0.8)
0.18/0.75
Ch-CH Noise Correlation Factor with
Signal (1)
dB
VPP
VCNTL= 0.6V (22 dB total channel gain)
40
67
VCNTL= 0, LNA = 18dB, PGA = 24dB
104
153
nV/rtHz
VCNTL= 0, LNA = 24dB, PGA = 24dB
190
Narrow Band Integrated Output Noise
Noise over 2MHz band around carrier at VCNTL = 0.6V ( 22dB total gain)
100
125
µVRMS
Input Common-mode Voltage
At INP and INM pins
2.4
V
8
kΩ
Output Referred Noise
Input resistance
Preset active termination enabled
Input capacitance
Input Control Voltage
VCNTLP - VCNTLM
Common-mode voltage
VCNTLP and VCNTLM
Gain Range
pF
0
1.5
V
0.75
V
-40
dB
VCNTL= 0.1V to 1.1V
35
dB/V
Input Resistance
Between VCNTLP and VCNTLM
200
KΩ
Input Capacitance
Between VCNTLP and VCNTLM
1
pF
TGC Response Time
VCNTL= 0V to 1.5V step function
1.5
µs
10, 15, 20, 30
MHz
Settling time for change in LNA gain
14
µs
Settling time for change in active
termination setting
1
µs
Noise correlation factor is defined as Nc/(Nu+Nc), where Nc is the correlated noise power in single channel; and Nu is the uncorrelated
noise power in single channel. Its measurement follows the below equation, in which the SNR of single channel signal and the SNR of
summed eight channel signal are measured.
NC
=
10
8CH_SNR
10
10
Nu + NC
6
Ω
20
Gain Slope
3rd order-Low-pass Filter
(1)
50/100/200/400
1CH_SNR
1
x
1
-
56
7
10
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ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5V, AVDD = 3.3V, AC-coupled with 0.1µF at INP and bypassed to ground with 15nF at INM, No active
termination, VCNTL= 0V, fIN= 5MHz, LNA = 18dB, PGA = 24dB, LPF Filter = 15MHz, low noise mode, VOUT= –1dBFS (1.8VPP),
single-ended VCNTL mode, VCNTLM = GND, 2 kΩ load (ADC Rin), internal 500Ω CW feedback resistor, CMOS CW clocks,
at ambient temperature TA = 25°C, unless otherwise noted. Min and max values are specified across full-temperature range
with AVDD_5V=5V, AVDD=3.3V
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
AC ACCURACY
LPF Bandwidth tolerance
CH-CH group delay variation
2MHz to 15MHz
CH-CH Phase variation
15MHz signal
0V < VCNTL< 0.1V (Dev-to-Dev)
Gain matching
±5
%
2
ns
11
Degree
±0.5
0.1V< VCNTL < 1.1V(Dev-to-Dev)
–1.05
±0.5
1.05
0.1V< VCNTL < 1.1V(Dev-to-Dev) Temp = -40°C and 85°C
-1.25
±0.5
1.25
dB
1.1V< VCNTL< 1.5V(Dev-to-Dev)
±0.5
Gain matching
Channel-to-Channel
±0.25
Output offset
VCNTL= 0, PGA = 30dB, LNA = 24dB
-6
dB
6
mV
AC PERFORMANCE
HD2
HD3
THD
Second-Harmonic Distortion
Third-Harmonic Distortion
Total Harmonic Distortion
FIN = 2MHz; VOUT = -1dBFS
–60
FIN = 5MHz; VOUT = -1dBFS
–60
FIN = 5MHz; VIN= 500mVPP,
VOUT = –1dBFS, LNA = 18dB
–55
FIN = 5MHz; Vin = 250mVPP,
VOUT =–1dBFS, LNA = 24dB
–55
FIN = 2MHz; VOUT = –1dBFS
–53
FIN = 5MHz; VOUT = –1dBFS
–55
FIN = 5MHz; VIN = 500mVPP ,
VOUT = –1dBFS, LNA = 18dB
–55
FIN = 5MHz; VIN = 250mVPP ,
VOUT = –1dBFS, LNA = 24dB
–55
FIN = 2MHz; VOUT= –1dBFS
–52.5
FIN = 5MHz; VOUT= –1dBFS
–55
dBc
dBc
dBc
IMD3
Intermodulation distortion
f1 = 5MHz at –1dBFS,
f2 = 5.01MHz at –27dBFS
–60
XTALK
Cross-talk
FIN = 5MHz; VOUT= –1dBFS
–65
dBc
Phase Noise
1kHz off 5MHz (VCNTL=0V)
–132
dBc/Hz
Input Referred Voltage Noise
RS = 0Ω, f = 2MHz, RIN = High Z, Gain = 24/18/12dB
High-Pass Filter
-3dB Cut-off Frequency
dBc
LNA
LNA linear output
0.63/0.70/0.9
nV/rtHz
50/100/150/200
KHz
4
Vpp
2/10.5
nV/rtHz
1.75
nV/rtHz
80
KHz
VCAT+ PGA
VCAT Input Noise
0dB/-40dB Attenuation
PGA Input Noise
24dB/30dB
-3dB HPF cut-off Frequency
High-Pass Filter is enabled
Output Common Mode Voltage
VOUTMAX
Maximum Linear Output Voltage
Defined as 0 dBFS
Minimum Load Impedance
0.9
V
2
VPP
1
KΩ
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ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5V, AVDD = 3.3V, AC-coupled with 0.1µF at INP and bypassed to ground with 15nF at INM, No active
termination, VCNTL= 0V, fIN= 5MHz, LNA = 18dB, PGA = 24dB, LPF Filter = 15MHz, low noise mode, VOUT= –1dBFS (1.8VPP),
single-ended VCNTL mode, VCNTLM = GND, 2 kΩ load (ADC Rin), internal 500Ω CW feedback resistor, CMOS CW clocks,
at ambient temperature TA = 25°C, unless otherwise noted. Min and max values are specified across full-temperature range
with AVDD_5V=5V, AVDD=3.3V
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
CW DOPPLER
en (RTI)
en (RTO)
en (RTI)
en (RTO)
1 channel mixer, LNA = 24dB, 500Ω feedback resistor
0.8
8 channel mixer, LNA = 24dB, 62.5Ω feedback resistor
0.33
1 channel mixer, LNA = 24dB, 500Ω feedback resistor
12
8 channel mixer, LNA = 24dB, 62.5Ω feedback resistor
5
1 channel mixer, LNA = 18dB, 500Ω feedback resistor
1.1
8 channel mixer, LNA = 18dB, 62.5Ω feedback resistor
0.5
1 channel mixer, LNA = 18dB, 500Ω feedback resistor
8.1
8 channel mixer, LNA = 18dB, 62.5Ω feedback resistor
4.0
Input voltage noise (CW)
nV/rtHz
Output voltage noise (CW)
nV/rtHz
Input voltage noise (CW)
nV/rtHz
Output voltage noise (CW)
nV/rtHz
NF
Noise figure
RS = 100Ω, RIN = High Z, FIN = 2MHz (LNA, I/Q mixer and summing
amplifier/filter)
1.8
dB
fCW
CW Operation Range (2)
CW signal carrier frequency, 16X mode / 32X mode
8/4
MHz
1X CLK (16X mode)
8
16X CLK(16X mode)
128
4X CLK(4X mode)
32
32X CLK(32X mode)
128
CW Clock frequency
MHz
AC coupled LVDS clock amplitude
0.7
CLKM_16X-CLKP_16X; CLKM_1X-CLKP_1X
AC coupled LVPECL clock amplitude
VCMOS
CLK duty cycle
1X and 16X CLKs
Common-mode voltage
Internal provided
35
CMOS Input clock amplitude
4
CW Mixer phase noise
1kHz off 2MHz carrier
Input dynamic range
FIN = 2MHz, LNA=24/18/12dB
IMD3
Intermodulation distortion
%
V
5
4
DR
8
65
2.5
CW Mixer conversion loss
(2)
VPP
1.6
V
dB
-156
dBc/Hz
160/164/165
dBFS/Hz
f1 = 5 MHz, f2 = 5.01 MHz, both tones at -8.5dBm amplitude, 8 channels
summed up in-phase, CW feedback resistor = 87 Ω
–50
dBc
f1 = 5 MHz, F2= 5.01 MHz, both tones at –8.5dBm amplitude, Single
channel case, CW feed back resistor = 500Ω
–60
dBc
I/Q Channel gain matching
16X mode
±0.04
dB
I/Q Channel phase matching
16X mode
±0.1
Degree
I/Q Channel gain matching
4X mode
±0.04
dB
I/Q Channel phase matching
4X mode
±0.1
Degree
Image rejection ratio
fin = 2.01MHz, 300mV input amplitude, CW clock frequency = 2.00MHz
–50
dBc
The maximum clock frequency for the 16X and 32X CLK is 128MHz. Hence, the CW operation range is limited to 8MHz in the 16X CW
mode. In the 8X, 4X, and 1X modes, higher CW signal frequencies up to 15 MHz can be supported with small degradation in
performance, please see CW Clock Selection.
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ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5V, AVDD = 3.3V, AC-coupled with 0.1µF at INP and bypassed to ground with 15nF at INM, No active
termination, VCNTL= 0V, fIN= 5MHz, LNA = 18dB, PGA = 24dB, LPF Filter = 15MHz, low noise mode, VOUT= –1dBFS (1.8VPP),
single-ended VCNTL mode, VCNTLM = GND, 2 kΩ load (ADC Rin), internal 500Ω CW feedback resistor, CMOS CW clocks,
at ambient temperature TA = 25°C, unless otherwise noted. Min and max values are specified across full-temperature range
with AVDD_5V=5V, AVDD=3.3V
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
CW SUMMING AMPLIFIER
VCMO
Common-mode voltage
Summing amplifier inputs/outputs
Summing amplifier output
100Hz
Input referred voltage noise (3)
Input referred current noise (3)
V
4
VPP
2
nV/rtHz
1.2
nV/rtHz
2KHz-100MHz
1
nV/rtHz
100Hz
7
pA/rtHz
1kHz
3
pA/rtHz
2.5
pA/rtHz
1kHz
10KHz-100MHz
Unit gain bandwidth
Max output current
1.5
Linear operation range
200
MHz
20
mAPP
POWER DISSIPATION
AVDD Voltage
3.15
3.3
3.6
V
AVDD_5V Voltage
4.75
5
5.5
V
TGC low noise mode, no signal
203
235
TGC medium power mode, no signal
126
TGC low power mode, no signal
99
CW-mode, no signal
147
TGC low noise mode, 500mVPP Input,1% duty cycle
210
TGC medium power mode, 500mVPP Input, 1% duty cycle
133
TGC low power, 500mVPP Input, 1% duty cycle
105
172
AVDD (3.3V) Current
mA
CW-mode, 500mVPP Input
375
TGC mode no signal
25.5
CW Mode no signal, 16X clock = 32MHz
32
TGC mode, 500mVPP Input,1% duty cycle
16.5
CW-mode, 500mVPP Input
42.5
35
AVDD_5V Current
mA
TGC low noise mode, no signal
99
TGC medium power mode, no signal
68
TGC low power mode, no signal
55.5
TGC low noise mode, 500mVPP input,1% duty cycle
102.5
121
VCA Power dissipation
mW/CH
TGC medium power mode, 500mVPP Input, 1% duty cycle
TGC low power mode, 500mVPP input,1% duty cycle
CW Power dissipation
71
59.5
No signal, CW Mode no signal, 16X clock = 32MHz
80
500mVPP input, 16X clock = 32MHz
173
PDN_FAST = High
12.5
Complete power-down PDN_Global=High
0.6
mW/CH
Power dissipation in power down mode
Power-down response time
Time taken to enter power down
VCA power down
Power-up response time
1
µs
2µs+1% of PDN
time
µs
Complete power down
2.5
ms
fin = 5MHz, at 50mVpp noise at 1KHz on supply (4)
–65
dBc
fin = 5MHz, at 50mVPP noise at 50KHz on supply (4)
–65
dBc
f = 10kHz, VCNTL = 0V (high gain), AVDD
–40
dBc
f = 10kHz, VCNTL = 0V (high gain), AVDD_5V
–55
dBc
f = 10kHz, VCNTL = 1V (low gain), AVDD
–50
dBc
Power supply modulation ratio (CW Mode
with 8 mixers active)
fin = 5MHz, 1-20 KHz 100mVpp noise on the AVDD
-57
dBc
fin = 5MHz, 1-20 KHz 100mVpp noise on the AVDD_5V
-59
dBc
Power supply rejection ratio (CW Mode
with 8 mixers active)
fin = 5MHz, 5.001-5.02 MHz 100mVpp noise on the AVDD
-75
dBc
fin = 5MHz, 5.001-5.02 MHz 100mVpp noise on the AVDD_5V
-40
dBc
Power supply modulation ratio, AVDD and
AVDD_5V (TGC Mode)
Power supply rejection ratio (TGC Mode)
(3)
(4)
mW/CH
2
By simulation.
PSMR specification is with respect to RF signal amplitude.
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DIGITAL CHARACTERISTICS
(Note: This timing data was collected under 14 bit operation)
Typical values are at 25°C, AVDD = 3.3V, AVDD_5 = 5V unless otherwise noted. Minimum and maximum values are across
the full temperature range: TMIN = -40°C to TMAX = 85°C.
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
DIGITAL INPUTS/OUTPUTS
VIH
Logic high input voltage
2
VIL
Logic low input voltage
0
3.3
0.3
V
V
Logic high input current
200
µA
Logic low input current
200
µA
5
pF
VOH
Input capacitance
Logic high output voltage
SDOUT pin
AVDD
V
VOL
Logic low output voltage
SDOUT pin
0
V
10
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TYPICAL CHARACTERISTICS
AVDD_5V = 5V, AVDD = 3.3V, ac-coupled with 0.1µF caps at INP and 15nF caps at INM, No active termination,
VCNTL = 0V, FIN = 5MHz, LNA = 18dB, PGA = 24dB, LPF Filter = 15MHz, low noise mode, single-ended VCNTL
mode, VCNTLM = GND, VOUT = -1dBFS (1.8VPP), 2 kΩ load (ADC Rin), 500Ω CW feedback resistor, CMOS 16X
clock, at ambient temperature TA = 25C, unless otherwise noted.
Figure 3. Gain vs. Temperature, LNA = 18dB and
PGA = 24dB
180
180
160
160
140
140
Number of Occurances
Number of Occurances
Figure 2. Gain vs. VCNTL, LNA = 18dB and PGA = 24dB
120
100
80
60
40
120
100
80
60
40
20
20
0
0
Gain Error (dB)
C001
Figure 4. Gain Matching Histogram,
VCNTL = 0.3V (1336channels)
Gain Error (dB)
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Figure 5. Gain Matching Histogram,
VCNTL = 0.6V (1336 channels)
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TYPICAL CHARACTERISTICS (continued)
Impedance Magnitude Response
180
Open
12000
140
10000
120
Impedance (Ohms)
Number of Occurances
160
100
80
60
40
8000
6000
4000
20
2000
0
500k
Gain Error (dB)
4.5M
8.5M
12.5M
16.5M
20.5M
C003
Frequency (Hz)
Figure 6. Gain Matching Histogram,
VCNTL = 0.9V (1336 channels)
Figure 7. Input Impedance without Active Termination
(Magnitude)
Impedance Phase Response
Impedance Magnitude Response
10
500
Open
0
400
Impedance (Ohms)
Phase (Degrees)
−10
−20
−30
−40
−50
−60
350
300
250
200
150
−70
100
−80
50
−90
500k
50 Ohms
100 Ohms
200 Ohms
400 Ohms
450
4.5M
8.5M
12.5M
16.5M
0
500k
20.5M
4.5M
8.5M
Frequency (Hz)
12.5M
16.5M
Figure 8. Input Impedance without Active Termination
(Phase)
Figure 9. Input Impedance with Active Termination
(Magnitude)
Impedance Phase Response
5
10MHz
15MHz
20MHz
30MHz
0
0
−10
−5
Amplitude (dB)
Phase (Degrees)
10
−20
−30
−40
−50
−60
−70
−80
−90
500k
20.5M
Frequency (Hz)
−10
−15
−20
50 Ohms
100 Ohms
200 Ohms
400 Ohms
4.5M
−25
−30
8.5M
12.5M
16.5M
0
20.5M
10
20
30
40
50
60
Frequency (MHz)
Frequency (Hz)
Figure 10. Input Impedance with Active Termination (Phase)
12
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Figure 11. Low-Pass Filter Response
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TYPICAL CHARACTERISTICS (continued)
HPF CHARECTERISTICS (LNA+VCA+PGA)
LNA INPUT HPF CHARECTERISTICS
3
5
0
0
−3
−5
Amplitude (dB)
Amplitude (dB)
−6
−9
−12
−15
−18
−21
01
00
11
10
−24
−27
−30
10
100
−10
−15
−20
−25
−30
−35
−40
500
10
100
Frequency (KHz)
Frequency (KHz)
Figure 12. LNA High-Pass Filter Response vs. Reg59[3:2]
−144
−146
−152
−154
−156
−158
−160
−162
−164
−150
−152
−154
−156
−158
−160
−162
−164
−166
−166
−168
−168
1000
10000
50000
PN 1 Ch
PN 8 Ch
−148
Phase Noise (dBc/Hz)
−150
Phase Noise
−144
16X Clock Mode
8X Clock Mode
4X Clock Mode
−148
Phase Noise (dBc/Hz)
Figure 13. Full Channel High-Pass Filter Response at
Default Register Setting
Single Channel CW PN
−146
−170
100
−170
100
1000
Offset frequency (Hz)
50000
Figure 15. CW Phase Noise, Fin = 2MHz,
1-CH vs. 8-CHs
Eight Channel CW PN
−146
16X Clock Mode
8X Clock Mode
4X Clock Mode
−148
−150
Phase Noise (dBc/Hz)
10000
Frequency Offset (Hz)
Figure 14. 1-CH CW Phase Noise, Fin = 2MHz
−144
500
−152
−154
−156
−158
−160
−162
−164
−166
−168
−170
100
1000
10000
50000
Offset frequency (Hz)
Figure 16. 8-CHs CW Phase Noise vs. Clock Modes, Fin =
2MHz
Figure 17. CW Thermal Noise 1-CH vs 8-CHs
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TYPICAL CHARACTERISTICS (continued)
14
Figure 18. IRN, PGA = 24dB and Low Noise Mode
Figure 19. IRN, PGA = 24dB and Low Noise Mode Zoomed
Figure 20. IRN, PGA = 24dB and Medium Power Mode
Figure 21. IRN, PGA = 24dB and Medium Power Mode
Zoomed
Figure 22. IRN, PGA = 24dB and Low Power Mode
Figure 23. IRN, PGA = 24dB and Low Power Mode Zoomed
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TYPICAL CHARACTERISTICS (continued)
Figure 24. ORN, PGA = 24dB and Low Noise Mode
Figure 25. ORN PGA=24dB and Med Power Mode
Figure 26. ORN, PGA = 24dB and Low Power Mode
Figure 27. IRN vs Frequency, PGA = 24dB and Low Noise
Mode
Figure 28. ORN vs Frequency, PGA = 24dB and Low Noise
Mode
Figure 29. IRN vs Frequency, PGA = 24dB and Low NF
Mode
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TYPICAL CHARACTERISTICS (continued)
16
Figure 30. ORN vs Frequency, PGA = 24dB and Low NF
Mode
Figure 31. TGC Noise Figure, LNA = 12dB and
Low Noise Mode
Figure 32. TGC Noise Figure, LNA = 18dB and
Low Noise Mode
Figure 33. TGC Noise Figure, LNA = 24dB and
Low Noise Mode
Figure 34. Noise Figure vs. Power Modes with 400Ω Active
Termination
Figure 35. Noise Figure vs. Power Modes without
Termination
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TYPICAL CHARACTERISTICS (continued)
Figure 36. HD2 vs. Frequency, Vin = 500mVpp and
Vout = -1dBFS
Figure 37. HD3 vs. Frequency, Vin = 500mVpp and
Vout = -1dBFS
Figure 38. HD2 vs. Gain, LNA = 12dB and PGA = 24dB and
Vout = -1dBFS
Figure 39. HD3 vs. Gain, LNA = 12dB and PGA = 24dB and
Vout = -1dBFS
Figure 40. HD2 vs. Gain, LNA = 18dB and PGA = 24dB and
Vout = -1dBFS
Figure 41. HD3 vs. Gain, LNA = 18dB and PGA = 24dB and
Vout = -1dBFS
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TYPICAL CHARACTERISTICS (continued)
Figure 42. HD2 vs. Gain, LNA = 24dB and PGA = 24dB and
Vout = -1dBFS
Figure 43. HD3 vs. Gain, LNA = 24dB and PGA = 24dB and
Vout = -1dBFS
Figure 44. IMD3, Fout1 = -7dBFS and Fout2 = -7 dBFS
Figure 45. IMD3, Fout1 = -21dBFS and Fout2 = -21dBFS
PSMR vs SUPPLY FREQUENCY
PSMR vs SUPPLY FREQUENCY
−60
−55
−65
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−60
PSMR (dBc)
PSMR (dBc)
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−65
−70
−70
−75
−75
5
10
100
1000 2000
−80
5
Supply frequency (kHz)
100
1000 2000
Supply frequency (kHz)
Figure 46. AVDD Power Supply Modulation Ratio, 100mVpp
Supply Noise with Different Frequencies (TGC Mode)
18
10
Figure 47. AVDD_5V Power Supply Modulation Ratio,
100mVpp Supply Noise with Different Frequencies (TGC
Mode)
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TYPICAL CHARACTERISTICS (continued)
3V PSRR vs SUPPLY FREQUENCY
5V PSRR vs SUPPLY FREQUENCY
−20
−20
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−40
−50
−60
−70
−40
−50
−60
−70
−80
−90
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−30
PSRR wrt supply tone (dB)
PSRR wrt supply tone (dB)
−30
−80
5
10
100
−90
1000 2000
5
10
100
Supply frequency (kHz)
Supply frequency (kHz)
Figure 48. AVDD Power Supply Rejection Ratio, 100mVpp
Supply Noise with Different Frequencies (TGC Mode)
Figure 49. AVDD_5V Power Supply Rejection Ratio,
100mVpp Supply Noise with Different Frequencies (TGC
Mode)
−65
−35
PSRR 1 CH
PSRR 8 CH
PSRR wrt supply tone (dB)
PSRR wrt supply tone (dB)
PSRR 1 CH
PSRR 8 CH
−70
−75
−80
−85
−90
5
10
100
Supply Frequency (kHz)
−37
−39
−41
−43
−45
500
5
100
Supply Frequency (kHz)
500
G000
Figure 51. AVDD_5V Power Supply Rejection Ratio,
Vnoise=100 mVpp, Freqnoise=5-500 KHz (CW Mode)
−50
−50
PSMR 1 CH
PSMR 8 CH
PSMR 1 CH
PSMR 8 CH
−55
PSMR (dBc)
−55
PSMR (dBc)
10
G000
Figure 50. AVDD Power Supply Rejection Ratio, Vnoise=100
mVpp, Freqnoise=5-500 KHz (CW Mode)
−60
−65
−70
1000 2000
−60
−65
5
10
100
Supply Frequency (kHz)
500
−70
5
G000
Figure 52. AVDD Power Supply Modulation Ratio, Vnoise=100
mVpp, Freqnoise=5.005-5.5 MHz (CW Mode)
10
100
Supply Frequency (kHz)
500
G000
Figure 53. AVDD_5V Power Supply Modulation Ratio,
Vnoise=100 mVpp, Freqnoise=5.005-5.5 MHz (CW Mode)
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Output Code
14000.0
12000.0
10000.0
8000.0
6000.0
4000.0
2000.0
0.0
0.0
0.5
1.0
1.5
Time (µs)
2.0
2.5
18000.0
14000.0
12000.0
10000.0
8000.0
6000.0
4000.0
2000.0
0.0
0.0
1.2
1.2
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−0.8
−1.0
−1.0
4.0
6.0
−1.2
0.0
8.0 10.0 12.0 14.0 16.0 18.0 20.0
Time (µs)
Figure 56. Pulse Inversion Asymmetrical Positive Input
10000.0
1.8
2.0
2.2
2.0
4.0
6.0
8.0 10.0 12.0 14.0 16.0 18.0 20.0
Time (µs)
10000
6000.0
47nF
15nF
8000
6000
4000
Output Code
4000.0
Output Code
1.0 1.2 1.5
Time (µs)
Figure 57. Pulse Inversion Asymmetrical Negative Input
Positive overload
Negative overload
Average
8000.0
2000.0
0.0
−2000.0
2000
0
−2000
−4000.0
−4000
−6000.0
−6000
−8000.0
−8000
−10000.0
0.0
0.8
0.0
−0.6
2.0
0.5
−0.2
−0.4
−1.2
0.0
0.2
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
2.5
Figure 55. VCNTL Response Time, LNA = 18dB and
PGA = 24dB
Input (V)
Input (V)
Figure 54. VCNTL Response Time, LNA = 18dB and
PGA = 24dB
1.0
2.0
3.0
Time (µs)
4.0
5.0
6.0
Figure 58. Pulse Inversion, Vin = 2Vpp, PRF = 1KHz,
Gain = 21dB
20
Output Code
Vcntl
16000.0
Vcntl (V)
16000.0
20000.0
Output Code
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
3.0
Output Code
Vcntl
18000.0
Vcntl (V)
TYPICAL CHARACTERISTICS (continued)
20000.0
−10000
0
0.5
1
1.5
2
2.5
3
Time (µs)
3.5
4
4.5
5
Figure 59. Overload Recovery Response vs. INM capacitor,
Vin = 50 mVpp/100 µVpp, Max Gain
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TYPICAL CHARACTERISTICS (continued)
2000
47nF
15nF
1600
1200
Output Code
800
400
0
−400
−800
−1200
−1600
−2000
1
1.5
2
2.5
3
3.5
Time (µs)
4
4.5
5
Figure 60. Overload Recovery Response vs. INM
capacitor(Zoomed), Vin = 50 mVpp/100 µVpp, Max Gain
Figure 61. Signal Chain Low Frequency Response with INM
Capacitor = 1 µF
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Serial Peripheral Interface (SPI) Operation
Register Write Description
Programming of different modes can be done through the serial interface formed by pins SEN (serial interface
enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. All these pins have a pull-down
resistor to GND of 20kΩ. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is
latched at every rising edge of SCLK when SEN is active (low). The serial data is loaded into the register at
every 24th SCLK rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits
are ignored. Data can be loaded in multiple of 24-bit words within a single active SEN pulse (there is an internal
counter that counts groups of 24 clocks after the falling edge of SEN). The interface can work with the SCLK
frequency from 20 MHz down to low speeds (few Hertz) and even with non-50% duty cycle SCLK. The data is
divided into two main portions: a register address (8 bits) and the data itself (16 bits), to load on the addressed
register. When writing to a register with unused bits, these should be set to 0. Figure 62 illustrates this process.
NOTE
RESET must be kept as '1' more than 100 ns. After resetting, >100 ns is recommended
before writing SPI registers.
Typically the VCA5807 responds to new register settings immediately after 24 bits (8-bit address and 16-bit data)
are written to VCA5807.
Start Sequence
End Sequence
SEN
t6
t7
t1
t2
Data Latched On Rising Edge of SCLK
SCLK
t3
SDATA
A7
A5
A6
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t4
t5
Start Sequence
End Sequence
RESET
T0384-01
Figure 62. Serial Interface Register Write Timing
Register Readout Description
The device includes an option where the contents of the internal registers can be read back. This may be useful
as a diagnostic test to verify the serial interface communication between the external controller and the VCA.
First, the bit (Reg0[1]) needs to be set to '1'. Then user should initiate a
serial interface cycle specifying the address of the register (A7-A0) whose content has to be read. The data bits
are "don’t care". The device will output the contents (D15-D0) of the selected register on the SDOUT pin. The
SDOUT has a typical delay t8 of 20 nS from the falling edge of the SCLK. For lower speed SCLK, SDOUT can be
latched on the rising edge of SCLK. For higher speed SCLK, that is, the SCLK period lesser than 60nS, it would
be better to latch the SDOUT at the next falling edge of SCLK. The following timing diagram shows this operation
(the time specifications follow the same information provided. In the readout mode, users still can access the
through SDATA/SCLK/SEN. To enable serial register writes, set the
bit back to '0'.
22
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Start Sequence
End Sequence
SEN
t6
t7
t1
t2
SCLK
t3
A7
SDATA
A6
A5
A4
A3
t4
A2
A1
A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D6
D5
D4
D3
D2
D1
D0
t8
t5
D15 D14 D13 D12 D11 D10 D9
SDOUT
D8
D7
Figure 63. Serial Interface Register Readout Timing
The VCA5807 SDOUT buffer is 3-stated and will get enabled only when 0[1] (REGISTER_READOUT_ENABLE)
is enabled. SDOUT pins from multiple VCA5807s can be tied together without any pull-up resistors. Level shifter
SN74AUP1T34 can be used to convert 3.3V logic to 2.5V/1.8V logics if needed.
SPI Timing Characteristics
Minimum values across full temperature range tMIN = –40°C to tMAX = 85°C, AVDD_5V = 5V, AVDD = 3.3V
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
t1
SCLK period
50
ns
t2
SCLK high time
20
ns
t3
SCLK low time
20
ns
t4
Data setup time
5
ns
t5
Data hold time
5
ns
t6
SEN fall to SCLK rise
8
ns
t7
Time between last SCLK rising edge to SEN rising edge
8
t8
SDOUT Delay
12
ns
20
28
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VCA Register Map
A reset process is required at the VCA5807 initialization stage. Initialization can be done in one of two ways:
1. Through a hardware reset, by applying a positive pulse in the RESET pin
2. Through a software reset, using the serial interface, by setting the SOFTWARE_RESET bit to high. Setting
this bit initializes the internal registers to the respective default values (all zeros) and then self-resets the
SOFTWARE_RESET bit to low. In this case, the RESET pin can stay low (inactive).
After reset, all VCA registers are set to ‘0’, that is, default setting. During register programming, all
reserved/unlisted register bits need to be set as ‘0’.Register settings are maintained when the VCA5807 is in
either partial power down mode or complete power down mode.
Table 1. VCA Register Map
ADDRESS ADDRESS Default
(DEC)
(HEX)
Value
FUNCTION
DESCRIPTION
0[0]
0x0[0]
0
SOFTWARE_RESET
0: Normal operation
1: Reset the device
0[1]
0[1]
0
REGISTER_READOUT_ENABLE
0:Disable readout
1: Enable readout of register at SDOUT Pin
51[0]
0x33[0]
0
RESERVED
0
51[3:1]
0x33[3:1]
0
LPF_PROGRAMMABILITY
000:
010:
011:
100:
51[4]
0x33[4]
0
PGA_INTEGRATOR_DISABLE
(PGA_HPF_DISABLE)
0: Enable
1: Disables offset integrator for PGA. Please see explanation
for the PGA integrator function in PROGRAMMABLE GAIN
AMPLIFIER (PGA) and PGA OUTPUT CONFIGURATION
section
51[7:5]
0x33[7:5]
0
PGA_CLAMP_LEVEL
Low Noise mode: 53[11:10]=00
000: –2 dBFS
010: 0 dBFS
1XX: Clamp is disabled
Low power/Medium Power mode; 53[11:10]=01/10
100: –2 dBFS
110: 0 dBFS
0XX: clamp is disabled
Note: At 000 setting, PGA output HD3 will be worsen by 3 dB
at –2 dBFS ADC input. In normal operation, clamp function can
be set as 000 in the low noise mode. The maximum PGA
output level can exceed 2Vpp with the clamp circuit enabled.
Note: in the low power and medium power modes,
PGA_CLAMP is disabled for saving power if 51[7]=0. Please
see PGA OUTPUT CONFIGURATION.
51[13]
0x33[13]
0
PGA_GAIN_CONTROL
0:24dB;
1:30dB.
52[4:0]
0x34[4:0]
0
ACTIVE_TERMINATION_
INDIVIDUAL_RESISTOR_CNTL
See Table 3 Reg 52[5] should be set as '1' to access these bits
52[5]
0x34[5]
0
ACTIVE_TERMINATION_
INDIVIDUAL_RESISTOR_ENABLE
0: Disable;
1: Enable internal active termination individual resistor control
52[7:6]
0x34[7:6]
0
PRESET_ACTIVE_ TERMINATIONS
00: 50ohm,
01: 100ohm,
10: 200ohm,
11: 400ohm.
(Note: the device will adjust resistor mapping (52[4:0])
automatically. 50ohm active termination is NOT supported in
12dB LNA setting. Instead, '00' represents high impedance
mode when LNA gain is 12dB)
52[8]
0x34[8]
0
ACTIVE TERMINATION ENABLE
0: Disable;
1: Enable active termination
24
15MHz,
20MHz,
30MHz,
10MHz
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Table 1. VCA Register Map (continued)
ADDRESS ADDRESS Default
(DEC)
(HEX)
Value
FUNCTION
DESCRIPTION
52[10:9]
0x34[10:9]
0
LNA_INPUT_CLAMP_SETTING
00:
01:
10:
11:
52[11]
0x34[11]
0
RESERVED
Set to 0
52[12]
0x34[12]
0
LNA_INTEGRATOR_DISABLE
(LNA_HPF_DISABLE)
0: Enable;
1: Disable offset integrator for LNA. Please see the explanation
for this function in the following section
52[14:13]
0x34[14:1
3]
0
LNA_GAIN
00:
01:
10:
11:
52[15]
0x34[15]
0
LNA_INDIVIDUAL_CH_CNTL
0: Disable;
1: Enable LNA individual channel control. See Register 57 for
details
53[7:0]
0x35[7:0]
0
PDN_CH
0: Normal operation;
1: Powers down corresponding channels. Bit7→CH8,
Bit6→CH7…Bit0→CH1. PDN_CH will shut down whichever
blocks are active depending on TGC mode or CW mode
53[8]
0x35[8]
0
RESERVED
Set to 0
53[9]
0x35[9]
0
LOW_NF
0: Normal operation
1: Enable low noise figure mode for high impedance probes
53[11:10]
0x35[11:1
0]
0
POWER_MODES
00: Low noise mode;
01: Low power mode. At 30dB PGA, total chain gain may
slightly change. See typical characteristics
10: Medium power mode. At 30dB PGA, total chain gain may
slightly change. See typical characteristics
11: Reserved
Note: in the low power and medium power modes,
PGA_CLAMP is disabled for saving power if 51[7]=0.
53[12]
0x35[12]
0
PDN_VCAT_PGA
0: Normal operation;
1: Power down VCAT (voltage-controlled-attenuator) and PGA
53[13]
0x35[13]
0
PDN_LNA
0: Normal operation;
1: Power down LNA only
53[14]
0x35[14]
0
VCA_PARTIAL_PDN
0: Normal operation;
1: Power down LNA, VCAT, and PGA partially(fast wake
response)
53[15]
0x35[15]
0
VCA_COMPLETE_PDN
0: Normal operation;
1: Power down LNA, VCAT, and PGA completely (slow wake
response). This bit can overwrite 53[14].
54[4:0]
0x36[4:0]
0
CW_SUM_AMP_GAIN_CNTL
Select Feedback resistor for the CW Amplifier as per Table 3
below
54[5]
0x36[5]
0
CW_16X_CLK_SEL
0: Accept differential clock;
1: Accept CMOS clock
54[6]
0x36[6]
0
CW_1X_CLK_SEL
0: Accept CMOS clock;
1: Accept differential clock
54[7]
0x36[7]
0
RESERVED
Set to 0
54[8]
0x36[8]
0
CW_TGC_SEL
0: TGC Mode;
1 : CW Mode
Note : VCAT and PGA are still working in the CW mode. They
should be powered down separately through 53[12]
54[9]
0x36[9]
0
CW_SUM_AMP_ENABLE
0: Enable CW summing amplifier;
1: Disable CW summing amplifier. Note: 54[9] is only effective
in the CW mode.
Auto setting
1.5Vpp
1.15Vpp
0.6Vpp
18dB;
24dB;
12dB;
Reserved
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Table 1. VCA Register Map (continued)
ADDRESS ADDRESS Default
(DEC)
(HEX)
Value
FUNCTION
DESCRIPTION
54[11:10]
0x36[11:1
0]
0
CW_CLK_MODE_SEL
00: 16X mode;
01: 8X mode;
10: 4X mode;
11: 1X mode;
Note: 0x3B[10]=0.
55[3:0]
0x37[3:0]
0
CH1_CW_MIXER_PHASE
55[7:4]
0x37[7:4]
0
CH2_CW_MIXER_PHASE
55[11:8]
0x37[11:8]
0
CH3_CW_MIXER_PHASE
55[15:12]
0x37[15:1
2]
0
CH4_CW_MIXER_PHASE
56[3:0]
0x38[3:0]
0
CH5_CW_MIXER_PHASE
56[7:4]
0x38[7:4]
0
CH6_CW_MIXER_PHASE
56[11:8]
0x38[11:8]
0
CH7_CW_MIXER_PHASE
56[15:12]
0x38[15:1
2]
0
CH8_CW_MIXER_PHASE
57[1:0]
0x39[1:0]
0
CH1_LNA_GAIN_CNTL
57[3:2]
0x39[3:2]
0
CH2_LNA_GAIN_CNTL
0000→1111, 16 different phase delays, see Table 6
00: 18dB;
01: 24dB;
10: 12dB;
11: Reserved
REG52[15] should be set as '1'
57[5:4]
0x39[5:4]
0
CH3_LNA_GAIN_CNTL
57[7:6]
0x39[7:6]
0
CH4_LNA_GAIN_CNTL
57[9:8]
0x39[9:8]
0
CH5_LNA_GAIN_CNTL
57[11:10]
0x39[11:1
0]
0
CH6_LNA_GAIN_CNTL
57[13:12]
0x39[13:1
2]
0
CH7_LNA_GAIN_CNTL
57[15:14]
0x39[15:1
4]
0
CH8_LNA_GAIN_CNTL
59[3:2]
0x3B[3:2]
0
HPF_LNA
00: 100KHz;
01: 50KHz;
10: 200KHz;
11: 150KHz
Note: the above frequencies is based on 0.015uF capacitors at
INMx.
59[6:4]
0x3B[6:4]
0
DIG_TGC_ATT_GAIN
000: 0dB attenuation;
001: 6dB attenuation;
N: ~N×6dB attenuation when 59[7] = 1
59[7]
0x3B[7]
0
DIG_TGC_ATT
0: Disable digital TGC attenuator;
1: Enable digital TGC attenuator
59[8]
0x3B[8]
0
CW_SUM_AMP_PDN
0: Power down CW summing amplifier;
1: Normal operation. Note: 59[8] is only effective in TGC test
mode.
59[9]
0x3B[9]
0
PGA_TEST_MODE
0: Normal CW operation;
1: PGA outputs appear at the CW outputs
59[10]
0x3B[10]
0
CW_32X_CLK_MODE_ENABLE
0: CW clock mode is determined by 0x36[11:10];
1: Enable CW 32X mode
26
00: 18dB;
01: 24dB;
10: 12dB;
11: Reserved
REG52[15] should be set as '1'
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VCA Register Description
LNA Input Impedances Configuration (Active Termination Programmability)
Different LNA input impedances can be configured through the register 52[4:0]. By enabling and disabling the
feedback resistors between LNA outputs and ACTx pins, LNA input impedance is adjustable accordingly. Table 2
describes the relationship between LNA gain and 52[4:0] settings. The input impedance settings are the same for
both TGC and CW paths.
The VCA5807 also has 4 preset active termination impedances as described in 52[7:6]. An internal decoder is
used to select appropriate resistors corresponding to different LNA gain.
Table 2. Register 52[4:0] Description
52[4:0]/0x34[4:0]
FUNCTION
00000
No feedback resistor enabled
00001
Enables 450 Ω feedback resistor
00010
Enables 900 Ω feedback resistor
00100
Enables 1800 Ω feedback resistor
01000
Enables 3600 Ω feedback resistor
10000
Enables 4500 Ω feedback resistor
Table 3. Register 52[4:0] vs LNA Input Impedances
52[4:0]/0x34[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
LNA:12dB
High Z
150 Ω
300 Ω
100 Ω
600 Ω
120 Ω
200 Ω
86 Ω
LNA:18dB
High Z
90 Ω
180 Ω
60 Ω
360 Ω
72 Ω
120 Ω
51 Ω
LNA:24dB
High Z
50 Ω
100 Ω
33 Ω
200 Ω
40 Ω
66.67 Ω
29 Ω
52[4:0]/0x34[4:0]
01000
01001
01010
01011
01100
01101
01110
01111
LNA:12dB
1200 Ω
133 Ω
240 Ω
92 Ω
400 Ω
109 Ω
171 Ω
80 Ω
LNA:18dB
720 Ω
80 Ω
144 Ω
55 Ω
240 Ω
65 Ω
103 Ω
48 Ω
LNA:24dB
400 Ω
44 Ω
80 Ω
31 Ω
133 Ω
36 Ω
57 Ω
27 Ω
52[4:0]/0x34[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
LNA:12dB
1500 Ω
136 Ω
250 Ω
94 Ω
429 Ω
111 Ω
176 Ω
81 Ω
LNA:18dB
900 Ω
82 Ω
150 Ω
56 Ω
257 Ω
67 Ω
106 Ω
49 Ω
LNA:24dB
500 Ω
45 Ω
83 Ω
31 Ω
143 Ω
37 Ω
59 Ω
27 Ω
52[4:0]/0x34[4:0]
11000
11001
11010
11011
11100
11101
11110
11111
LNA:12dB
667 Ω
122 Ω
207 Ω
87 Ω
316 Ω
102 Ω
154 Ω
76 Ω
LNA:18dB
400 Ω
73 Ω
124 Ω
52 Ω
189 Ω
61 Ω
92 Ω
46 Ω
LNA:24dB
222 Ω
41 Ω
69 Ω
29 Ω
105 Ω
34 Ω
51 Ω
25 Ω
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Programmable Gain for CW Summing Amplifier
Different gain can be configured for the CW summing amplifier through the register 54[4:0]. By enabling and
disabling the feedback resistors between the summing amplifier inputs and outputs, the gain is adjustable
accordingly to maximize the dynamic range of CW path. Table 4 describes the relationship between the summing
amplifier gain and 54[4:0] settings.
Table 4. Register 54[4:0] Description
54[4:0]/0x36[4:0]
FUNCTION
00000
No feedback resistor
00001
Enables 250 Ω feedback resistor
00010
Enables 250 Ω feedback resistor
00100
Enables 500 Ω feedback resistor
01000
Enables 1000 Ω feedback resistor
10000
Enables 2000 Ω feedback resistor
Table 5. Register 54[4:0] vs CW Summing Amplifier Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
00000
00001
00010
00011
00100
00101
00110
00111
N/A
0.50
0.50
0.25
1.00
0.33
0.33
0.20
01000
01001
01010
01011
01100
01101
01110
01111
2.00
0.40
0.40
0.22
0.67
0.29
0.29
0.18
10000
10001
10010
10011
10100
10101
10110
10111
4.00
0.44
0.44
0.24
0.80
0.31
0.31
0.19
11000
11001
11010
11011
11100
11101
11110
11111
1.33
0.36
0.36
0.21
0.57
0.27
0.27
0.17
Programmable Phase Delay for CW Mixer
Accurate CW beamforming is achieved through adjusting the phase delay of each channel. In the VCA5807, 16
different phase delays can be applied to each LNA output; and it meets the standard requirement of typical
1
λ
ultrasound beamformer, that is, 16 beamformer resolution. Table 4 describes the relationship between the
phase delays and the register 55 and 56 settings.
Table 6. CW Mixer Phase Delay vs Register Settings
CH1 - 55[3:0], CH2 - 55[7:4], CH3 - 55[11:8], CH4 - 55[15:12],
CH5- 56[3:0], CH6 - 56[7:4], CH7 - 56[11:8], CH8 - 56[15:12],
CHX_CW_MIXER_PHASE
PHASE SHIFT
0000
0001
0010
0011
0100
0101
0110
0111
0
22.5°
45°
67.5°
90°
112.5°
135°
157.5°
CHX_CW_MIXER_PHASE
1000
1001
1010
1011
1100
1101
1110
1111
PHASE SHIFT
180°
202.5°
225°
247.5°
270°
292.5°
315°
337.5°
28
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THEORY OF OPERATION
VCA5807 OVERVIEW
The VCA5807 is an integrated Voltage Controlled Amplifier (VCA) solution specifically designed for ultrasound
systems in which high performance and small size are required. The VCA5807 integrates a complete time-gaincontrol (TGC) imaging path and a continuous wave Doppler (CWD) path. It also enables users to select one of
various power/noise combinations to optimize system performance. The VCA5807 contains eight channels; each
channels includes a Low-Noise Amplifier (LNA), a Voltage Controlled Attenuator (VCAT), a Programmable Gain
Amplifier (PGA), a Low-pass Filter (LPF), and a CW mixer.
In addition, multiple features in the VCA5807 are suitable for ultrasound applications, such as active termination,
individual channel control, fast power up/down response, programmable clamp voltage control, fast and
consistent overload recovery, ands o on. Therefore, the VCA5807 brings premium image quality to
ultra–portable, handheld systems all the way up to high-end ultrasound systems. In addition, the VCA5807 can
support sonar applications, considering its excellent low frequency (1μF
CM_BYP
>1μF
VHIGH
RVCNTL
200Ω
VCNTLP IN
VCNTLM IN
RVCNTL
200Ω
CLOCK
INPUTS
SDATA
SCLK
SEN
VCA5807
PGA_OUTM7
VCA5807
RESET
PGA_OUTP8
PDN_FAST
DIGITAL
INPUTS
PGA_OUTM8
ANALOG INPUTS
ANALOG OUTPUTS
BIAS DECOUPLING
OUTPUTS
1μF ACT8
IN CH8
CLKM_16X
VCA5807
SOUT
1μF ACT6
IN CH6
Clock termination
depends on clock types
PECL, or CMOS
PDN_GLOBAL
OTHER
VCA5807
OUTPUT
CW_IP_AMPINP
REXT (optional)
CW_IP_OUTM
CCW
CW_IP_AMPINM
REXT (optional)
CW_IP_OUTP
CCW
OTHER
VCA5807
OUTPUT
CVCNTL
470pF
VCNTLP
VCNTLM
CVCNTL
470pF
VREF_IN
OTHER
VCA5807
OUTPUT
CW_QP_AMPINP
CW_QP_OUTM
CCW
CW_QP_AMPINM
REXT (optional)
CW_QP_OUTP
CCW
CAC R
SUM
CAC RSUM
CAC R
SUM
TO
SUMMING
AMP
CAC RSUM
CAC R
SUM
CAC RSUM
CAC R
SUM
REXT (optional)
TO
SUMMING
AMP
DNCs
AVSS
OTHER
VCA5807
OUTPUT
CAC RSUM
Figure 81. Application Circuit
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0.1 F
10
INP
PGA_OUTP
VCA5807
OUTPUTS
High Speed
12~14 Bit ADCs
ADS529x
2 pF
PGA_OUTM
INM
10
0.1 F
Note: The optional R-C filter (10 Ω and 2 pF) across the ADC inputs is to absorb the glitches caused by the opening
and closing of the sampling capacitors. See the corresponding ADC data sheets.
Figure 82. Typical Application Circuit between VCA5807 and ADC
VCA5807
OUTPUTS
PGA_OUTP
0.1mF
R
+V
R
OUTPUT
+
R
PGA_OUTM
-
0.1mF
0.1mF
-V
R
Note: R ≥ 500 Ω to meet the VCA Minimum load resistance of 1 KΩ.
Figure 83. Typical Application Circuit between VCA5807 and Operational Amplifier
A typical application circuit diagram is listed above. The configuration for each block is discussed below.
LNA CONFIGURATION
LNA Input Coupling and Decoupling
The LNA closed-loop architecture is internally compensated for maximum stability without the need of external
compensation components. The LNA inputs are biased at 2.4V and AC coupling is required. A typical input
configuration is shown in Figure 84. CIN is the input AC coupling capacitor. CACT is a part of the active termination
feedback path. Even if the active termination is not used, the CACT is required for the clamp functionality.
Recommended values for CACT ≥ 1µF and CIN are ≥ 0.1µF. A pair of clamping diodes is commonly placed
between the T/R switch and the LNA input. Schottky diodes with suitable forward drop voltage (that is, the
BAT754/54 series, the BAS40 series, the MMBD7000 series, or similar) can be considered depending on the
transducer echo amplitude.
42
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CLAMP
CACT
CIN
INPUT
Optional
Diodes
CBYPSS
ACTx
INPx
INMx
LNAx
DC Offset
Correction
Figure 84. LNA Input Configurations
This architecture minimizes any loading of the signal source that may otherwise lead to a frequency-dependent
voltage divider. The closed-loop design yields very low offsets and offset drift. CBYPASS (≥0.015µF) is used to set
the high-pass filter cut-off frequency and decouple the complimentary input. Its cut-off frequency is inversely
proportional to the CBYPASS value. The HPF cut-off frequency can be adjusted through the register 59[3:2] as
Table 8 lists. Low frequency signals at T/R switch output, such as signals with slow ringing, can be filtered out. In
addition, the HPF can minimize system noise from DC-DC converters, pulse repetition frequency (PRF) trigger,
and frame clock. Most ultrasound systems’ signal processing unit includes digital high-pass filters or band-pass
filters (BPFs) in FPGAs or ASICs. Further noise suppression can be achieved in these blocks. If low frequency
signal detection is desired in some applications, the LNA HPF can be disabled.
Table 8. LNA HPF Settings (CBYPASS = 15 nF)
Reg59[3:2] (0x3B[3:2])
Frequency
00
100 KHz
01
50 KHz
10
200 KHz
11
150 KHz
CM_BYP and VHIGH pins, which generate internal reference voltages, need to be decoupled with ≥1uF
capacitors. Bigger bypassing capacitors (>2.2uF) may be beneficial if low frequency noise exists in system.
LNA Noise Contribution
The noise spec is critical for LNA and it determines the dynamic range of entire system. The LNA of the
VCA5807 achieves low power and an exceptionally low-noise voltage of 0.63nV/√Hz, and a low current noise of
2.7pA/√Hz.
Typical ultrasonic transducer’s impedance Rs varies from tens of ohms to several hundreds of ohms. Voltage
noise is the dominant noise in most cases; however, the LNA current noise flowing through the source
impedance (Rs) generates additional voltage noise.
2
2
LNA _ Noise total = VLNAnoise
+ R2s ´ ILNAnoise
(5)
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The VCA5807 achieves low noise figure (NF) over a wide range of source resistances as shown in Figure 31,
Figure 32, and Figure 33.
In addition, a low noise figure mode has been implemented by optimizing the current noise and voltage noise
contribution. When high impedance transducers appear, the VCA5807's noise figure can be improved by
enabling the low noise figure mode (register 0x35[9]). Figure 34 shows the advantages of the low noise figure
mode.
Active Termination
In ultrasound applications, signal reflection exists due to long cables between transducer and system. The
reflection results in extra ringing added to echo signals in pulsed-wave (PW) mode. Since the axial resolution
depends on echo signal length, such ringing effect can degrade the axial resolution. Hence, either passive
termination or active termination, is preferred if good axial resolution is desired. Figure 85 shows three
termination configurations:
Rs
LNA
(a) No Termination
Rf
Rs
LNA
(b) Active Termination
Rs
Rt
LNA
(c) Passive Termination
S0499-01
Figure 85. Termination Configurations
Under the no termination configuration, the input impedance of the VCA5807 is about 6KΩ (8K//20pF) at 1 MHz.
Passive termination requires external termination resistor Rt, which contributes to additional thermal noise.
The LNA supports active termination with programmable values, as shown in Figure 86 .
44
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450Ω
900Ω
1800Ω
ACTx
3600Ω
4500Ω
INPx
Input
INMx
LNAx
S0500-01
Figure 86. Active Termination Implementation
The VCA5807 has four pre-settings 50,100, 200 and 400Ω which are configurable through the registers. Other
termination values can be realized by setting the termination switches shown in Figure 86. Register [52] is used
to enable these switches. The input impedance of the LNA under the active termination configuration
approximately follows:
ZIN =
Rf
AnLNA
1+
2
(6)
Table 2 lists the LNA RIN under different LNA gains. System designers can achieve fine tuning for different
probes.
The equivalent input impedance is given by Equation 7 where RIN (8K) and CIN (20pF) are the input resistance
and capacitance of the LNA.
ZIN =
Rf
/ /CIN / /RIN
AnLNA
1+
2
(7)
Therefore, the ZIN is frequency dependent and it decreases as frequency increases shown in Figure 9. Since
2MHz~10MHz is the most commonly used frequency range in medical ultrasound, this rolling-off effect doesn’t
impact system performance greatly. Active termination can be applied to both CW and TGC modes. Since each
ultrasound system includes multiple transducers with different impedances, the flexibility of impedance
configuration is a great plus.
Figure 31, Figure 32, and Figure 33 shows the NF under different termination configurations. It indicates that no
termination achieves the best noise figure; active termination adds less noise than passive termination. Thus
termination topology should be carefully selected based on each use scenario in ultrasound.
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LNA Gain Switch Response
The LNA gain is programmable through SPI. The gain switching time depends on the SPI speed as well as the
LNA gain response time. During the switching, glitches might occur and they can appear as artifacts in images.
LNA gain switching in a single imaging line may not be preferred, although digital signal processing might be
used here for glitch suppression.
NOTE
The clamp settings may change during LNA gain switching. The clamp settling time needs
to be considered when adjusting LNA gain dynamically, especially when overload signals
exceed the clamping voltage.
VOLTAGE-CONTROLLED-ATTENUATOR
The attenuator in the VCA5807 is controlled by a pair of differential control inputs, the VCNTLM/P pins. The
differential control voltage spans from 0V to 1.5V. This control voltage varies the attenuation of the attenuator
based on its linear-in-dB characteristic. Its maximum attenuation (minimum channel gain) appears at VCNTLP VCNTLM = 1.5V, and minimum attenuation (maximum channel gain) occurs at VCNTLP - VCNTLM = 0. The typical gain
range is 40dB and remains constant, independent of the PGA setting.
When only single-ended VCNTL signal is available, this 1.5Vpp signal can be applied on the VCNTLP pin with the
VCNTLM pin connected to ground. As the below figures show, TGC gain curve is inversely proportional to the
VCNTLP - VCNTLM.
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1.5V
VCNTLP
VCNTLM = 0V
X+40dB
TGC Gain
XdB
(a) Single-Ended Input at VCNTLP
1.5V
VCNTLP
0.75V
VCNTLM
0V
X+40dB
TGC Gain
XdB
(b) Differential Inputs at VCNTLP and VCNTLM
W0004-01
Figure 87. VCNTLP and VCNTLM Configurations
As discussed in the theory of operation, the attenuator architecture uses seven attenuator segments that are
equally spaced in order to approximate the linear-in-dB gain-control slope. This approximation results in a
monotonic slope; the gain ripple is typically less than ±0.5dB.
The control voltage input (VCNTLM/P pins) represents a high-impedance input. The VCNTLM/P pins of multiple
VCA5807 devices can be connected in parallel with no significant loading effects. When the voltage level
(VCNTLP-VCNTLM) is above 1.5V or below 0V, the attenuator continues to operate at its maximum attenuation level
or minimum attenuation level respectively. It is recommended to limit the voltage from -0.3V to 2V.
When the VCA5807 operates in CW mode, the attenuator stage remains connected to the LNA outputs.
Therefore, it is recommended to power down the VCAT and PGA using corresponding register bits. In this case,
VCNTLP-VCNTLM voltage does not matter.
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The VCA5807 gain-control input has a –3dB bandwidth of approximately 800KHz. This wide bandwidth, although
useful in many applications (that is, fast VCNTL response), can also allow high-frequency noise to modulate the
gain control input and finally affect the Doppler performance. In practice, this modulation can be avoided by
additional external filtering (RVCNTL and CVCNTL) at VCNTLM/P pins as Table 9 shows. However, the external filter's
cutoff frequency cannot be kept too low as this results in low gain response time. Without external filtering, the
gain control response time is typically less than 1 μs to settle within 10% of the final signal level of 1VPP
(–6dBFS) output as indicated in Figure 54 and Figure 55.
Typical VCNTLM/P signals are generated by an 8bit to 12bit 10MSPS digital to analog converter (DAC) and a
differential operation amplifier. TI’s DACs, such as TLV5626 and DAC7821/11 (10MSPS/12bit), could be used to
generate TGC control waveforms. Differential amplifiers with output common mode voltage control (that is,
THS4130 and OPA1632) can connect the DAC to the VCNTLM/P pins. The buffer amplifier can also be configured
as an active filter to suppress low frequency noise. More information can be found in the literatures SLOS318F
and SBAA150. The VCNTL vs Gain curves can be found in Figure 2. The below table also shows the absolute
gain vs VCNTLat room temperature, which may help program DAC correspondingly.
In PW Doppler and color Doppler modes, VCNTL noise should be minimized to achieve the best close-in phase
noise and SNR. Digital VCNTL feature is implemented to address this need in the VCA5807. In the digital VCNTL
mode, no external VCNTL is needed.
Table 9. VCNTLP – VCNTLM vs Gain Under Different LNA and PGA Gain Settings (Low Noise Mode and Room
Temperature)
VCNTLP–VCNTLM
(V)
Gain (dB)
LNA = 12 dB
PGA = 24 dB
Gain (dB)
LNA = 18 dB
PGA = 24 dB
Gain (dB)
LNA = 24 dB
PGA = 24 dB
Gain (dB)
LNA = 12 dB
PGA = 30 dB
Gain (dB)
LNA = 18 dB
PGA = 30 dB
Gain (dB)
LNA = 24 dB
PGA = 30 dB
0
35.8
41.8
47.8
41.6
47.6
53.6
0.1
33.3
39.3
45.3
39.1
45.1
51.1
0.2
30.4
36.4
42.4
36.2
42.2
48.2
0.3
27
33
39
32.8
38.8
44.8
0.4
23.3
29.3
35.3
29.1
35.1
41.1
0.5
20.2
26.2
32.2
26
32
38
0.6
16.6
22.6
28.6
22.4
28.4
34.4
0.7
13
19
25
18.8
24.8
30.8
0.8
9.7
15.7
21.7
15.5
21.5
27.5
0.9
5.7
11.7
17.7
11.5
17.5
23.5
1.0
2.2
8.2
14.2
8
14
20
1.1
-1.2
4.8
10.8
4.6
10.6
16.6
1.2
-3.2
2.8
8.8
2.6
8.6
14.6
1.3
-4.4
1.6
7.6
1.4
7.4
13.4
1.4
-4.7
1.3
7.3
1.1
7.1
13.1
1.5
-4.7
1.3
7.3
1.1
7.1
13.1
PGA OUTPUT CONFIGURATION
As illustrated in Figure 68, the PGA current clamping circuit can be enabled (register 51) to improve the overload
recovery performance of the VCA. If we measure the standard deviation of the output just after overload, for 0.5V
VCNTL, it is about 3.2 LSBs in normal case, that is, the output is stable in about 1 clock cycle after overload. With
the current clamp circuit disabled, the value approaches 4 LSBs meaning a longer time duration before the
output stabilizes; however, with the current clamp circuit enabled, there will be degradation in HD3 for PGA
output levels > -2dBFS. For example, for a –2dBFS output level, the HD3 degrades by approximately 3dB. In
order to maximize the output dynamic range, the maximum PGA output level can exceed 2Vpp (0 dBFS linear
output range) with the clamp circuit. Thus ADCs with excellent overload recovery performance should be
selected.
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NOTE
In the low power and medium power modes, PGA_CLAMP is disabled for saving power if
51[7]=0
Figure 82 and Figure 83 show that the PGA outputs can be further processed by either high speed 12-14 Bit
ADCs or operational amplifiers. The selection of ADCs or OPAMPs shall minimize performance impact of the
VCA5807, that is, selecting devices with significant lower input noise floor compared to VCA5807's output noise.
TI's multi-channel high-speed ADCs, such as ADS5294 and ADS5292 and low noise opamps OPA842 and
THS4130, are suitable candidates. In portable applications, lower power ADCs and OPAMPs may be selected.
The impact on performance degradation can be predicted by comparing the VCA5807 output noise to the total
noise of VCA5807 and its subsequent device.
The below figures show the SNR curves when VCA5807 is sampled by ADS5294. Better than 70dBFS SNR is
achieved. Further improvement is expected when a 16-bit ADC, e.g. ADS5263, is used.
Figure 88. SNR vs Gain at PGA Low Noise Mode
Figure 89. SNR vs Gain at PGA Low Power Mode
Figure 90. SNR vs Gain vs Power Modes at 24dB PGA
LOW FREQUENCY SUPPORT
The signal chain of the VCA5807 can handle signal frequency lower than 100 KHz, which enables the VCA5807
to be used not only in medical ultrasound applications but also in sonar applications. The PGA integrator has to
be turned off in order to enable the low frequency support. Meanwhile, a large capacitor like 1 µF can be used for
setting low corner frequency of the LNA DC offset correction circuit as shown in Figure 65. VCA5807's low
frequency response can be found in Figure 61.
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CW CONFIGURATION
CW Summing Amplifier
In order to simplify CW system design, a summing amplifier is implemented in the VCA5807 to sum and convert
8-channel mixer current outputs to a differential voltage output. Low noise and low power are achieved in the
summing amplifier while maintaining the full dynamic range required in CW operation.
This summing amplifier has 5 internal gain adjustment resistors which can provide 32 different gain settings
(register 54[4:0], Figure 86 and Table 4). System designers can easily adjust the CW path gain depending on
signal strength and transducer sensitivity. For any other gain values, an external resistor option is supported. The
gain of the summation amplifier is determined by the ratio between the 500Ω resistors after LNA and the internal
or external resistor network REXT/INT. Thus the matching between these resistors plays a more important role than
absolute resistor values. Better than 1% matching is achieved on chip. Due to process variation, the absolute
resistor tolerance could be higher. If external resistors are used, the gain error between I/Q channels or among
multiple VCAs may increase. It is recommended to use internal resistors to set the gain in order to achieve better
gain matching (across channels and multiple VCAs). With the external capacitor CEXT , this summing amplifier
has 1st order LPF response to remove high frequency components from the mixers, such as 2f0±fd. Its cut-off
frequency is determined by:
fHP =
1
2pRINT/EXT CEXT
(8)
Note that when different gain is configured through register 54[4:0], the LPF response varies as well.
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CEXT
REXT
250Ω
250Ω
RINT
500Ω
1000Ω
2000Ω
CW_AMPINP
CW_AMPINM
CW_OUTM
I/V Sum
Amp
CW_OUTP
250Ω
250Ω
500Ω
RINT
1000Ω
2000Ω
REXT
CEXT
S0501-01
Figure 91. CW Summing Amplifier Block Diagram
Multiple VCA5807s are usually utilized in parallel to expand CW beamformer channel count. These VCA5807s’
CW outputs can be summed and filtered externally further to achieve desired gain and filter response. AC
coupling capacitors CAC are required to block DC component of the CW carrier signal. CAC can vary from 1uF to
10s μF depending on the desired low frequency Doppler signal from slow blood flow. Multiple VCA5807s’ I/Q
outputs can be summed together with a low noise external differential amplifiers before 16/18-bit differential
audio ADCs. Ultralow noise differential precision amplifier OPA1632 and THS4130 can be considered.
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An alternative current summing circuit is shown in Figure 93. However this circuit only achieves good
performance when a lower noise operational amplifier is available compared to the VCA5807's internal summing
differential amplifier.
VCA No.4
VCA No.3
VCA No.2
ACT1
500 Ω
INP1
INPUT1
INM1
VCA No.1
Mixer 1
Clock
LNA1
500 Ω
ACT2
500 Ω
INP2
INPUT2
INM2
Ext Sum
Amp
Cext
Mixer 2
Clock
Rint/Rext
CW_AMPINP
CW_AMPINM
LNA2
I/V Sum
Amp
CW_OUTM
CW_OUTP
Rint/Rext
500 Ω
CAC
RSUM
Cext
CW I or Q CHANNEL
Structure
ACT8
500 Ω
INP8
INPUT8
INM8
Mixer 8
Clock
LNA8
500 Ω
S0502-01
Figure 92. CW circuit with Multiple VCA5807s (Voltage output mode)
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Dev No.X
ACT1
500
INM1
LNA1
+
INPUT1
Mixer 1
Clock
CW_AMPINP
CW_AMPINM
CM_BYP
500
ACT2
500
IN2
INPUT2
INM2
-
IN1
Dev No.2
Dev No.1
Prefer to use an ultra-low noise
fully differential amplifier with
high output driving current
Mixer 1
Clock
CW_AMPINP
CW_AMPINM
LNA2
500
+
CM_BYP
CW I or Q CHANNEL
Structure
INPUT8
INM8
-
500
IN8
+
ACT8
Mixer 1
Clock
LNA8
Ultra-low noise single-ended
amplifiers is an option as well
500
Figure 93. CW Circuit with Multiple VCA5807s (Current output mode)
The CW I/Q channels are well matched internally to suppress image frequency components in Doppler spectrum.
Low tolerance components and precise operational amplifiers should be used for achieving good matching in the
external circuits as well.
CW Clock Selection
The VCA5807 can accept differential LVDS, LVPECL, and other differential clock inputs as well as single-ended
CMOS clock. An internally generated VCM of 2.5V is applied to CW clock inputs, that is, CLKP_16X/ CLKM_16X
and CLKP_1X/ CLKM_1X. Since this 2.5V VCM is different from the one used in standard LVDS or LVPECL
clocks, AC coupling is required between clock drivers and the VCA5807 CW clock inputs. When CMOS clock is
used, CLKM_1X and CLKM_16X should be tied to ground. Common clock configurations are illustrated in
Figure 94. Appropriate termination is recommended to achieve good signal integrity.
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3.3 V
130 Ω
83 Ω
CDCM7005
CDCE7010
3.3 V 0.1 μF
VCA
CLOCKs
0.1 μF
130 Ω
LVPECL
(a) LVPECL Configuration
100 Ω
CDCE72010
0.1 μF
0.1 μF
VCA
CLOCKs
LVDS
(b) LVDS Configuration
0.1μF
0.1μF
CLOCK
SOURCE
0.1μF
VCA
CLOCKs
50 Ω
0.1μF
(c) Transformer Based Configuration
CMOS CLK
Driver
VCA
CMOS CLK
CMOS
(d) CMOS Configuration
S0503-01
Figure 94. Clock Configurations
The combination of the clock noise and the CW path noise can degrade the CW performance. The internal
clocking circuit is designed for achieving excellent phase noise required by CW operation. The phase noise of
the VCA5807 CW path is better than 155dBc/Hz at 1KHz offset. Consequently the phase noise of the mixer clock
inputs needs to be better than 155dBc/Hz.
In the 16, 8, 4 × ƒcw operations modes, low phase noise clock is required for 16, 8, 4 × ƒcw clocks (that is,
CLKP_16X/ CLKM_16X pins) in order to maintain good CW phase noise performance. The 1 × ƒcw clock (that is,
CLKP_1X/ CLKM_1X pins) is only used to synchronize the multiple VCA5807 chips and is not used for
demodulation. Thus 1 ƒcw clock’s phase noise is not a concern. Either a continue clock with a frequency of ƒcw or
a single pulse with a width >1/(Nƒcw) can be used.
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On the other hand, in the 1 × ƒcw operation mode, low phase noise clocks are required for both CLKP_16X/
CLKM_16X and CLKP_1X/ CLKM_1X pins since both of them are used for mixer demodulation. In general,
higher slew rate clock has lower phase noise; thus clocks with high amplitude and fast slew rate are preferred in
CW operation. In the CMOS clock mode, 5V CMOS clock can achieve the highest slew rate.
Clock phase noise can be improved by a divider as long as the divider’s phase noise is lower than the target
phase noise. The phase noise of a divided clock can be improved approximately by a factor of 20log10N dB
where N is the dividing factor of 16, 8, or 4. If the target phase noise of mixer LO clock 1 × ƒcw is 160dBc/Hz at
1KHz off carrier, the 16 × ƒcw clock phase noise should be better than 160-20log1016 = 136dBc/Hz. TI’s jitter
cleaners LMK048X/CDCM7005/CDCE72010 exceed this requirement and can be selected for the VCA5807. In
the 4X/1X modes, higher quality input clocks are expected to achieve the same performance since N is smaller.
Thus the 16X mode is a preferred mode since it reduces the phase noise requirement for system clock design. In
addition, the phase delay accuracy is specified by the internal clock divider and distribution circuit. In the 16X
operation mode, the CW operation range is limited to 8 MHz due to the 16X CLK. The maximum clock frequency
for the 16X CLK is 128 MHz. In the 8X, 4X, and 1X modes, higher CW signal frequencies up to 15 MHz can be
supported with small degradation in performance, e.g. the phase noise is degraded by 9 dB at 15 MHz,
compared to 2 MHz.
As the channel number in a system increases, clock distribution becomes more complex. It is not preferred to
use one clock driver output to drive multiple VCAs since the clock buffer’s load capacitance increases by a factor
of N. As a result, the falling and rising time of a clock signal is degraded. A typical clock arrangement for multiple
VCA5807s is illustrated in Figure 95. Each clock buffer output drives one VCA5807 in order to achieve the best
signal integrity and fastest slew rate, that is, better phase noise performance. When clock phase noise is not a
concern, thai is. the 1 × ƒcw clock in the 32, 16, 8, 4 × ƒcw operation modes, one clock driver output may excite
more than one VCA5807s. Nevertheless, special considerations should be applied in such a clock distribution
network design. In typical ultrasound systems, it is preferred that all clocks are generated from a same clock
source, such as 16 × ƒcw , 1 × ƒcw clocks, audio ADC clocks, RF ADC clock, pulse repetition frequency signal,
frame clock and so on. By doing this, interference due to clock asynchronization can be minimized
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FPGA Clock/
Noisy Clock
n×16×CW Freq
LMK048K
CDCE72010/
CDCM7005
16X CW
CLK
1X CW
CLK
CDCLVP1208
LMK0030x
LMK01000
CDCLVP1208
LMK0030x
LMK01000
8 Synchronized
16X CW CLKs
8 Synchronized
1X CW CLKs
DEV
DEV
DEV
DEV
DEV
DEV
DEV
DEV
Figure 95. CW Clock Distribution
CW Supporting Circuits
As a general practice in CW circuit design, in-phase and quadrature channels should be strictly symmetrical by
using well matched layout and high accuracy components.
In systems, additional high-pass wall filters (20Hz to 500Hz) and low-pass audio filters (10KHz to 100KHz) with
multiple poles are usually needed. Since CW Doppler signal ranges from 20Hz to 20KHz, noise under this range
is critical. Consequently low noise audio operational amplifiers are suitable to build these active filters for CW
post-processing, that is, OPA1632, OPA2211, LME49990, LMH6629, or THS4130 . More filter design techniques
can be found from www.ti.com. TI’s active filter design tool http://focus.ti.com/docs/toolsw/folders/print/filterdesigner.html
The filtered audio CW I/Q signals are sampled by audio ADCs and processed by DSP or PC. Although CW
signal frequency is from 20 Hz to 20 KHz, higher sampling rate ADCs are still preferred for further decimation
and SNR enhancement. Due to the large dynamic range of CW signals, high resolution ADCs (≥16bit) are
required, such as ADS8413 (2MSPS/16it/92dBFS SNR) and ADS8472 (1MSPS/16bit/95dBFS SNR). ADCs for
in-phase and quadature-phase channels must be strictly matched, not only amplitude matching but also phase
matching, in order to achieve the best I/Q matching,. In addition, the in-phase and quadrature ADC channels
must be sampled simultaneously.
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POWER MANAGEMENT
Power/Performance Optimization
The VCA5807 has options to adjust power consumption and meet different noise performances. This feature
would be useful for portable systems operated by batteries when low power is more desired. Please refer to
characteristics information listed in the table of electrical characteristics as well as the typical characteristic plots.
Power Management Priority
Power management plays a critical role to extend battery life and ensure long operation time. The VCA5807 has
fast and flexible power down/up control which can maximize battery life. The VCA5807 can be powered down/up
through external pins or internal registers. The following table indicates the affected circuit blocks and priorities
when the power management is invoked. In the device, all the power down controls are logically ORed to
generate final power down for different blocks. Thus, the higher priority controls can cover the lower priority ones.
The VCA5807 register settings are maintained when the VCA5807 is in either partial power down mode or
complete power down mode.
Table 10. Power Management Priority
Pin
Name
Blocks
Priority
PDN_GLOBAL
All
High
Medium
Pin
PDN_FAST
LNA + VCAT+ PGA
Register
VCA_PARTIAL_PDN
LNA + VCAT+ PGA
Low
Register
VCA_COMPLETE_PDN
LNA + VCAT+ PGA
Medium
Register
PDN_VCAT_PGA
VCAT + PGA
Lowest
Register
PDN_LNA
LNA
Lowest
Partial Power-Up/Down Mode
The partial power up/down mode is also called as fast power up/down mode. In this mode, most amplifiers in the
signal path are powered down, while the internal reference circuits remain active.
The partial power down function allows the VCA5807 to be wake up from a low-power state quickly. This
configuration ensures that the external capacitors are discharged slowly; thus a minimum wake-up time is
needed as long as the charges on those capacitors are restored. The VCA wake-up response is typically about 2
μs or 1% of the power down duration whichever is larger. The longest wake-up time depends on the capacitors
connected at INP and INM, as the wake-up time is the time required to recharge the caps to the desired
operating voltages. For 0.1μF at INP and 15nF at INM can give a wake-up time of 2.5ms. For larger capacitors
this time will be longer. Thus, the VCA5807 wake-up time is more dependent on the VCA wake-up time. The
power-down time is instantaneous, less than 1µs.
This fast wake-up response is desired for portable ultrasound applications in which the power saving is critical.
The pulse repetition frequency of a ultrasound system could vary from 50KHz to 500Hz, while the imaging depth
(that is, the active period for a receive path) varies from 10 μs to hundreds of us. The power saving can be
significant when a system’s PRF is low. In some cases, only the VCA would be powered down while the ADC
keeps running normally to ensure minimum impact to FPGAs.
In the partial power-down mode, the VCA5807 typically dissipates only 12.5 mW/ch, representing a >80% power
reduction compared to the normal operating mode. This mode can be set using either pin PDN_FAST or register
bit VCA_PARTIAL_PDN.
Complete Power-Down Mode
To achieve the lowest power dissipation of 0.7 mW/CH, the VCA5807 can be placed into a complete power-down
mode. This mode is controlled through the registers VCA_COMPLETE_PDN or PDN_GLOBAL pin. In the
complete power-down mode, all circuits including reference circuits within the VCA5807 are powered down; and
the capacitors connected to the VCA5807 are discharged. The wake-up time depends on the time needed to
recharge these capacitors. The wake-up time depends on the time that the VCA5807 spends in shutdown mode.
0.1μF at INP and 15nF at INM can give a wake-up time close to 2.5ms.
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Power Saving in CW Mode
Usually only half the number of channels in a system are active in the CW mode. Thus the individual channel
control through VCA_PDN_CH can power down unused channels and save power consumption greatly.
Under the default register setting in the CW mode, the voltage controlled attenuator, PGA, is still active. During
the debug phase, both the PW and CW paths can be running simultaneously. In real operation, these blocks
need to be powered down manually.
TEST MODES
When direct probing VCA outputs is not feasible, the VCA5807 has a test mode in which the CH7 and CH8 PGA
outputs can be brought to the CW pins. By monitoring these CW pins, the functionality of VCA operation can be
verified. The PGA outputs are connected to the virtual ground pins of the summing amplifier (CW_IP_AMPINM/P,
CW_QP_AMPINM/P) through 5KΩ resistors. The PGA outputs can be monitored at the summing amplifier
outputs when the LPF capacitors CEXT are removed. Note that the signals at the summing amplifier outputs are
attenuated due to the 5KΩ resistors. The attenuation coefficient is RINT/EXT/5KΩ
If users would like to check the PGA outputs without removing CEXT, an alternative way is to measure the PGA
outputs directly at the CW_IP_AMPINM/P and CW_QP_AMPINM/P when the CW summing amplifier is powered
down
Some registers are related to this test mode. PGA Test Mode Enable: Reg59[9]; Buffer Amplifier Power Down
Reg59[8]; and Buffer Amplifier Gain Control Reg54[4:0]. Based on the buffer amplifier configuration, the registers
can be set in different ways:
Configuration 1:
In this configuration, the test outputs can be monitored at CW_AMPINP/M
Reg59[9]=1 ;Test mode enabled
Reg59[8]=0 ;Buffer amplifier powered down
Configuration 2:
In this configuration, the test outputs can be monitored at CW_OUTP/M
Reg59[9]=1 ;Test mode enabled
Reg59[8]=1 ;Buffer amplifier powered on
Reg54[4:0]=10H; Internal feedback 2K resistor enabled. Different values can be used as well
PGA_P
Cext
5K
ACT
500 Ω
INP
INPUT
INM
Mixer
Clock
Rint/Rext
CW_AMPINP
CW_AMPINM
LNA
500 Ω
CW_OUTM
I/V Sum
Amp
Rint/Rext
CW_OUTP
5K
Cext
PGA_M
S0504-01
Figure 96. VCA5807 PGA Test Mode
58
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Product Folder Links: VCA5807
VCA5807
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SLOS727 – DECEMBER 2012
POWER SUPPLY, GROUNDING AND BYPASSING
In a mixed-signal system design, power supply and grounding design plays a significant role. In most cases, it
should be adequate to lay out the printed circuit board (PCB) to use a single ground plane for the VCA5807.
Care should be taken that this ground plane is properly partitioned between various sections within the system to
minimize interactions between analog and digital circuitry. In addition, optical isolator or digital isolators, such as
ISO7240, can separate the analog portion from the digital portion completely. Consequently they prevent digital
noise to contaminate the analog portion. Table 10 lists the related circuit blocks for each power supply.
Table 11. Supply vs Circuit Blocks
Power Supply
Ground
Circuit Blocks
AVDD (3.3VA)
AVSS
LNA, attenuator, PGA with clamp
and BPF, reference circuits, CW
summing amplifier, CW mixer,
VCA SPI
AVDD_5V (5VA)
AVSS
LNA, CW clock circuits, reference
circuits
All bypassing and power supplies for the VCA5807 should be referenced to their corresponding ground planes.
All supply pins should be bypassed with 0.1µF ceramic chip capacitors (size 0603 or smaller). In order to
minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible.
Where double-sided component mounting is allowed, these capacitors are best placed directly under the
package. In addition, larger bipolar decoupling capacitors 2.2µF to 10µF, effective at lower frequencies) may also
be used on the main supply pins. These components can be placed on the PCB in proximity (< 0.5 in or 12.7
mm) to the VCA5807 itself.
The VCA5807 has a number of reference supplies needed to be bypassed, such CM_BYP, VHIGH, and
VREF_IN. These pins should be bypassed with at least 1µF; higher value capacitors can be used for better lowfrequency noise suppression. For best results, choose low-inductance ceramic chip capacitors (size 0402, > 1µF)
and place them as close as possible to the device pins.
High-speed mixed signal devices are sensitive to various types of noise coupling. One primary source of noise is
the switching noise from the serializer and the output buffer/drivers. For the VCA5807, care has been taken to
ensure that the interaction between the analog and digital supplies within the device is kept to a minimum
amount. The extent of noise coupled and transmitted from the digital and analog sections depends on the
effective inductances of each of the supply and ground connections. Smaller effective inductance of the supply
and ground pins leads to improved noise suppression. For this reason, multiple pins are used to connect each
supply and ground sets. It is important to maintain low inductance properties throughout the design of the PCB
layout by use of proper planes and layer thickness.
BOARD LAYOUT
Proper grounding and bypassing, short lead length, and the use of ground and power-supply planes are
particularly important for high-frequency designs. Achieving optimum performance with a high-performance
device such as the VCA5807 requires careful attention to the PCB layout to minimize the effects of board
parasitics and optimize component placement. A multilayer PCB usually ensures best results and allows
convenient component placement.
In addition, appropriate delay matching should be considered for the CW clock path, especially in systems with
high channel count. For example, if clock delay is half of the 16x clock period, a phase error of 22.5°C could
exist. Thus the timing delay difference among channels contributes to the beamformer accuracy.
To avoid noise coupling through supply pins, it is recommended to keep sensitive input pins, such as
INM, INP, ACT pins always from the AVDD 3.3 V and AVDD 5V planes. For example, either the traces or
vias connected to these pins should NOT be routed across the AVDD 3.3 V and AVDD 5V planes.
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Product Folder Links: VCA5807
59
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
VCA5807PZP
ACTIVE
HTQFP
PZP
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
VCA5807
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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