VFC32KUG4

VFC32 ® Voltage-to-Frequency and Frequency-to-Voltage CONVERTER FEATURES DESCRIPTION ● OPERATION UP TO 500kHz The VFC32 voltage-to-frequency converter provides an output frequency accurately proportional to its input voltage. The digital open-collector frequency output is compatible with all common logic families. Its integrating input characteristics give the VFC32 excellent noise immunity and low nonlinearity. ● EXCELLENT LINEARITY ±0.01% max at 10kHz FS ±0.05% max at 100kHz FS ● V/F OR F/V CONVERSION ● MONOTONIC ● VOLTAGE OR CURRENT INPUT Full-scale output frequency is determined by an external capacitor and resistor and can be scaled over a wide range. The VFC32 can also be configured as a frequency-to-voltage converter. APPLICATIONS The VFC32 is available in 14-pin plastic DIP, SO-14 surface-mount, and metal TO-100 packages. Commercial, industrial, and military temperature range models are available. ● INTEGRATING A/D CONVERTER ● SERIAL FREQUENCY OUTPUT ● ISOLATED DATA TRANSMISSION ● FM ANALOG SIGNAL MOD/DEMOD ● MOTOR SPEED CONTROL ● TACHOMETER VOUT Comparator Input +VCC fOUT –In One-Shot +In Common VFC32 –VCC One-Shot Capacitor International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 © SBVS015 1977 Burr-Brown Corporation PDS-372G Printed in U.S.A. October, 1998 SPECIFICATIONS At TA = +25°C and VCC = ±15V, unless otherwise noted. VFC32KP, KU PARAMETER CONDITIONS INPUT (V/F CONVERTER) FOUT = VIN/7.5 R1 C1 Voltage Range(1) Positive Input Negative Input Current Range(1) Bias Current Inverting Input Noninverting Input Offset Voltage(2) Differential Impedance Common-mode Impedance MIN TYP >0 >0 >0 INPUT (F/V CONVERTER) VOUT = 7.5 R1 C1 FIN Impedance Logic “1” Logic “0” Pulse-width Range ACCURACY Linearity Error(3) Offset Error Input Offset Votlage(2) Offset Drift(6) Gain Error(2) Gain Drift(6) Full Scale Drift (offset drift and gain drift)(6, 7) Power Supply Sensitivity MIN +0.25mA x R1 –10 +0.25 MIN ✽ ✽ ✽ ✽ ✽ ✽ 500 || 3 ✽ ✽ 150 || 10 +1.0 –0.05 ✽ ✽ ✽ ✽ ✽ 300 || 3 50 || 10 0.1 100 250 4 150k/FMAX VFC32SM MAX ✽ 300 || 10 MAX UNITS ✽ ✽ V ✽ ✽ ✽ ✽ V mA ✽ ✽ ✽ nA nA mV kΩ || pF ✽ ✽ ✽ ✽ ✽ ✽ TYP ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ MΩ || pF ✽ ✽ ✽ kΩ || pF V V µs ±0.005 ±0.010(4) ✽ ✽ ✽ ✽ % of FSR(5) ±0.025 ±0.05 ✽ ✽ ✽ ✽ % of FSR ±0.05 1 ±3 5 ±75 ±75 f = 10kHz f = 10kHz TYP ✽ ✽ ✽ ✽ 20 100 1 650 || 10 0.01Hz ≤ Oper Freq ≤ 10kHz 0.1Hz ≤ Oper Freq ≤ 100kHz 0.5Hz ≤ Oper Freq ≤ 500kHz VFC32BM MAX f = DC, ±VCC = 12VDC to 18VDC ✽ ✽ ✽ ✽ ±50 ±50 4 ±0.015 ✽ ✽ ✽ ✽ ✽ ±70 ±70 ±100 ±100 % of FSR ✽ ±150 ±150 mV ppm of FSR/°C % of FSR ppm/°C ppm of FSR/°C ✽ % of FSR/% ✽ ✽ V ✽ ✽ µA ✽ ✽ V s ns ✽ ✽ V mA Ω pF ✽ OUTPUT (V/F CONVERTER) (open collector output) ISINK = 8mA Voltage, Logic “0” Leakage Current, Logic “1” Voltage, Logic “1” 0 VO = 15V External Pull-up Resistor Required (see Figure 4) For Best Linearity IOUT = 5mA, CLOAD = 500pF Pulse Width Fall Time 0.2 0.4 0.01 1.0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ VPU ✽ 0.25/FMAX ✽ ✽ 400 OUTPUT (F/V CONVERTER) VOUT IO ≤ 7mA VO ≤ 7VDC Closed Loop Without Oscillation Voltage Current Impedance Capacitive Load DYNAMIC RESPONSE Full Scale Frequency Dynamic Range Settling Time Overload Recovery ✽ ✽ 0 to +10 +10 500(8) (V/F) to Specified Linearity for a Full Scale Input Step < 50% Overload ✽ ✽ (9) (9) ±11 TEMPERATURE RANGE Specification Operating Storage ✽ ✽ 1 100 6 POWER SUPPLY Rated Voltage Voltage Range Quiescent Current ✽ ✽ 0 –25 –25 ±15 ±5.5 ±20 ±6.0 +70 +85 +85 –25 –55 –65 ✽ ✽ kHz decades ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ +85 +125 +150 –55 –55 –65 V V mA +125 +125 +150 °C °C °C ✽ Specification the same as VFC32KP. NOTES: (1) A 25% duty cycle (0.25mA input current) is recommended for best linearity. (2) Adjustable to zero. See Offset and Gain Adjustment section. (3) Linearity error is specified at any operating frequency from the straight line intersecting 90% of full scale frequency and 0.1% of full scale frequency. See Discussion of Specifications section. Above 200kHz, it is recommended all grades be operated below +85°C. (4) ±0.015% of FSR for negative inputs shown in Figure 5. Positive inputs are shown in Figure 1. (5) FSR = Full Scale Range (corresponds to full scale frequency and full scale input voltage). (6) Exclusive of external components’ drift. (7) Positive drift is defined to be increasing frequency with increasing temperature. (8) For operations above 200kHz up to 500kHz, see Discussion of Specifications and Installation and Operation sections. (9) One pulse of new frequency plus 1µs. VFC32 2 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................................................................... ±22V Output Sink Current (FOUT ) ................................................................ 50mA Output Current (VOUT) ...................................................................... +20mA Input Voltage, –Input ..................................................................... ±Supply Input Voltage, +Input ..................................................................... ±Supply Comparator Input .......................................................................... ±Supply Storage Temperature Range: VFC32BM, SM ............................................................. –65°C to +150°C VFC32KP, KU ................................................................ –25°C to +85°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) VFC32KP VFC32BM VFC32SM VFC32KU 14-Pin Plastic DIP TO-100 Metal TO-100 Metal SO-14 SOIC 010 007 007 235 TEMPERATURE RANGE 0°C to 70°C –25°C to +85°C –55°C to +125°C 0°C to +70°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PIN CONFIGURATIONS Top View M Package (TO-100) P Package U Package (Epoxy Dual-in-line) VOUT –In –VCC (Case) 10 Input Amp 2 9 Switch 3 One-Shot Capacitor 1 Oneshot 8 4 7 5 NC +VCC Common Comparator Input –In 1 NC 2 13 VOUT NC 3 12 +VCC –VCC 4 11 Common One-Shot Capacitor 5 NC 6 fOUT 7 6 fOUT Input Amp Switch +In Oneshot 14 +In 10 Comparator Input 9 NC 8 NC NC = no internal connection External connection permitted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 3 VFC32 TYPICAL PERFORMANCE CURVES At TA = +25°C and VCC = ±15V, unless otherwise noted. LINEARITY ERROR vs OPERATING FREQUENCY LINEARITY ERROR vs FULL SCALE FREQUENCY 1 fFULL SCALE = 10kHz, 25% Duty Cycle TA = +25°C Linearity Error (Hz) Duty Cycle = 25% at Full Scale 0.01 TA = +25°C 0.001 0.5 0 –0.5 –1.0 1k 10k 100k 1M 0 1k 2k Full Scale Frequency (Hz) 3k 1000 100 (SM, KP, KU) (BM) 10 1k 10k 100k Full Scale Frequency (Hz) VFC32 4k 5k 6k 7k Operating Frequency (Hz) FULL SCALE DRIFT vs FULL SCALE FREQUENCY Full Scale Temp Drift (ppm of FSR/°C) Typical Linearity Error (% of FSR) 0.10 4 1M 8k 9k 10k APPLICATION INFORMATION approximately 2.5Vp-p integrator voltage waveform. If C2’s value is made too low, the integrator output voltage can exceed its linear output swing, resulting in a nonlinear response. Using C2 values larger than shown in Figure 2 is acceptable. Figure 1 shows the basic connection diagram for frequencyto-voltage conversion. R1 sets the input voltage range. For a 10V full-scale input, a 40kΩ input resistor is recommended. Other input voltage ranges can be achieved by changing the value of R1. V FS R1 = (1) 0.25mA Accuracy or temperature stability of C2 is not critical because its value does not directly affect the output frequency. For best linearity, however, C2 should have low leakage and low dielectric absorption. Polycarbonate and other film capacitors are generally excellent. Many ceramic types are adequate, but some low-voltage ceramic capacitor types may degrade nonlinearity. Electrolytic types are not recommended. R1 should be a metal film type for good stability. Manufacturing tolerances can produce approximately ±10% variation in output frequency. Full-scale output frequency can be trimmed by adjusting the value of R1—see Figure 3. The full-scale output frequency is determined by C1. Values shown in Figure 1 are for a full-scale output frequency of 10kHz. Values for other full-scale frequencies can be read from Figure 2. Any variation in C1—tolerance, temperature drift, aging—directly affect the output frequency. Ceramic NPO or silver-mica types are a good choice. FREQUENCY OUTPUT PIN The frequency output terminal is an open-collector logic output. A pull-up resistor is usually connected to a 5V logic supply to create standard logic-level pulses. It can, however, be connected to any power supply up to +VCC. Output pulses have a constant duration and positive-going during the oneshot period. Current flowing in the open-collector output transistor returns through the Common terminal. This terminal should be connected to logic ground. For full-scale frequencies above 200kHz, use larger capacitor values as indicated in Figure 2, with R1 = 20kΩ. The value of the integrating capacitor, C2, does not directly influence the output frequency, but its value must be chosen within certain bounds. Values chosen from Figure 2 produce fO VINT Pull-Up Voltage 0V ≤ VPU ≤ +VCC +15V C2 10nF film +5V 0.1µF VINT RPU 4.7kΩ R1 40kΩ fOUT VIN 0 to 10kHz One-Shot 0 to 10V VFC32 0.1µF Pinout shown is for DIP or SOIC packages. C1 3.3nF NPO Ceramic –15V FIGURE 1. Voltage-to-Frequency Converter Circuit. 5 VFC32 VPU ≤ 8mA RPU FREQUENCY-TO-VOLTAGE CONVERSION PRINCIPLES OF OPERATION Figure 4 shows the VFC32 connected as a frequency-tovoltage converter. The capacitive-coupled input network C3, R6 and R7 allow standard 5V logic levels to trigger the comparator input. The comparator triggers the one-shot on the falling edge of the frequency input pulses. Threshold voltage of the comparator is approximately –0.7V. For frequency input waveforms less than 5V logic levels, the R6/R7 voltage divider can be adjusted to a lower voltage to assure that the comparator is triggered. The VFC32 operates on a principle of charge balance. The signal input current is equal to VIN/R1. This current is integrated by input op amp and C2, producing a downward ramping integrator output voltage. When the integrator output ramps to the threshold of the comparator, the one-shot is triggered. The 1mA reference current is switched to the integrator input during the one-shot period, causing the integrator output ramp upward. After the one-shot period, the integrator again ramps downward. The value of C1 is chosen from Figure 2 according to the full-scale input frequency. C2 smooths the output voltage waveform. Larger values of C2 reduce the ripple in the output voltage. Smaller values of C2 allow the output voltage to settle faster in response to a change in input frequency. Resistor R1 can be trimmed to achieve the desired output voltage at the full-scale input frequency. The oscillation process forces a long-term balance of charge (or average current) between the input signal current and the reference current. The equation for charge balance is: I IN = I R(AVERAGE) (2) V IN = f O t OS (1mA) R1 (3) 0.1µF Where: fO is the output frequency tOS is the one-shot period, equal to tOS = 7500 C1 (Farads) C2 Capacitor Value 10nF 1nF 33,000pF C1 = – 30pF fFS (kHz) The values suggested for R1 and C1 are chosen to produce a 25% duty cycle at full-scale frequency output. For full-scale frequencies above 200kHz, the recommended values produce a 50% duty cycle. R1 = 40kΩ Above 200kHz Full-Scale 66,000pF C1 = – 30pF fFS (kHz) 100pF R1 = 20kΩ 10pF 1k 10k (4) 100k 1M Full Scale Frequency (Hz) FIGURE 2. Capacitor Value Selection. VINT C2 0.1µF 13 Gain Trim 10kΩ VIN 10 +5V +15V 4.7kΩ 12 7 35kΩ 1 One-Shot 14 +15V 10MΩ Offset Trim 11 1mA 100kΩ VFC32 –15V 4 Pinout shown is for DIP and SOIC packages. –15V FIGURE 3. Gain and Offset Voltage Trim Circuit. VFC32 6 5 C1 33nF fO +15V 2.5V 0V 0 to 10kHz 0V –2.5V 12kΩ 500pF fIN 5V Logic Input C2 0.1µF 2.2kΩ VO 0 to 10V R1 40kΩ +15V 13 12 10 7 10MΩ 1 +15V One-Shot 14 100kΩ –15V 11 VFC32 4 5 C1 3.3nF –15V FIGURE 4. Frequency-to-Voltage Converter Circuit. +15V +5V 0.1µF C2 2nF 13 12 10 7 1 VIN One-Shot 14 fOUT 0 to 50kHz 0V to –10V R1 40kΩ 11 VFC32 Nonlinearity may be higher than specified due to common-mode voltage on op amp input. 0.1µF 4 5 C1 650pF Pinout shown is for DIP or SOIC package. –15V FIGURE 5. V/F Converter—Negative Input Voltage. 7 VFC32 NC PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) VFC32KP ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 VFC32KP VFC32KPG4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 VFC32KP VFC32KU ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 VFC32KU VFC32KU/2K5 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 VFC32KU VFC32KUE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 VFC32KU (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of