VSP2101

® VSP 210 1 VSP2101 CCD SIGNAL PROCESSOR For Digital Cameras TM FEATURES q CCD SIGNAL PROCESSING: Correlated Double Sampling Black Level Clamping –2 to +34dB Gain Ranging High SNR: 53dB q 10-BIT A/D CONVERSION: Up to 27MHz Conversion Rate No Missing Codes q PORTABLE OPERATION: Low Voltage: 2.7V to 3.6V Low Power: 190mW at 3.0V q LOW POWER: 160mW at 2.7V q POWER-DOWN MODE: 18mW DESCRIPTION The VSP2101Y is a complete digital camera IC, providing signal conditioning and 10-bit analog-to-digital conversion for the output of a CCD array. The primary CCD channel provides correlated double sampling to extract the video information from the pixels, –2dB to +34dB gain ranging with digital control for varying illumination conditions, and black level clamping for an accurate black reference. Input signal clamping and offset correction of the CDS is also performed. The stable gain control is linear in dB. Additionally, the black level is quickly recovered after gain change. An on-chip general purpose 10-bit digital-to-analog converter allows you to obtain analog control voltage for iris control. The VSP2101Y is available in a 48-lead LQFP package and operates from a single +3V supply. APPLICATIONS q q q q VIDEO CAMERAS DIGITAL STILL CAMERAS PC CAMERAS SECURITY CAMERAS REFCK DATCK WRT SD SCLK DAC OUT OB ADCK DRVDD C Serial Port Register 10-Bit D/A Converter (DAC1) A/D Timing Control 10-Bit D/A Converter (DAC0) Black Level Auto-Zero CCD D Correlated Double Sampling Clamp +6dB Log VCA +28dB 10-Bit A/D Converter Output Latch 10-Bit Digital Output CCD Out CCD R Dummy Pixel Auto- Zero A/D Reference DUMC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1506B Printed in U.S.A. June, 1999 SPECIFICATIONS At TA = +25°C, all power supply voltages = +3.0V, and conversion rate = 18MHz, unless otherwise specified. VSP2101Y PARAMETER RESOLUTION DIGITAL INPUT Logic Family Logic Levels Logic Currents A/D Clock Duty Cycle Input Capacitance DIGITAL OUTPUT Logic Family Logic Levels ANALOG OUTPUT General Purpose D/A Converter Output Minimum Output Voltage Maximum Output Voltage DAC Settling TIme TRANSFER CHARACTERISTICS Differential Non-Linearity Integral Non-Linearity No Missing Codes Signal Settling Time Conversion Rate Data Latency Signal-to-Noise Ratio(1) CCD Offset Correction Range Black Clamp Level CDS Data Settling Time to ±0.1% for FS Change with RS = 40 Input Signal Level for FS Out Input Capacitance Input Time Constant INPUT CLAMP Clamp-On Resistance Clamp Level GAIN CONTROL CHARACTERISTICS Gain, max Gain, min Gain Control Linearity Gain Control Settling Time POWER SUPPLY Rated Voltage Quiescent Current Power Dissipation Power-Down Mode TEMPERATURE RANGE Specified Range Thermal Resistance, θJA 48-Lead LQFP NOTE: (1) SNR = 20log (full-scale voltage/rms noise). Ambient Control Data = 0 Control Data = 1023 32 CONDITIONS MIN TYP 10 CMOS Logic HI Logic LO Logic HI, VIN = +3V Logic LO, VIN = 0V 2.5 +0.4 10 10 50 5 CMOS Logic HI, CL = 10pF Logic LO, CL = 10pF 2.5 +0.4 V V V V µA µA % pF MAX UNITS Bits Control Data = 1023 Control Data = 0 0.3 2.4 1.0 ±0.5 2.0 Guaranteed V V µs LSB LSB 110 ns MHz Clocks dB mV LSB ns mV pF ps kΩ V dB dB dB µs +3.6 V mA mW mW °C °C/W Black to Full-Scale Change to 1/4 LSB into A/D 500kHz Grounded Input Cap, Maximum Gain 5.5 53 ±150 32 11 600 20 300 3.3 1.2 34 –2 ±1.0 10 +3.0 63 190 18 27 From Leading Edge of DATCK Minimum Gain DATCK LOW +2.7 –25 100 +85 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® VSP2101 2 ABSOLUTE MAXIMUM RATINGS Power Supply (+VS) ............................................................................. +6V Analog Input .............................................................. –0.3V to (+VS +0.3V) Logic Input ............................................................... –0.3V to (+VS +0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ...................................................... –40°C to +150°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 340 " SPECIFIED TEMPERATURE RANGE –25°C to +85°C " PACKAGE MARKING VSP2101Y " ORDERING NUMBER(2) VSP2101Y VSP2101Y/2K TRANSPORT MEDIA 50-Piece Tray Tape and Reel PRODUCT VSP2101Y " PACKAGE 48-Lead LQFP " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP2101Y/2K” will get a single 1000piece Tape and Reel. ® 3 VSP2101 PIN CONFIGURATION DACOUT RESET AVDD6 AVDD5 AVDD4 AVDD3 REFN AVSS6 AVSS5 REFP 48 DVSS1 B10 (LSB) B9 B8 B7 B6 B5 B4 B3 1 2 3 4 5 6 7 8 9 47 46 45 44 43 42 41 40 39 38 37 36 WRT 35 SCLK 34 SD 33 AVDD2 32 LCM 31 AVSS4 VSP2101Y 2.4V 30 TP2 29 TP1 28 AVSS2 27 CCD R 26 CCD D 25 AVSS1 24 B2 10 B1 (MSB) 11 DRVDD 12 13 14 15 16 17 18 19 20 21 22 23 CM DUMC PD PB DRVSS ADCK DVSS2 DVSS3 DVDD OB REFCK PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DESIGNATOR DVSS1 B10 (LSB) B9 B8 B7 B6 B5 B4 B3 B2 B1 (MSB) DRVDD DRVSS DVSS2 DVSS3 ADCK DVDD PD DESCRIPTION Digital Ground Bit 10, ADC Output, Least Significant Bit Bit 9, ADC Output Bit 8, ADC Output Bit 7, ADC Output Bit 6, ADC Output Bit 5, ADC Output Bit 4, ADC Output Bit 3, ADC Output Bit 2, ADC Output Bit 1, ADC Output, Most Significant Bit Digital Power Supply for Digital Outputs (B1-B10) Digital Ground for Digital Outputs (B1-B10) Digital Ground Digital Ground Clock for Digital Data Output Latch Digital Power Supply Power Down: LOW = Normal Operation HIGH = Reduced Power (digital output= 0000000000) Preblanking: LOW = ADC Output: –FS +32LSB HIGH = ADC Output: Normal Optical Black Clamp Pulse, Active LOW CDS Reference Sampling Pulse, Active LOW CDS Data Sampling Pulse, Active LOW Dummy Clamp, Active LOW PIN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 DESIGNATOR C AVSS1 CCD D CCD R AVSS2 TP1 TP2 AVSS4 LCM AVDD2 SD SCLK WRT 2.4V CM AVDD3 AVDD4 RESET DACOUT AVDD5 AVDD6 AVSS5 AVSS6 REFN REFP DESCRIPTION Capacitor for Optical Feedback Loop Analog Ground CCD Signal Input Capacitor for Dummy Feedback Loop Analog Ground Test Pin 1, Open Test Pin 2, Open Analog Ground Attenuator Common-Mode Bypass Analog Power Supply Serial Data Input for D/A Converters Clock for Serial Data Input Write Pulse for Serial Data Input, Rising Edge Trigger Attenuator Ladder Bypass ADC Common-Mode Voltage Analog Power Supply Analog Power Supply Resets DAC Registers, Active LOW D/A Converter (DAC1) Output Analog Power Supply Analog Power Supply Analog Ground Analog Ground ADC Negative Reference, Bypass to Ground ADC Positive Reference, Bypass to Ground 19 20 21 22 23 PB OB REFCK DATCK DUMC ® VSP2101 4 DATCK C SERIAL CONTROL DATA FORMAT FOR DAC0/DAC1 BIT NO. 1 2 DESIGNATOR A1 A0 DESCRIPTION Start Bit. Either HIGH or LOW will be acceptable. Address Bit. Selects internal DACs. LOW = DAC0, VGA control DAC HIGH = DAC1, general purpose DAC Digital Input Data for DAC, Bit 10 (MSB) Digital Input Data for DAC, Bit 9 Digital Input Data for DAC, Bit 8 Digital Input Data for DAC, Bit 7 Digital Input Data for DAC, Bit 6 Digital Input Data for DAC, Bit 5 Digital Input Data for DAC, Bit 4 Digital Input Data for DAC, Bit 3 Digital Input Data for DAC, Bit 2 Digital Input Data for DAC, Bit 1 (LSB) TIMING SPECIFICATIONS FOR SERIAL REGISTERS Timing Specifications = tMIN to tMAX with +3V power supply. SYMBOL tCKP tCKL tCKH tSD tHD tSW tW tWD tRS tRSD PARAMETER Serial Clock Period Serial Clock Pulse Width LOW Serial Clock Pulse Width HIGH Data Setup Time Data Hold Time Write Pulse Setup Time Write Pulse Width Data Valid Delay Time Register Reset Pulse Width Register Reset Delay Time MIN 100 50 50 50 25 100 50 50 50 50 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns 3 4 5 6 7 8 9 10 11 12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TIMING FOR SERIAL PORT WRITING tCKH SCLK tCKP Must be LOW before WRT goes HIGH tSD SD A1 A0 D9 tHD D8 D7 D6 D5 D4 D3 D2 D1 D0 tSW tW tCKL WRT tWD DATA Valid TIMING FOR REGISTER RESET tRS RESET tRSD REGISTER DATA All Zeros TIMING FOR PREBLANKING PB Mode 5.5 Clocks ADCK 5.5 Clocks DIGITAL OUTPUT t7 PB Mode t7 ® 5 VSP2101 TIMING DIAGRAMS 9.5MHz 0ns RESET 56 HI 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns 106 CCD OUT REFCK DATCK 26 45 80 96 132 151 26 ADCK OB DUMC 19 79 132 159 24 81 88 DATA VALID 127 167 OUTPUT DATA DATA VALID 14MHz 0ns RESET 39 HI 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns CCD OUT REFCK DATCK 21 37 54 69 21 ADCK OB DUMC –7 OUTPUT DATA 33 DATA VALID 28 56 91 161 69 168 208 58 65 136 176 DATA VALID ® VSP2101 6 TIMING DIAGRAMS (CONT) 18MHz 0ns RESET 27.7 HI 55.5 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns CCD OUT REFCK DATCK 18 32 46 60 18 ADCK OB DUMC 24 46 74 130 64 48 OUTPUT DATA DATA VALID 55 DATA VALID DATA VALID CDS/ADC TIMING DIAGRAM 27MHz Feedthrough Data Output Interval CDS Input (CCD Output) N t1 REFCK (Pin 21) DATCK (Pin 22) ADCK (Pin 16) DIGITAL OUTPUT (Pins 2-11) t4 t5 N-7 N-6 t7 N-5 t0 t3 t2 t6 N+1 N+2 SYMBOL t0 t1 t2 t3 t4, t5 t6 t7 PARAMETER REFCK Pulse Width REFCK Samling Delay DATCK Pulse Width DATCK Sampling Delay ADCK Pulse Width ADCK Delay Output Data Delay(1) MIN 11 1.5 11 1.5 18.5 0 7.1 TYP 14 2 14 2 27 13 8.3 MAX UNITS ns ns ns ns ns ns ns 26 9.5 NOTE: (1) CLOAD = 5pF. ® 7 VSP2101 TYPICAL HORIZONTAL INTERVAL TIMING CCD Video Dummy Pixel Optical Black Blanking Interval Video OB DUMC PB OUTPUT Video Black Level Video TYPICAL PERFORMANCE CURVES At TA = +25°C, all power supply voltages = +3.0V, and conversion rate = 18MHz, unless otherwise specified. VCA CHARACTERISTICS 40 35 Quiescent Current (mA) 100 QUIESCENT CURRENT vs POWER SUPPLY 30 25 80 Gain (dB) 20 15 10 5 0 –5 2.7V 3.0V 3.6V 3.3V 60 40 20 0 1023 974 926 877 828 779 731 682 633 585 536 487 438 390 341 292 244 195 146 97 49 0 2.7 3.0 Power Supply Voltage (V) 3.3 DAC0 Code (LSB) DAC1 ANALOG OUTPUT 3.0 2.5 Analog Output (V) 2.0 1.5 1.0 .5 1023 768 512 DAC1 Code (LSB) 256 0 ® VSP2101 8 THEORY OF OPERATION The VSP2101 is an integrated circuit that contains many of the key features associated with the processing of analog signals in a video camera or a digital-still camera. Figure 1 shows a simplified block diagram of the VSP2101. The output from the CCD array is first sent to a Correlated Double Sampler (CDS), then a voltage-controlled attenuator with a logarithmic control characteristic, and an output amplifier prior to being applied to the input of a 10-bit A/D converter. Two calibration cycles are employed to reduce the offset variation of the VSP2101. During the dummy pixel time, an input auto-zero circuit is activated that eliminates the offset of the correlated double sampler. During the optical black timing interval, another auto-zero circuit is employed to eliminate the offset associated with the output amplifier and the remaining offset from the CDS. CORRELATED DOUBLE SAMPLER (CDS) The CDS removes low frequency noise from the output of the image sensor. Refer to Figure 2 which shows a block diagram of the CDS. The output from the CCD array is sampled during the reference interval as well as during the data interval. Noise that is present at the input and is of a period greater than the pixel interval will be eliminated by subtraction. The VSP2101 employs a three track/hold correlated double sampler architecture. Track/Hold 2 is sampled during the reference interval by the REFCK signal. Track/Hold 3 is resampled at the same time that the data Track/Hold 1 is sampled by the DATCK signal. This is done to remove large transients from Track/Hold 2 that results from a portion of the reset transient being present during the acquisition time of this track and hold. The output of Track/Hold 2 is buffered by a voltage follower. Dummy Feedback Loop DUMC OB Black Level Auto-Zero Loop ADCK CCD Input CDS VCA Output Amplifier 10-Bit 27MHz A/D Digital Output Clamp REFCK DATCK Gain Control FIGURE 1. Simplified Block Diagram of VSP2101. CCD Input Data Sampling Channel Reference Sampling Channel T/H1 To VCA T/H3 T/H2 1V DUMC REFCK DATCK FIGURE 2. Block Diagram of Correlated Double Sampler. ® 9 VSP2101 DIFFERENCE AMPLIFIER The correlated double sampler function is completed when the output of the data and reference channel are sent to the difference amplifier where the signals are subtracted. In addition to providing the difference function, the difference amplifier amplifies the signal by a factor of 2 which helps to improve the overall signal-to-noise ratio. The difference amplifier also generates a differential signal to drive the voltage-controlled attenuator. INPUT CLAMP The output from the CCD array is capacitively coupled to the VSP2101. To prevent shifts in the DC level from taking place due to varying input duty cycles, the input capacitor is clamped during the dummy pixel interval by the REFCK signal and the DUMC signal. A P-channel transistor is used for this input clamp switch to allow a 2V negative change at the input that would bring the signal below ground by 1. Under typical conditions, the bias at the input to the VSP2101 is at 1V. DUMMY PIXEL AUTO-ZERO LOOP The output from the data and reference channel is processed by the previously mentioned difference amplifier. The differential output from the difference amplifier is sent to both the voltage-controlled logarithmic attenuator and to an error amplifier. The error amplifier amplifies and feeds a signal to the difference amplifier to drive the offset measured at the output of the difference amplifier to zero. A block diagram of this circuit is shown in Figure 3. This error amplifier serves the purpose of reducing the offset of the CDS to avoid a large offset from being amplified by the output amplifier. The effective time constant of this loop is given by: T = RC AD where R is 10kΩ, C is an external capacitor connected to pin 27 (CCD R), A is the gain of the error amplifier with a value of 50, and D is the duty cycle of the time that the dummy pixel auto-zero loop is in operation. The duty cycle (D) must be considered as the loop operates in a sampled mode. Operation of the dummy auto-zero loop is activated by the DUMC signal that happens once during each horizontal line interval. TIMING The REFCK and DATCK signals are used to operate the CDS as previously explained. These same two signals are also used by internal timing circuitry to create the necessary timing signals for the A/D. The output from the A/D is read out to external circuitry by the ADCK signal. DUMC is used to activate the dummy pixel auto-zero loop and OB is used to activate the black level auto-zero loop. The input digital timing signals REFCK, DATCK, DUMC and OB are capable of being driven from either 3V or 5V logic levels. VOLTAGE-CONTROLLED ATTENUATOR To maximize the dynamic range of the VSP2101, a voltagecontrolled attenuator is included with a control range from 0dB to –34dB. The gain control has a logarithmic relationship between the control voltage and the attenuation. The attenuator processes a differential signal from the difference amplifier to improve linearity and to reject both power supply and common-mode noise. The output from the attenuator is amplified by 28dB prior to being applied to the A/D. A typical gain control characteristic of the VSP2101 is shown in the typical performance curve, “VCA Characteristics”. BLACK LEVEL AUTO-ZERO LOOP The black level auto-zero loop amplifies the difference between the output of the output amplifier and a reference signal during the optical black timing interval. This difference signal is amplified and fed back into the output amplifier to correct the offset. In doing so, the output level of the entire CCD channel can be controlled to be approximately – FS + 32LSBs under zero input signal conditions. The black level auto-zero loop is activated by the OB timing signal. Figure 4 shows a block diagram of the black level auto-zero loop. The loop time constant is given by: T= C (GM) (D) CCDIN CDS To VCA Output Amplifier From VCA To ADS 32LSB Error Amplifier A CCD R C R GM C C Error Amplifier DUMCK OB FIGURE 3. Block Diagram of Dummy Pixel Loop. ® FIGURE 4. Black Level Auto-Zero Loop. 10 VSP2101 where C is the external filter capacitance applied to pin 24 (C), GM is .001Ω and D is the duty cycle of the time that the black level auto-zero loop is in operation. The duty cycle (D) must be considered as the loop operates in a sampled mode. Operation of the black level auto-zero loop is activated by the OB signal that happens once during each horizontal line interval. A/D CONVERTER The A/D converter utilizes a pipline architecture. The fully differential topology and digital error correction guarantee 10-bit resolution. The A/D converter circuitry includes a reference circuit that provides bias voltages for the entire system. SERIAL INTERFACE AND DACs The VSP2101 incorporates two identical 10-bit DACs (DAC0 and DAC1). DAC0 is for controlling the amount of attenuation of the log Voltage Controlled Attenuator (VCA) and DAC1 is for user-defineable options such as iris control. The input data for these DACs are set by the written data through the serial interface. The serial port has an 12-bit register which is controlled by four signals (SD, SCLK, WRT, RESET). SD is the serial data input, SCLK is the clock for the serial data, WRT pulse takes the serial register data into another internal parallel register at the rising edge, RESET resets all the registers’ data to zeros asynchronously when RESET = LOW. The serial register uses master-slave dual flip-flops and the master flip-flop receives the input data at the rising edge of SCLK and transmits this data into the slave at the falling edge of SCLK. Therefore, the clock SCLK must be normally LOW. When the DAC input data is all zeros, this corresponds to a maximum output voltage of 2.4V. In a similar manner, all ones correspond to a DAC output voltage of 0.3V. The VCA attenuation is at a minimum—which is the same as the channel gain being a maximum—when the DAC voltage is at 2.4V. The serial data format and the related signal timing are shown page 5. When the input serial data is longer than 12 bits, the last 12 bits become effective and the former bits are erased. When the registers are reset, the user should be careful that the channel gain setting becomes maximum and DAC1 output voltage goes to maximum. DECOUPLING AND GROUNDING CONSIDERATIONS The VSP2101 has several supply pins, one of which is dedicated to supply only the digital output driver (pin 12, DRVDD). The remaining supply pins are not, as is often the case, divided into analog and digital supply pins since they are internally connected on the chip. For this reason, it is recommended that the VSP2101 be treated as an analog component and be powered from the analog supply only. Digital supply lines often carry high levels of wide band noise which can couple back into the VSP2101 and limit performance. Figure 5 shows the recommended decoupling scheme for the VSP2101. In most cases, 0.1µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual pin. Therefore, they should be located as close as possible to the pins. In addition, one larger capacitor (1µF to 22µF) should be placed on the PC board in proximity of the VSP2101. OTHER RECOMMENDATIONS DRVDD is a power supply used exclusively for the digital output driver and should not be connected to AVDD and DVDD, even if the power supply voltage is the same. The voltage level difference between DRVDD, AVDD, and DVDD should be kept less than 0.3V. If your PC board has analog and digital ground, AVSS, DVSS, and DRVSS should be connected to analog ground. DEMONSTRATION BOARD A demonstration board, DEM-VSP2101, is available to assist in the inital evaluation of the circuit performance using the VSP2101. The schematic of the DEM-VSP2101 is shown in Figure 5. ® 11 VSP2101 1 2 3 4 5 CN1 8 6 4 2 10 ® C12 10µF 1 2 VCC C11 0.1µF TP2 ADCCK VCC C1 0.1µF 1 2 JP1 JP2 C13 10µF 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 7 5 3 1 C PB OB PD DVDD ADCK DVSS3 DVSS2 DUMC DATCK JP3 25 AVSS1 DRVDD 12 B1 (MSB) 11 B2 10 B3 B4 B5 REFCK DRVSS FIGURE 5. DEM-VSP2101Y Schematic. CN3 TP8 TP6 TP4 TP7 TP5 TP3 2.4V CM AVDD3 AVDD4 RESET DACOUT AVDD5 AVDD6 AVSS5 AVSS6 REFN REFP VSP2101 U2 1 OE1 A1 A2 A3 A4 A5 A6 Y2 Y3 Y4 Y5 Y1 OE2 VDD 20 19 18 17 16 15 14 1 3 5 7 9 2 C10 0.1µF 4 5 24 23 22 21 20 19 18 17 16 15 14 13 6 7 8 9 10 TP1 3 CN2 2 4 6 8 10 BNC CCD D C3 0.1µF 1 2 26 CCD D 27 CCD R 28 AVSS2 9 8 7 6 5 4 3 2 1 DVSS1 A7 A8 GND Y6 Y7 Y8 13 12 11 11 13 15 12 14 16 R1 50Ω C4 0.1µF 12 29 TP1 30 TP2 31 AVSS4 B6 B7 B8 B9 B10 (LSB) IDT74FCT541 C2 0.1µF 17 19 21 23 18 20 22 24 C5 0.1µF VSP2101Y 32 LCM 33 AVDD2 34 SD 35 SCLK 36 WRT U3 1 2 3 4 5 6 7 8 OE1 A1 A2 A3 A4 A5 A6 A7 VDD OE2 Y1 Y2 Y3 Y4 Y5 Y6 25 20 19 18 17 16 15 14 13 27 29 31 33 35 37 39 26 28 30 32 34 36 38 40 VCC TP9 TP10 TP11 37 38 39 40 41 42 43 44 45 46 47 48 C9 0.1µF C8 0.1µF C6 0.1µF C7 0.1µF ADCCK 9 10 A8 GND Y7 Y8 12 11 Header 20x2 TP12 VCC TP13 R8 1kΩ IDT74FCT541