VSP2262K

VSP2262 VSP 226 2 www.ti.com CCD SIGNAL PROCESSOR for DIGITAL CAMERAS FEATURES q CCD SIGNAL PROCESSING: Correlated Double Sampling (CDS) Programmable Black Level Clamping q PROGRAMMABLE GAIN AMPLIFIER (PGA): –6dB to +42dB Gain Ranging q 12-BIT DIGITAL DATA OUTPUT: Up to 20MHz Conversion Rate No Missing Codes q 79dB SIGNAL-TO-NOISE RATIO q PORTABLE OPERATION: Low Voltage: 2.7V to 3.6V Low Power: 83mW (typ) at 3.0V Stand-By Mode: 6mW DESCRIPTION The VSP2262 is a complete mixed-signal processing IC for digital cameras, providing signal conditioning and Analog-to-Digital (A/D) conversion for the output of a CCD array. The primary CCD channel provides Correlated Double Sampling (CDS) to extract video information from the pixels, –6dB to +42dB gain range with digital control for varying illumination conditions, and black level clamping for an accurate black level reference. Input signal clamping and offset correction of the input CDS are also performed. The stable gain control is linear in dB. Additionally, the black level is quickly recovered after gain change. The VSP2262Y is available in an LQFP-48 package and operates from a single +3V/+3.3V supply. CLPDM SHP SHD SLOAD SCLK SDATA RESET ADCCK DRVDD VCC Serial Interface Input Clamp Timing Control CCDIN Correlated Double Sampling (CDS) Programmable Gain Amplifier (PGA) –6dB to +42dB AnalogtoDigital Converter Output Latch 12-Bit Digital Output B[11:0] CCD Output Signal Preblanking Optical Black (OB) Level Clamping Reference Voltage Generator PBLK COB CLPOB BYPP2 BYP BYPM REFN CM REFP DRVGND GNDA Copyright © 2000, Texas Instruments Incorporated SBMS011 Printed in U.S.A. November, 2000 SPECIFICATIONS At TA = +25°C, VCC = +3.0V, DRVDD = +3.0V, Conversion Rate (fADCCK) = 20MHz, unless otherwise noted. VSP2262Y PARAMETER RESOLUTION CONVERSION RATE DIGITAL INPUT Logic Family Input Voltage Input Current DIGITAL OUTPUT Logic Family Logic Coding Output Voltage ADCCK Clock Duty Cycle Input Capacitance Maximum Input Voltage ANALOG INPUT (CCDIN) Input Signal Level for Full-Scale Out Input Capitance Input Limit TRANSFER CHARACTERISTICS Differential Non-Linearity (DNL) Integral Non-Linearity (INL) No Missing Codes Step Response Settling Time Overload Recovery Time Data Latency Signal-to-Noise Ratio(1) CCD Offset Correction Range CDS Reference Sample Settling Time Data Sample Settling Time INPUT CLAMP Clamp-On Resistance Clamp Level PROGRAMMABLE GAIN AMP (PGA) Gain-Control Resolution Maximum Gain High Gain Medium Gain Low Gain Minimum Gain Gain Control Error OPTICAL BLACK CLAMP LOOP Control DAC Resolution Optical Black Clamp Level Min Output Current for Control DAC Max Output Current for Control DAC Loop Time Constant Slew Rate CCOB REFERENCE Positive Reference Voltage Negative Reference Voltage POWER SUPPLY Supply Voltage Power Dissipation TEMPERATURE RANGE Operating Temperature Thermal Resistance VCC, DRVDD 2.7 Normal Operation Mode: No Load, DAC0 and DAC1 are Suspended Stand-By Mode: fADCCK = Not Apply –25 Within 1LSB, Driver Impedance = 50Ω Within 1LSB, Driver Impedance = 50Ω 400 1.5 10 42 34 20 0 –6 ±0.5 10 Programmable Range of Clamp Level OBCLP Level at CODE = 1000 COB Pin COB Pin CCOB = 0.1µF = 0.1µF, Output Current from Control DAC is Saturated 2 130 ±0.15 ±153 1530 1.75 1.25 3.0 86 6 3.6 60 PGA Gain = 0dB 20 TTL 1.7 1.0 ±20 ±20 CMOS Straight Binary Logic HIGH (VOH) IOH = –2mA Logic LOW (VOL) IOL = 2mA 2.4 0.4 50 5 –0.3 900 15 –0.3 PGA Gain = 0dB PGA Gain = 0dB Full-Scale Step Input Step Input from 1.8V to 0V Grounded Input Cap, PGA Gain = 0dB Grounded Input Cap, Gain = +24dB –180 ±0.5 ±1 Guaranteed 1 2 9 (Fixed) 79 55 200 11 11 3.3 5.3 V V % pF V mV pF V LSB LSB Pixel Pixels Clock Cycles dB dB mV ns ns Ω V Bits dB dB dB dB dB dB Bits LSB LSB µA µA µs V/s V V V mW mW °C °C/W CONDITIONS MIN TYP 12 MAX UNITS Bits MHz LOW to HIGH Threshold Voltage (VT+) HIGH to LOW Threshold Voltage (VT–) Logic HIGH (IIH) VIN = +3V Logic LOW (IIL) VIN = 0V V V µA µA Gain Gain Gain Gain Gain Code Code Code Code Code = = = = = 1111111111 1101001000 1000100000 0010000000 0000000000 +85 100 θJA LQFP-48 NOTE: (1) SNR = 20 log(full-scale voltage/rms noise). 2 VSP2262 SBMS011 ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage: VCC, DRVDD ........................................................... +4.0V Supply-Voltage Differences: Among VCC ......................................... ±0.1V Ground-Voltage Differences: Among GNDA .................................... ±0.1V Digital Input Voltage ............................................................ –0.3 to +5.3V Analog Input Voltage .................................................. –0.3 to VCC + 0.3V Input Current (Any Pins Except Supplies) ..................................... ±10mA Ambient Temperature Under Bias ..................................... –40 to +125°C Storage Temperature ......................................................... –55 to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (Soldering, 5s) ................................................ +260°C Package Temperature (IR Reflow, Peak, 10s) ............................. +235°C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER 340 SPECIFIED TEMPERATURE RANGE 0 to +85°C PACKAGE MARKING VSP2262Y ORDERING NUMBER(1) VSP2262Y VSP2262Y/2K TRANSPORT MEDIA 250-Piece Tray Tape and Reel PRODUCT VSP2262Y PACKAGE LQFP-48 " " " " " NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP2262Y/2K” will get a single 2000 piece Tape and Reel. DEMO BOARD ORDERING INFORMATION PRODUCT VSP2262Y ORDERING NUMBER DEM-VSP2262Y VSP2262 SBMS011 3 PIN CONFIGURATION Top View BYPP2 CCDIN GNDA GNDA GNDA GNDA BYPM COB BYP VCC VCC VCC LQFP 36 CM 37 REFP 38 REFN 39 VCC 40 GNDA 41 GNDA 42 NC 43 NC 44 RESET 45 SLOAD 46 SDATA 47 SCLK 48 1 B0 (LSB) 35 34 33 32 31 30 29 28 27 26 25 24 VCC 23 CLPDM 22 SHD 21 SHP 20 CLPOB 19 PBLK VSP2262 18 VCC 17 GNDA 16 ADCCK 15 GNDA 14 DRVGND 13 DRVDD 2 B1 3 B2 4 B3 5 B4 6 B5 7 B6 8 B7 9 B8 10 B9 11 B10 12 B11 (MSB) PIN DESCRIPTIONS PIN NAME TYPE(1) DESCRIPTION DO DO DO DO DO DO DO DO DO DO DO DO P P P DI P P DI Bit 0 (LSB), A/D Converter Output Bit 1, A/D Converter Output Bit 2, A/D Converter Output Bit 3, A/D Converter Output Bit 4, A/D Converter Output Bit 5, A/D Converter Output Bit 6, A/D Converter Output Bit 7, A/D Converter Output Bit 8, A/D Converter Output Bit 9, A/D Converter Output Bit 10, A/D Converter Output Bit 11 (MSB), A/D Converter Output Power Supply, Exclusively for Digital Output Digital Ground, Exclusively for Digital Output Analog Ground Clock for Digital Output Buffer Analog Ground Analog Power Supply Preblanking: HIGH = Normal Operation Mode LOW = Preblanking Mode: Digital Output “All Zero” Optical Black Clamp Pulse (Default = Active LOW) (5) CDS Reference Level Sampling Pulse (Default = Active LOW)(5) CDS Data Level Sampling Pulse (Default = Active LOW) (5) Dummy Pixel Clamp Pulse (Default = Active LOW)(5) PIN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME VCC GNDA GNDA VCC COB BYPP2 CCDIN BYP BYPM VCC VCC GNDA GNDA CM REFP REFN VCC GNDA GNDA NC NC RESET SLOAD SDATA SCLK TYPE(1) DESCRIPTION P P P P AO AO AI AO AO P P P P AO AO AO P P P – – DI DI DI DI Analog Power Supply Analog Ground Analog Ground Analog Power Supply Optical Black Clamp Loop Reference(2) Internal Reference P(3) CCD Signal Input Internal Reference C(4) Internal Reference N(3) Analog Power Supply Analog Power Supply Analog Ground Analog Ground A/D Converter Common-Mode Voltage(4) A/D Converter Positive Reference(4) A/D Converter Negative Reference(4) Analog Power Supply Analog Ground Analog Ground Should be Left OPEN Should be Left OPEN Asynchronous System Reset (Active LOW) Serial Data Latch Signal (Triggered at the Rising Edge) Serial Data Input Clock for Serial Data Shift (Triggered at the Rising Edge) 1 B0 (LSB) 2 B1 3 B2 4 B3 5 B4 6 B5 7 B6 8 B7 9 B8 10 B9 11 B10 12 B11 (MSB) 13 DRVDD 14 DRVGND 15 GNDA 16 ADCCK 17 GNDA 18 VCC 19 PBLK 20 21 22 23 CLPOB SHP SHD CLPDM DI DI DI DI NOTES: (1) Type designators: P = Power Supply and Ground; DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output. (2) Should be connected to ground with a bypass capacitor. We recommend the value of 0.1µF to 0.22 µF, however, it depends on the application environment. Refer to the “Optical Black Level Clamp Loop” section for more detail. (3) Should be connected to ground with a bypass capacitor. We recommend the value of 400pF to 9000pF, however, it depends on the application environment. Refer to the “Voltage Reference” section for more detail. (4) Should be connected to ground with a bypass capacitor (0.1µF). Refer to the “Voltage Reference” section for more detail. (5) Refer to “Serial Interface” section for more detail. 4 VSP2262 SBMS011 CDS TIMING SPECIFICATIONS CCD Output Signal N N+1 N+2 N+3 tWP tCKP SHP(1) tPD tDP tWD tS tCKP SHD(1) tS tINHIBIT tADC tADC tCKP ADCCK tHOLD tOD B[11:0] N – 11 N – 10 N–9 N–8 N–7 SYMBOL tCKP tADC tWP tWD tPD tDP tS tINHIBIT tHOLD tOD DL PARAMETER Clock Period ADCCK HIGH/LOW Pulse Width SHP Pulse Width SHD Pulse Width SHP Trailing Edge to SHD Leading Edge(1) SHD Trailing Edge to SHP Leading Edge(1) Sampling Delay Inhibited Clock Period Output Hold Time Output Delay Data Latency, Normal Operation Mode MIN 48 20 14 11 8 12 TYP MAX UNITS ns ns ns ns ns ns 5 20 7 38 9 (fixed) ns ns ns ns Clock Cycles NOTE: (1) The description and timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). The user can select the active polarity (Active LOW or Active HIGH) through the serial interface. Refer to the “Serial Interface” section for more detail. VSP2262 SBMS011 5 SERIAL INTERFACE TIMING SPECIFICATIONS SLOAD tXS tXH tCKL tCKH tCKP SCLK tDH tDS SDATA MSB LSB 2 Bytes SYMBOL tCKP tCKH tCKL tDS tDH tXS tXH PARAMETER Clock Period Clock HIGH Pulse Width Clcok LOW Pulse Width Data Setup Time Data Hold TIme SLOAD to SCLK Setup Time SCLK to SLOAD Hold Time MIN 100 40 40 30 30 30 30 TYP MAX UNITS ns ns ns ns ns ns ns NOTES: (1) Data shift operation should occur at the rising edge of SCLK while SLOAD is LOW. Two bytes of input data are loaded to the parallel latch in the VSP2260 at the rising edge of SLOAD. (2) When the input serial data is longer than two bytes (16 bits), the last two bytes become effective and the former bits are lost. 6 VSP2262 SBMS011 THEORY OF OPERATION INTRODUCTION The VSP2262 is a complete mixed-signal IC that contains all of the key features associated with the processing of the CCD imager output signal in a video camera, a digital still camera, security camera, or similar applications (see the simplified block diagram on page 1 for details). The VSP2262 includes a Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA), Analog-to-Digital Converter (ADC), input clamp, Optical Black (OB) level clamp loop, serial interface, timing control, reference voltage generator, and general-purpose 8-bit Digital-to-Analog Converters (DAC). We recommend an off-chip emitter follower buffer between the CCD output and the VSP2262 CCDIN input. The PGA gain control, clock polarity setting, and operation mode can be selected through the serial interface. All parameters are reset to the default value when the RESET pin goes LOW asynchronously from the clocks. CORRELATED DOUBLE SAMPLER (CDS) The output signal of a CCD imager is sampled twice during one pixel period: once at the reference interval and the other at the data interval. Subtracting these two samples from each other extracts the video information of the pixel as well as removes any noise that is common, or correlated, to both the intervals. Thus, the CDS is very important in reducing the reset noise and low-frequency noises that are present on the CCD output signal. Figure 1 shows the simplified block diagram of the CDS and input clamp. capacitance can be seen at the input pin. The analog input signal range at the CCDIN pin is 1Vp-p, and the appropriate common-mode voltage for the CDS is around 0.5V to 1.5V. The reference level is sampled during SHP active period, and the voltage level is held on sampling capacitor C1 at the trailing edge of SHP. The data level is sampled during SHD active period, and the voltage level is held on the sampling capacitor C2 at the trailing edge of SHD. The switchedcapacitor amplifier then performs the subtraction of these two levels. The user can select the active polarity of SHP/SHD (Active HIGH or Active LOW) through the serial interface (refer to the “Serial Interface” section for more detail). The default value of SHP/SHD is “Active LOW”. However, immediately after power ON, this value is Unknown. For this reason, the appropriate value must be set by using the serial interface, or reset to the default value by strobing the RESET pin. The descriptions and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). INPUT CLAMP OR DUMMY PIXEL CLAMP The buffered CCD output is capacitively coupled to the VSP2262. The purpose of the input clamp is to restore the DC component of the input signal that was lost with the AC coupling and establish the desired DC bias point for the CDS. A simplified block diagram of the input clamp is shown in Figure 1. The input level is clamped to the internal reference voltage, CM (1.5V), during the dummy pixel interval. More specifically, when both CLPDM and SHP are active, the dummy clamp function becomes active. If the dummy pixels and/or the CLPDM pulse are not available in your system, the CLPOB pulse can be used in place of CLPDM, as long as the clamping takes place during black pixels. In this case, both the CPLDM pin (active at same timing as CLPOB) and SHP become active during the optical black pixel interval, and then the dummy clamp function becomes active. The active polarity of CLPDM and SHP (Active HIGH or Active LOW) can be selected through the serial interface (refer to the “Serial Interface” section for more detail). The default value of CLPDM and SHP is “Active LOW”. However, immediately after power ON, this value is Unknown. For this reason, the appropriate value must be set by using the serial interface, or reset to the default value by strobing the RESET pin. The descriptions and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). HIGH PERFORMANCE ANALOG-TO-DIGITAL CONVERTER (ADC) The ADC utilizes a fully differential and pipelined architecture. This ADC is well suited for low-voltage operations, low power consumption requirements, and high-speed applications. It guarantees 12-bit resolution with no missing codes. The VSP2262 includes a reference voltage generator for the ADC. REFP (Positive Reference, pin 38), REFN VSP2262 SHP C1 10pF CIN CCD Output CLPDM SHD SHP CCDIN OPA C2 10pF CM (1.5V) FIGURE 1. Simplified Block Diagram of CDS and Input Clamp. The CDS is driven through an off-chip coupling capacitor (CIN). AC coupling is strongly recommended because the DC level of the CCD output signal is usually several volts too high for the CDS to work properly. A 0.1µF capacitor is recommended for CIN, depending on the application environment. Additionally, we recommend an off-chip emitter follower buffer that can drive more than 10pF, because the 10pF capacitor and a few pF of stray VSP2262 SBMS011 7 (Negative Reference, pin 39), and CM (Common-Mode Voltage, pin 37) should be bypassed to ground with a 0.1µF ceramic capacitor and should not be used elsewhere in the system, as they affect the stability of these reference levels, which causes ADC performance degradation. Note that these are analog output pins and, therefore, do not apply external voltage. PROGRAMMABLE GAIN AMPLIFIER (PGA) Figure 2 shows the characteristics of the PGA gain. The PGA provides a gain range of –6dB to +42dB, which is linear in dB. The gain is controlled by a digital code with 10-bit resolution, and can be set through the serial interface (refer to the “Serial Interface” section for more detail). The default value of the gain control code is 128 (PGA Gain = 0dB). However, immediately after power ON, this value is Unknown. For this reason, the appropriate value must be set by using the serial interface, or reset to the default value by strobing the RESET pin. equivalent to 1LSB of the DAC output current. When C is 0.1µF, time constant T is 40.7µs. Additionally, the slew rate SR is given the following equation: SR = IMAX/C Where C is the capacitor value connected to COB, IMAX is the maximum current (153µA) of the control DAC in the OB level clamp loop, and 153µA is equivalent to 1023LSB of the DAC output current. Generally, OB level clamping at high speed causes “Clamp Noise” (or “White Streak Noise”), however, the noise will decrease by increasing C. On the other hand, an increased C requires a much longer time to restore from Stand-by mode, or right after power ON. Therefore, we consider 0.1µF to 0.22µF a reasonable value for C. However, it depends on the application environment; we recommend making careful adjustments using trial-and-error. The “OB clamp level” (the pedestal level) is programmable through the serial interface (refer to the “Serial Interface” section for more detail). Table I shows the relationship between input code and the OB clamp level. INPUT CODE 0000 0001 0010 0011 0100 0101 0110 0111 1000 (Default) 1001 1010 1011 1100 1101 1110 1111 OB CLAMP LEVEL, LSBs OF 12 BITS 2LSB 18LSB 34LSB 50LSB 66LSB 82LSB 98LSB 114LSB 130LSB 146LSB 162LSB 178LSB 194LSB 210LSB 226LSB 242LSB 50 40 30 Gain (dB) 20 10 0 –10 0 100 200 300 400 500 600 700 800 900 1k 1023 Input Code for Gain Control (0 to 1023) FIGURE 2. The Characteristics of PGA Gain. OPTICAL BLACK (OB) LEVEL CLAMP LOOP To extract the video information correctly, the CCD signal must be referenced to a well-established OB level. The VSP2262 has an auto-calibration loop to establish the OB level using the optical black pixels output from the CCD imager. The input signal level of the OB pixels is identified as the real “OB level”, and the loop should be closed while CLPOB is active. During the effective pixel interval, the reference level of the CCD output signal is clamped to the OB level by the OB level clamp loop. To determine the loop time constant, an off-chip capacitor is required, and should be connected to COB (pin 28). Time constant T is given in the following equation: T = C/(16384 • IMIN) Where C is the capacitor value connected to COB, IMIN is the minimum current (0.15µA) of the control Digital-to-Analog Converter (DAC) in the OB level clamp loop, and 0.15µA is TABLE I. Programmable OB Clamp Level. The active polarity of CLPOB (Active HIGH or Active LOW) can be selected through the serial interface (refer to the “Serial Interface” section for more detail). The default value of CLPOB is “Active LOW”. However, immediately after power ON, this value is Unknown. For this reason, the appropriate value must be set by using the serial interface, or reset to the default value by strobing the RESET pin. The descriptions and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). PREBLANKING AND DATA LATENCY The VSP2262 has an input blanking, or preblanking, function. When PBLK goes LOW, all digital outputs will go to ZERO at the 11th rising edge of ADCCK. In this mode, the digital output data comes out on the rising edge of ADCCK with a delay of 11 clock cycles (data latency is 11). This is 8 VSP2262 SBMS011 different from the preblanking mode in which the digital output data comes out on the rising edge of ADCCK with a delay of nine clock cycles (data latency is nine). If the input voltage is higher than the supply rail by 0.3V or lower than the ground rail by 0.3V, the protection diodes will be turned on to prevent the input voltage from going any further. Such a high swing signal may cause device damage to the VSP2262 and should be avoided. STAND-BY MODE For the purpose of saving power, the VSP2262 can be set to Stand-by mode (or Power-Down mode) through the serial interface when the VSP2262 is not in use. Refer to the “Serial Interface” section for more detail. In this mode, all the function blocks are disabled and the digital outputs will go to all ZEROs, causing the current consumption to drop to 1mA. Since all the bypass capacitors will discharge during this mode, a substantial time (usually of the order of 200ms to 300ms) is required to power up from Stand-by mode. VOLTAGE REFERENCE All the reference voltages and bias currents needed in the VSP2262 are generated by its internal bandgap circuitry. The CDS and the ADC use mainly three reference voltages: REFP (Positive Reference, pin 38), REFN (Negative Reference, pin 39) and CM (Common-Mode Voltage, pin 37). REFP, REFN and CM should be heavily decoupled with appropriate capacitors (e.g., 0.1µF ceramic capacitor). Do not use these voltages elsewhere in the system as they affect the stability of the reference level, and cause ADC performance degradation. Note that these are analog output pins and do not apply external voltage. BYPP2 (pin 29), BYP (pin 31), and BYPM (pin 32) are also reference voltages to be used in the analog circuit. BYP should be connected to ground with a 0.1µF ceramic capacitor. Since the capacitor value for BYPP2 and BYPM affects the step response, we consider 400pF to 9000pF to be a reasonable value. However, as it depends on the application environment, we recommend making careful adjustments using trial-and-error. BYPP2, BYP and BYPM should all be heavily decoupled with appropriate capacitors, and not used elsewhere in the system. They affect the stability of the reference levels, and cause performance degradation. Note that these are analog output pins and do not apply external voltage. SERIAL INTERFACE The serial interface has a 2-byte shift register and various parallel registers to control all the digitally programmable features of the VSP2262. Writing to these registers is controlled by four signals (SLOAD, SCLK, SDATA, and RESET). To enable the shift register, SLOAD must be pulled LOW. SDATA is the serial data input and the SCLK is the shift clock. The data at SDATA is taken into the shift register at the rising edge of SCLK; the data length should be two bytes. After the 2-byte shift operation, the data in the shift register is transferred to the parallel latch at the rising edge of SLOAD. In addition to the parallel latch, there are several registers dedicated to the specific features of the device and are synchronized with ADCCK. It takes five or six clock cycles for the data in the parallel latch to be written to those registers. Therefore, to complete the data updates, it requires five or six clock cycles after parallel latching by the rising edge of SLOAD. See Table II for the serial interface data format. TEST is the flag for the test mode (Texas Instruments proprietary only), A0 to A2 is the address for the various registers, and D0 to D11 is the data (or operand) field. VSP2262 SBMS011 9 MSB REGISTERS Configuration PGA Gain OB Clamp Level Clock Polarity Reserved Reserved Reserved Reserved Reserved x = Don’t Care. TEST 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 x A1 0 0 1 1 0 0 1 1 x A0 0 1 0 1 0 1 0 1 x D11 0 0 0 0 x x x x x D10 0 0 0 0 x x x x x D9 0 G9 0 0 x x x x x D8 0 G8 0 0 x x x x x D7 0 G7 0 0 x x x x x D6 0 G6 0 0 x x x x x D5 0 G5 0 0 x x x x x D4 0 G4 0 0 x x x x x D3 0 G3 O3 0 x x x x x D2 0 G2 O2 P2 x x x x x D1 0 G1 O1 P1 x x x x x LSB D0 C0 G0 O0 P0 x x x x x TABLE II. Serial Interface Data Format. REGISTER DEFINITIONS C[0] Operation Mode, Normal/Stand-By Serial Interface and Registers are always active, independently from the operation mode. C0 = Operation Mode for the entire chip except the serial interface and registers. (C0 = 0 “Active”; C0 = 1 “Stand-by”) G[9:0] O[3:0] P[2:0] The Characteristics of PGA Gain (refer to Figure 2) Programmable OB Clamp Level (refer to Table I) Clock Polarity P0 = Polarity for CLPDM P1 = for CLPOB P2 = for SHP/SHD (P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”) (P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”) (P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”) Immediately after power ON, these values are Unknown. The appropriate value must be set by using the serial interface, or reset to the default value by strobing the RESET pin. Default values are: C[2:0] = 0 G[9:0] = 0010000000 O[3:0] = 1000 P[2:0] = 000 Normal Operation Mode PGA Gain = 0dB OB Clamp Level = 32LSB CLPDM, CLPOB, SHP/SHD are all “Active LOW” (1) NOTE: (1) The descriptions and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). 10 VSP2262 SBMS011 TIMINGS The CDS and the ADC are operated by SHP/SHD and their derivative timing clocks generated by the on-chip timing generator. The digital output data is synchronized with ADCCK. See the VSP2262 “CDS Timing Specifications” for the timing relationship among the CCD signal, SHP/SHD, ADCCK and the output data. CLPOB is used to activate the black level clamp loop during the OB pixel interval, and CLPDM is used to activate the input clamping during the dummy pixel interval. If the CLPDM pulse is not available in your system, the CLPOB pulse can be used in place of CLPDM as long as the clamping takes place during black pixels (refer to the “Input Clamp and Dummy Pixel Clamp” section for more detail). The clock polarities of SHP/SHD, CLPOB and CLPDM can be independently set through the serial interface (refer to the “Serial Interface” section for more detail). The descriptions and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). In order to keep a stable and accurate OB clamp level, we recommend CLPOB should not be activated during PBLK active period. Refer to the “Preblanking and Data Latency” section for more detail. In Stand-by mode, ADCCK, SHP, SHD, CLPOB and CLPDM are internally masked and pulled HIGH. POWER SUPPLY, GROUNDING AND DEVICE DECOUPLING RECOMMENDATIONS The VSP2262 incorporates analog circuitry and a very high-precision, high-speed ADC that are vulnerable to any extraneous noise from the rails or elsewhere. For this reason, it should be treated as an analog component and all supply pins except for DRVDD should be powered by the only analog supply of the system. This will ensure the most consistent results, since digital power lines often carry high levels of wideband noise that would otherwise be coupled into the device and degrade the achievable performance. Proper grounding, short lead length, and the use of ground planes are also very important for high-frequency designs. Multi-layer PC boards are recommended for the best performance, since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. It is highly recommended that analog and digital ground pins of the VSP2262 be joined together at the IC and be connected only to the analog ground of the system. The driver stage of the digital outputs (B[11:0]) is supplied through a dedicated supply pin (DRVDD) and it should be separated from the other supply pins completely, or at least with a ferrite bead. It is also recommended to keep the capacitive loading on the output data lines as low as possible (typically less than 15pF). Larger capacitive loads demand higher charging current surges that can feed back into the analog portion of the VSP2262 and affect the performance. If possible, external buffers or latches should be used, providing the added benefit of isolating the VSP2262 from any digital noise activities on the data lines. In addition, resistors in series with each data line may help minimize the surge current. Values in the range of 100Ω to 200Ω will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances as the output levels change from LOW to HIGH, or HIGH to LOW. Due to high operation speed, the converter also generates high-frequency current transients and noises that are fed back into the supply and reference lines. This requires the supply and reference pins to be sufficiently bypassed. In most cases, 0.1µF ceramic chip capacitors are adequate to decouple the reference pins. Supply pins should be decoupled to the ground plane with a parallel combination of tantalum (1µF to 22µF) and ceramic (0.1µF) capacitors. The effectiveness of the decoupling largely depends on the proximity to the individual pin. DRVDD should be decoupled to the proximity of DRVGND. Special attention must be paid to the bypassing of COB, BYPP2 and BYPM, since these capacitor values determine important analog performances of the device. VSP2262 SBMS011 11 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device VSP2262Y VSP2262Y/2K (1) Status (1) ACTIVE ACTIVE Package Type LQFP LQFP Package Drawing PT PT Pins Package Eco Plan (2) Qty 48 48 250 2000 TBD TBD Lead/Ball Finish CU SNPB CU SNPB MSL Peak Temp (3) Level-1-235C-UNLIM Level-1-235C-UNLIM The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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