VSP3010

® VSP 301 0 VSP3010 For most current data sheet and other product information, visit www.burr-brown.com 12-Bit, 12MHz CCD/CIS SIGNAL PROCESSOR TM FEATURES q 12-BIT, 12MHz A/D CONVERTER q GUARANTEED NO MISSING CODES q 3-CHANNEL, 4MHz COLOR SCAN MODE: Correlated Double Samplers 8-Bit Offset Adjustment DACs 0dB to +13dB PGAs q q q q q A/D INPUT MONITOR INTERNAL VOLTAGE REFERENCE SINGLE +5V SUPPLY 3V OR 5V DIGITAL OUTPUT LOW POWER: 500mW typ (CCD Mode) DESCRIPTION The VSP3010 is a complete, three-channel image signal processor for Charge Coupled Device (CCD) or Contact Image Sensor (CIS) systems. Each channel contains sensor signal sampling, Black Level adjustment and a programmable gain amplifier. The three inputs are multiplexed into a high speed, 12-bit analog-to-digital converter. Input circuitry can be configured, by digital command, for CCD or CIS sensors. A Black Clamp and Correlated Double Samplers (CDS) are provided for CCD sensors. For CIS devices, the VSP3010 provides a single-ended sampler and a reference input. The VSP3010 is available in a 48-lead LQFP package and operates from 0° C to +85° C with a single +5V supply. APPLICATIONS q CCD AND CIS COLOR SCANNERS q FAX AND MULTI-FUNCTION MACHINES q INDUSTRIAL /MEDICAL IMAGING SYSTEMS CLP CK1 CK2 STRT ADCCK TP0 VREF Bandgap Reference Clamp RINP CM REFT REFB Timing CDS PGA M1 M2 M3 RINN 8 Clamp GINP 8-Bit DAC 5 VDRV CDS GINN PGA MUX 12-Bit A/D 12 B0-B11 (D0-D7, A0-A2) 8 Clamp BINP 8-Bit DAC 5 OE CDS BINN PGA Gain Adjust Register R G 5 B 5 Configuration Register 3 Offset Register R G B 8 8-Bit DAC 8 Register Port 8 P/S WRT RD SCLK SD 8 VSP3010 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1999 Burr-Brown Corporation PDS-1542A Printed in U.S.A. June, 1999 SPECIFICATIONS At TA = full specified temperature range, VDDA = +5V, VDDD = +5V, fADCCK = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, and PGA gain = 1, unless otherwise specified. VSP3010Y PARAMETER RESOLUTION CONVERSION CHARACTERISTICS 3-Channel CCD Mode 3-Channel CIS Mode ANALOG INPUTS Full-Scale Input Range Input Capacitance External Reference Voltage Range Reference Input Resistance Input Limits DYNAMIC CHARACTERISTICS Integral Non-Linearity (INL) Differential Non-Linearity (DNL) No Missing Codes Input-Referred Noise PSRR DIGITAL INPUTS Logic Family Convert Command High Level Input Current (VIN = VDDD) Low Level Input Current (VIN = 0V) Positive-Going Threshold Voltage Negative-Going Threshold Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding VDRV Supply Range Output Voltage, VDRV = +5V Low Level High Level Low Level High Level Output Voltage, VDRV = +3 Low Level High Level 3-State Enable Time 3-State Enable Time Output Capacitance Data Latency Data Output Delay DC ACCURACY Zero Error Gain Error POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation Thermal Resistance, θJA SPECIFIED TEMPERATURE RANGE 0 Operating 3-Channel Mode 1-Channel Mode 3-Channel Mode 1-Channel Mode 4.7 VDDA = +5V ± 0.25V 12 12 0.5 10 0.25 800 GNDA – 0.3 ±1 0.3 12 0.3 0.04 CMOS Rising Edge of ADCCK 20 20 3.80 2.05 µA µA V V pF VDDA + 0.3 ±2 0.75 1.75 3.5 CONDITIONS MIN TYP 12 MAX UNITS Bits MHz MHz Vp-p pF V Ω V LSB LSB Bits LSBs rms % FSR Start Conversion 3.00 1.25 3.40 1.65 5 CMOS Straight Binary +2.7 IOL = 50µA I OH = 50µA IOL = 1.6mA I OH = 0.5mA IOL = 50µA I OH = 50µA OE = LOW OE = HIGH +5.3 +0.1 V V V V V V V ns ns pF Clock Cycles ns % FS % FS +4.6 +0.4 +2.4 +0.1 +2.5 20 2 5 6 40 10 CL = 15pF 0.8 1.5 5 100 82 500 410 100 12 5.3 108 90 540 450 +85 V mA mA mW mW °C/W °C ® VSP3010 2 ABSOLUTE MAXIMUM RATINGS Supply Voltage, (VDDA, VDDD,VDRV) ...................................................... +6V Analog Input ....................................................... (–0.3V) to (+VDDA + 0.3V) Logic Input ......................................................... (–0.3V) to (+VDDD + 0.3V) Operating Temperature ........................................................ 0°C to +85°C Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 340 SPECIFIED TEMPERATURE RANGE 0°C to +85°C PACKAGE MARKING VSP3010Y ORDERING NUMBER(2) VSP3010Y VSP3010Y/2K TRANSPORT MEDIA 250-Piece Tray Tape and Reel PRODUCT VSP3010Y PACKAGE LQFP-48 " " " " " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP3010Y/2K” will get a single 2000piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 VSP3010 PIN CONFIGURATION GNDD GNDA GNDA REFB REFT VDDD 38 VDDA VDDA 48 CLP GNDA RINP RINN GNDA GINP GINN GNDA BINP 1 2 3 4 5 6 7 8 9 47 46 45 44 43 42 41 40 39 37 36 B11 (MSB) 35 B10 (A2) 34 B9 (A1) 33 B8 (A0) 32 B7 (D7) 31 B6 (D6) VSP3010Y VDRV 30 B5 (D5) 29 B4 (D4) 28 B3 (D3) 27 B2 (D2) 26 B1 (D1) 25 B0 (D0, LSB) 24 VREF BINN 10 GNDA 11 VDDA 12 13 14 15 16 17 18 19 20 21 22 23 TP0 CM GNDD WRT ADCCK SCLK STRT VDDD P/S RD CK1 CK2 SD PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESIGNATOR CLP GNDA RINP RINN GNDA GINP GINN GNDA BINP BINN GNDA VDDA STRT ADCCK CK1 CK2 GNDD RD WRT P/S SD SCLK VDDD OE TYPE DI P AI AI P AI AI P AI AI P P DI DI DI DI P DI DI DI DI DI P DI DESCRIPTION Clamp Enable Analog Ground Red-Channel Analog Input Red-Channel Reference Input Analog Ground Green-Channel Analog Input Green-Channel Reference Input Analog Ground Blue-Channel Analog Input Blue-Channel Reference Input Analog Ground Analog Power Supply, +5V Start Line Scanning A/D Converter Clock Input Sample Reference Clock Sample Data Clock Digital Ground Read Signal for Registers Write Signal for Registers Parallel/Serial Port Select; HIGH = Parallel, LOW = Serial Serial Data Input Serial Data Clock Digital Power Supply, +5V A/D Converter Output Enable PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 DESIGNATOR B0 (D0) LSB B1 (D1) B2 (D2) B3 (D3) B4 (D4) B5 (D5) B6 (D6) B7 (D7) B8 (A0) B9 (A1) B10 (A2) B11 MSB VDRV VDDD GNDD TP0 GNDA VDDA VREF GNDA REFB CM REFT VDDA TYPE DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DO P P P AO P P AIO P AO AO AO P DESCRIPTION A/D Output (Bit 0) and Register Data Port (Bit 0) A/D Output (Bit 1) and Register Data Port (Bit 1) A/D Output (Bit 2) and Register Data Port (Bit 2) A/D Output (Bit 3) and Register Data Port (Bit 3) A/D Output (Bit 4) and Register Data Port (Bit 4) A/D Output (Bit 5) and Register Data Port (Bit 5) A/D Output (Bit 6) and Register Data Port (Bit 6) A/D Output (Bit 7) and Register Data Port (Bit 7) A/D Output (Bit 8) and Register Address (Bit 0) A/D Output (Bit 9) and Register Address (Bit 1) A/D Output (Bit 10) and Register Address (Bit 2) A/D Output (Bit 11) Output Driver Voltage Supply Digital Power Supply, +5V Digital Ground A/D Converter Input Monitor Pin Analog Ground Analog Power Supply, +5V Reference Input/Output Analog Ground Bottom Reference Common-Mode Voltage Top Reference Analog Power Supply, +5V ® VSP3010 4 OE TIMING DIAGRAMS Timing specifications = tMIN to tMAX with +5V power supply. Timing for 3-Channel CCD/CIS Mode 3-Channel CCD Mode CCD tS STRT tST CK1 tSET CK2 tCCK ADCCK R G tCKP tCCK B tADCCK2 tCNV R1 G1 B1 tCK12A tCK2A tCK21A tCK1AP tCK1A R1, G1, B1 tS 3-Channel CIS Mode CIS R1, G1, B1 tS STRT tST tSET CK1 tADCCK1 B tCKP tCNV R1 G1 B1 tCK1A tCK1AP tCCK ADCCK R G tCCK SYMBOL tCK1AP tCK1A tCK2A tCCK tCKP tS tCK12A tCK21A tSET tADCCK2 tADCCK1 tCNV tST PARAMETER 3-Channel Conversion Rate CK1 Pulse Width CK2 Pulse Width ADCCK Pulse Width ADCCK Period Sampling Delay CK1 Falling Edge to CK2 Rising Edge CK2 Falling Edge to CK1 Rising Edge ADCCK Falling Edge to CK1 Rising Edge ADCCK Falling Edge to CK2 Falling Edge ADCCK Falling Edge to CK1 Falling Edge Conversion Delay Start Conversion Time MIN 200 15 15 35 83 10 15 50 10 20 20 22 20 TYP 250 70 70 42 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns 100 ® 5 VSP3010 TIMING DIAGRAMS (cont.) Timing specifications = tMIN to tMAX with +5V power supply. Timing for 1-Channel CCD/CIS Mode 1-Channel CCD Mode CCD Output Pixel 1 tS STRT tCK1BP CK1 tCK12B CK2 tCK1SET ADCCK tCCK tCKP tCCK tCK1ADC tADCCK2 tTR Pixel 1 tCK2B tCK21B tCK1B tS 1-Channel CIS Mode CIS Pixel 1 tS STRT tCK1BP CK1 tCCK ADCCK tCCK tCKP tSET tCNV Pixel 1 tCK1B SYMBOL tCK1BP tCK1B tCK2B tCCK tCKP tS t CK12B t CK21B tCK1SET tCK1ADC tADDCK2 tCNV tTR tSET PARAMETER 1-Channel Conversion Rate CK1 Pulse Width CK2 Pulse Width ADCCK Pulse Width ADCCK Period Sampling Delay CK1 Falling Edge to CK2 Rising Edge CK2 Falling Edge to CK1 Rising Edge ADCCK Rising Edge to CK1 Rising Edge CK1 Rising Edge to ADCCK Falling Edge ADDCK Falling Edge to CK2 Falling Edge Conversion Delay Transmission Time ADCCK Falling Edge to CK1 Rising Edge MIN 66 15 15 35 83 10 10 30 10 10 20 22 5 10 TYP 83 20 20 42 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® VSP3010 6 TIMING DIAGRAMS (cont.) Timing for Parallel Port Writing tPR P/S A2-A0 Stable tRW D7-D0 Stable tDA WRT tW Register Valid D7-D0 RD tRD Valid tRH A2-A0 tRW P/S Register tDA Stable Valid Timing for Reading tPR SYMBOL tPR tW tRW tDA PARAMETER Parallel Ready Time WRT Pulse Width Address Setup Time Data Setup Time MIN 20 30 20 30 TYP 50 50 50 MAX UNITS ns ns ns ns SYMBOL tRW tDA tRD tRH tPR PARAMETER Address Setup Time Data Setup Time Readout Delay Readout Hold Time Parallel Ready Time MIN 20 30 TYP 50 50 MAX UNITS ns ns ns ns ns 20 1 20 Timing for Serial Port Writing P/S tSS SCLK(1) tSD SD A2 A1 A0 D7 tSCKP D6 D5 D4 D3 D2 D1 D0 tSW tW WRT tWD Data tSCK tSCK SYMBOL tW tWD tSD tSCK tSCKP tSS tSW PARAMETER WRT Pulse Width Data Valid Time Data Ready Time Serial Clock Pulse Width Serial Clock Period Serial Ready Time WRT Pulse Setup Time MIN 30 15 30 60 100 50 TYP 50 MAX 30 UNITS ns ns ns ns ns ns ns 50 50 100 200 NOTE: SCLK must be LOW before WRT goes HIGH. ® 7 VSP3010 TIMING DIAGRAMS (Cont) DOUT Timing Diagram—3-Channel CCD Mode Pixel (n) CCD Output Pixel (n + 1) Pixel (n + 2) STRT tST CK1 CK2 tCNV ADCCK tCNV tCNV tCNV CDS Output R(1) R(1) (n) (n + 1) (n + 2) MUX A/D Input R G B R R (n) G G (n) B B (n) R G B R G B R G B R (n + 1) G (n + 1) B (n + 1) R (n + 2) G (n + 2) B (n + 2) A/D Output R(1) R G B R (n) G (n) B (n) R (n + 1) G (n +1) NOTE: (1) Depends on the D4 and D5 bits of the Configuration Register and sets to “R” right after the power supply goes ON. SYMBOL t CNV tST PARAMETER Conversion Delay Start Conversion Time MIN 22 20 TYP 100 MAX UNITS ns ns Timing for A/D Output tOEP P/S tOES tOEW OE tOER DOUT Valid tACKD ADCCK t3E SYMBOL tOES tOEW tOER t3E tACKD tOEP PARAMETER ADC Output Enable Setup Time OE Pulse Width Output Enable Time 3-State Enable Time Data Output Delay Parallel Port Setup Time MIN 20 100 TYP MAX UNITS ns ns 20 2 10 40 10 12 ns ns ns ns ® VSP3010 8 TYPICAL PERFORMANCE CURVES At TA = +25°C, VDDA = +5V, VDDD = +5V, fADCCK = 6MHz, fCK1 = 2MHz, and fCK2 = 2MHz, unless otherwise specified. PGA TRANSFER FUNCTION Sample Quantity, N = 100 5.0 4.5 Power Dissipation (mW) POWER DISSIPATION vs POWER SUPPLY (3-Channel Mode) 650 4.0 3.5 Gain (V/V) 550 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 PGA Gain Setting (Setting Code) 450 350 250 150 4.70 4.80 4.90 5.00 5.10 5.20 5.30 Power Supply Voltage (V) POWER DISSIPATION vs POWER SUPPLY (1-Channel Mode) 500 Power Dissipation (mW) 400 300 200 100 0 4.70 4.80 4.90 5.00 5.10 5.20 5.30 Power Supply Voltage (V) ® 9 VSP3010 THEORY OF OPERATION The VSP3010 can be operated in one of the following four modes: 3-Channel 3-Channel 1-Channel 1-Channel CCD Mode CIS Mode CCD Mode CIS Mode DAC (+50mV to –150mV). A 3-to-1 analog MUX follows the CIS signal processing circuits and feeds a high performance 12-bit A/D converter. The analog MUX can be programmed to cycle between red, green, and blue or blue, green, and red. When the STRT signal is HIGH, the conversion is initiated on the rising edge of ADCCK. The STRT signal indicates the first sample for a scan line. When STRT goes LOW, the analog MUX is switched to the first sample of the sequence. As specified in the “3-Channel CIS Mode” timing diagram, the falling edge of CK1 must be in the LOW period of ADCCK. If the falling edge of CK1 is in the HIGH period of ADCCK (in the timing diagram, ADCCK for sampling B channel), the VSP3010 will not function properly. 1-CHANNEL CCD MODE In this mode, the VSP3010 processes only one CCD signal. The CCD signal is AC-coupled to RINP, GINP, or BINP (as selected by the data in the Configuration Register). RINN, GINN, BINN are not used in this mode and should be grounded. The CLP signal enables internal biasing circuitry to clamp this input to a proper voltage so that internal CDS circuitry can work properly. The VSP3010 input may be applied as a DC-coupled input, which needs to be levelshifted to a proper DC level. The CDS takes two samples of the incoming CCD signal. The CCD reference value is taken on the falling edge of CK1 and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDS and the result is the CDS’ output. In this mode, only one of the three channels is enabled. Each CDS consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog MUX is inserted between the CDSs and a high performance 12-bit A/D converter. The analog MUX is not cycling between channels in this mode. Instead, the analog MUX is connected to a specific channel, depending on the data in the Configuration Register. As specified in the “1-Channel CCD Mode” timing diagram, the rising edge of CK1 must be in the HIGH period of ADCCK and the falling edge of the CK2 must be in the LOW period of ADCCK. Otherwise, the VSP3010 will not function properly. 1-CHANNEL CIS MODE In this mode, the VSP3010 is operated as a 1-channel sampler and digitizer. Unlike the CCD mode, VSP3010 takes only one sample on the falling edge of CK1. Since only one sample is taken, CK2 is grounded in this operation. The input signal is DC-coupled in most cases. Here, the VSP3010 inputs are differential. For example, for the red channel, RINP is the CIS signal input, and RINN is the CIS reference signal. The same applies to the green channel (GINP and GINN) and blue channel (BINP and BINN). 3-CHANNEL CCD MODE In this mode, the VSP3010 can simultaneously process three output CCD signals. These signals are AC-coupled to the RINP, GINP, and BINP inputs. RINN, GINN, BINN are not used in this mode and should be grounded. The CLP signal enables internal biasing circuitry to clamp these inputs to a proper voltage, enabling internal CDS circuitry to operate properly. VSP3010 inputs may be applied as DC-coupled inputs, which need to be level-shifted to a proper DC level. The correlated double samplers take two samples of the incoming CCD signals; the CCD reference levels are taken on the falling edge of CK1 and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDSs and the result is the CDS’ output. Three channels are used to process three inputs simultaneously. Each consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset digital-to-analog converter (+50mV to –150mV). A 3-to-1 analog MUX follows the CDS channels and feeds a high performance 12-bit A/D converter. The analog MUX can be programmed to cycle between red, green, and blue or blue, green, and red. When the STRT signal is HIGH, the conversion is initiated on the rising edge of ADCCK. The STRT signal indicates the first samples for a scan line. When STRT goes LOW, the analog MUX is switched to the first sample of the sequence. As specified in the “3-Channel CCD Mode” timing diagram, the falling edge of CK2 must be in the LOW period of ADCCK. If the falling edge of CK2 is in the HIGH period of ADCCK (in the timing diagram, ADCCK for sampling B channel), the VSP3010 will not function properly. 3-CHANNEL CIS MODE In this mode, the VSP3010 is operated as 3-channel samplers and a digitizer. Unlike the CCD mode, VSP3010 takes only one sample on the falling edge of CK1 for each input. Since only one sample is taken, CK2 is grounded in this operation. The input signal is DC-coupled in most cases. For example, for the red channel, RINP is the CIS signal input, and RINN is the CIS reference signal. The same applies to the green channel (GINP and GINN) and blue channel (BINP and BINN). In this mode, three CDSs become CIS signal processing circuits (acting like a track-and-hold) to process three inputs simultaneously. Each CIS signal processing circuit consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset ® VSP3010 10 In this mode, the CDS becomes a CIS signal processing circuit (acting like a track-and-hold). Each CIS signal processing circuit consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog MUX follows the CIS signal processing circuits and feeds a high performance 12-bit A/D converter. The analog MUX is not cycling between channels in this mode. Instead, the analog MUX is connected to a specific channel, depending on the data in the Configuration Register. As specified in the “1-Channel CIS Mode” timing diagram, the active period of CK1 (tCK1B) must be in the LOW period of ADCCK. If it is in the HIGH period of ADCCK, the VSP3010 will not function properly. ANALOG PGA There is one analog PGA on each channel. Each analog PGA is controlled by a 5-bit PGA gain register. The analog PGA gain varies from 1 to 4.44 (0dB to +13dB). The transfer function of the PGA is: Gain = 4/(4 – 0.1 • X) where X is the integer representation of the 5-bit PGA gain register. Figure 1 shows the PGA transfer function plot. CHOOSING AC INPUT COUPLING CAPACITORS The purpose of the input coupling capacitor is to isolate the DC output of the CCD array from affecting the VSP3010. The internal clamping circuitry restores the necessary DC component to the CCD output signal. The internal clamp voltage, VCLAMP, is derived from the reference. VCLAMP depends on the value of VREF; if VREF is set to 1V, VCLAMP is 2.5V and if VREF is set to 1.5V, VCLAMP is 3V. There are many factors that determine the size of the input coupling capacitors including CCD signal swing, voltage droop across the input capacitor since the last clamp interval, leakage current of the VSP3010 input circuitry, and the time period of CK1. Figure 2 shows a simplified equivalent circuit of the VSP3010 inputs. In this equivalent circuit, the input coupling capacitor, CIN, and the sampling capacitor, C1, are constructed as a capacitor divider (during CK1). For AC analysis, op amp inputs are grounded. Therefore, the sampling voltage, VS (during CK1) is: VS = (CIN/CIN + C1)) • VIN From this equation, we see that a larger value of CIN makes VS closer to VIN. In other words, the input signal VIN will be attenuated less if CIN is large. However, there is a disadvantage to using a large value of CIN: the larger the CIN, the more dummy or optical black pixels must be used to restore the DC component of the input signal. PGA TRANSFER FUNCTION 4.5 4.0 3.5 CK1 C1 4pF CIN VIN VS OP AMP C2 4pF CK2 0 5 10 15 20 25 31 Gain 3.0 2.5 2.0 1.5 1.0 PGA Gain Setting CLP CK1 PGA TRANSFER FUNCTION 14 12 10 VCLAMP FIGURE 2. Equivalent Circuit of VSP3010 Inputs. CHOOSING CMAX AND CMIN As mentioned previously, a large CIN is preferable if there is enough time for the CLP signal to charge up CIN. Typically, 0.01µF to 0.1µF of CIN can be used for most cases. In order to optimize CIN, the following two equations can be used to calculate CMAX and CMIN: 0 5 10 15 20 25 31 Gain (dB) 8 6 4 2 0 PGA Gain Setting CMAX = ( tCK1 • N)/[RSW • ln (VD/VERROR)] where, tCK1 is the time when both CK1 and CLP are HIGH and N is the number of black pixels, RSW is the total switch ® FIGURE 1. PGA Transfer Function Plot. 11 VSP3010 resistance, VD is the droop across CIN and VERROR is the difference between VS and VCLAMP. The nominal value of RSW is 4kΩ plus the driver’s impedance. 0.1V should be tolerable for VERROR and still keep the VSP3010 working properly. CMIN = ( I/VERROR) • t where, I is 10nA, the typical leakage current of the VSP3010 input circuitry and t is the time between clamp pulses. PROGRAMMING THE VSP3010 The VSP3010 consists of three CCD or CIS channels and a 12-bit A/D converter. Each channel (red, green, and blue) has its own 8-bit offset and 5-bit gain adjustable registers to be programmed by the user. There is also a 7-bit Configuration Register on-chip to program the different operation modes. These registers are as follows: ADDRESS A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 REGISTER Configuration Register (7-Bit) Red Channel Offset Register (8-Bit) Green Channel Offset Register (8-Bit) Blue Channel Offset Register (8-Bit) Red Channel Gain Register (5-Bit) Green Channel Gain Register (5-Bit) Blue Channel Gain Reigster (5-Bit) Reserved For Reading/Writing to the Configuration Register, the address will be: A2 = ‘0’, A1 = ‘0’, and A0 = ‘0’ Example: A 3-channel CCD with internal reference VREF = 1V (2V full-scale input), the mode will be: = > D0 = ‘0’, D1 = ‘0’and D3 = ‘0’ For this example, VREF will be 1V. Bypass VREF with 10µF and 0.1µF capacitors when internal reference mode is used. Example: A 1-channel CIS mode (red channel) with external 1.2V reference: = > D0 = ‘1’, D1 = X, D2 = ‘1’, D4 = ‘0’ and D5 = ‘0’ For this example, VREF will be an input pin, applied with 1.2V. This input will set the full-scale input of the VSP3010 at 2.4V. Offset Registers Offset registers control the analog offset input to the channel prior to the PGA. There is an 8-bit Offset Register on each channel. The offset range varies from –150mV to +50mV. The Offset Register uses a Straight Binary code. All ‘0’s correspond to –150mV and all ‘1’s correspond to +50mV of the offset adjustment. PGA Gain Registers The PGA Gain Registers control the analog gain to the channels prior to the A/D converter. There is a 5-bit PGA Gain Register on each channel. The gain range varies from 1 to 4.44 (0dB to +13dB). The PGA Gain Register is a Straight Binary code. All ‘0’s correspond to analog gain of 0dB and all ‘1’s correspond to the analog gain of 13dB. These Registers can be accessed by either the parallel or serial port. In the parallel mode, the address and data port are combined with the ADC data output pins. The data bus is assigned as D0 to D7 (pin 25 to pin 32) and the address bus is A0 to A2 (pin 33 to pin 35). In the serial mode, serial data (SD), serial clock (SCLK), and write signal (WRT pin for both parallel and serial writing) are assigned. The following table shows how to access these modes. OE 0 0 1 1 P/S 0 1 0 1 MODE A/D Data Output Enabled, Serial Mode Enabled Prohibit Mode A/D Data Output Disabled, Serial Mode Enabled A/D Data Output Disabled, Parallel Mode Enabled OFFSET AND GAIN CALIBRATION SEQUENCE DIGITAL OUTPUTS The digital outputs of the VSP3010 are designed to be compatible with both high-speed TTL and CMOS logic families. The driver stage of the digital outputs is supplied through a separate supply pin, VDRV, which is not connected to the analog supply pins. By adjusting the voltage on VDRV, the digital output levels will vary respectively. Thus, it is possible to operate the VSP3010 on a +5V analog supply while interfacing the digital outputs to 3V logic. It is recommended to keep the capacitive loading on the data lines as low as possible (typically less than 15pF). Larger capacitive loads demanding higher charging current surges can feed back to the analog portion of the VSP3010 and influence the performance. If necessary, external buffers or latches may be used which provide the added benefit of isolating the VSP3010 from any digital noise activities on 12 Configuration Register The Configuration Register is designed as follows: BIT D0 D1 D2 D3 LOGIC ‘0’ CCD Mode VREF = 1V Internal Reference 3-Channel, D4 and D5 Disabled LOGIC ‘1’ CIS Mode VREF = 1.5V External Reference 1-Channel, D4 and D5 Enabled D4 D5 0 0 Red Channel 0 1 Green Channel 1 0 Blue Channel 1 1 Reserved B > G > R MUX Sequence Reserved D6 D7 R > G > B MUX Sequence Reserved ® VSP3010 the bus coupling back high frequency noise. In addition, resistors in series with each data line may help minimize the surge current. Their use depends on the capacitive loading seen by the converter. As the output levels change from low to high and high to low, values in the range of 100Ω to 200Ω will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances. GROUNDING, BYPASSING, AND POWER SUPPLY RECOMMENDATIONS Proper grounding, bypassing, short lead length and the use of ground planes are particularly important for high frequency designs. Multi-layer PC boards are recommended for the best performance since they offer distinct advantages such as minimizing ground impedance, separation of signal layers by ground layers, etc. It is recommended that analog and digital ground pins of the VSP3010 be joined together at the IC and connected only to the analog ground of the system. The VSP3010 has analog and digital supply pins, however, the converter should be treated as an analog component and all supply pins should be powered by the analog supply. This will ensure the most consistent results since digital supply lines often carry high levels of noise that would otherwise be coupled into the converter and degrade the achievable performance. As the result of the high operation speed, the converter also generates high frequency current transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. Figure 3 shows the recommended decoupling schemes for the entire chip. In most cases, 0.1µF ceramic chip capacitors are adequate to keep the impedance low over the wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. When the VSP3010 is powered on, it will be initialized as a 3-channel CCD, 1V internal (2V full scale) reference mode with analog gain of 1. This mode is commonly used for CCD scanner applications. The calibration procedure is done at the very beginning of the scan. Once calibration is done, registers on VSP3010 will keep this information (offset and gain for each channel) during the operation. To calibrate the VSP3010, use the following procedure: Step 1: Set the VSP3010 to the proper mode. Step 2: Set analog PGA gain to 1 (code: 00H) and offset to 0mV (code: C0H). Step 3: Scan a dark line. Step 4: Calculate the pixel offsets according to the ADC output. Step 5: Readjust input Offset Registers. Step 6: Scan a white line. Step 7: Calculate gain. It will be the ADC full scale divided by the ADC output when the white line is scanned. Step 8: Set the Gain Register. If the ADC output is not close to full scale, go back to Step 3. The calibration is complete if the output is close to full scale. ® 13 VSP3010 VDDA VDD C4 0.1µF VDRV C7 10µF + TP0 C9 0.1µF C11 0.1µF C12 0.1µF C10 0.1µF C8 0.1µF VDDD VDDA + C18 10µF 40 38 37 36 35 34 33 32 31 30 C5 0.1µF C6 0.1µF VDDD VDRV JP4 ® C15 0.1µF + C16 10µF C17 0.1µF CM VDDA VREF VDDA TP0 REFT REFB VDDD VDRV GNDA GNDA GNDD BNC2 GINN GINN GNDA BINP B2 (D2) 27 B1 (D1) 26 (LSB) B0 (D0) 25 B3 (D3) 28 B4 (D4) 29 7 B5 (D5) 30 IDT74FCT541T STRT ADCCK CK1 CK2 GNDD RD WRT P/S SD SCLK VDDD OE IDT74FCT541T VSP3010 48 47 46 45 44 43 42 41 40 39 38 37 10 11 12 13 14 15 16 17 18 2 1 R8 1kΩ 10 9 8 7 6 5 WRT SD P/S SCLK TP5 RD OE 4 3 2 R5 50Ω TP6 CK1 BNC6 R6 50Ω CK2 BNC7 R7 50Ω VDD TP7 R10 1kΩ 1 11 12 13 14 15 16 17 18 19 20 R11 1kΩ C14 0.1µF 33 ADCCK 19 20 R9 1kΩ C13 0.1µF 17 19 21 23 B3 B2 B1 B0 (LSB) 9 8 7 6 5 4 3 1 3 5 7 9 11 13 15 B11 (MSB) B10 B9 B8 B7 B6 B5 B4 CLP CLP GNDA RINP RINN GNDA GINP B6 (D6) 31 B7 (D7) 32 B8 (A0) 33 B9 (A1) 34 B10 (A2) 35 TP1 2 3 RINN 5 6 4 C1 0.1µF 1 (MSB) B11 36 BNC1 R1 50Ω 14 12 10 8 6 4 2 JP1 TP2 C2 0.1µF VSP3010 R2 50Ω 8 9 BINN 11 GNDA 12 VDDA 10 BINN TP3 14 13 14 15 16 17 18 19 20 21 22 23 24 JP2 C3 0.1µF BNC3 R3 50Ω JP3 TP1 STRT BNC4 R4 50Ω ADCCK BNC5 29 28 27 26 25 24 22 20 18 15 39 OE FIGURE 3. VSP3010 Evaluation Board Schematic APPLICATION EXAMPLES +5V +5V 1µF 1µF 1µF 1µF TP0 48 47 46 45 44 43 42 41 40 39 38 37 VDDA VREF VDDA REFT REFB GNDA GNDA GNDD VDDD VDRV TP0 CM CLP 1 1µF 2 3 4 1µF 5 6 7 1µF 8 9 CLP GNDA RINP RINN GNDA GINP GINN GNDA BINP VSP3010 (MSB) B11 36 B10 (A2) 35 B9 (A1) 34 B8 (A0) 33 B7 (D7) 32 B6 (D6) 31 B5 (D5) 30 B4 (D4) 29 B3 (D3) 28 B2 (D2) 27 B1 (D1) 26 (LSB) B0 (D0) 25 (MSB) B11 B10 (A2) B9 (A1) B8 (A0) B7 (D7) B6 (D6) B5 (D5) B4 (D4) B3 (D3) B2 (D2) B1 (D1) (LSB) B0 (D0) RINP GINP BINP 10 BINN 11 GNDA ADCCK 12 VDDA STRT GNDD SCLK VDDD WRT CK1 CK2 P/S 13 14 15 16 17 18 19 20 21 22 23 24 STRT CK1 ADCCK CK2 WRT SD SCLK FIGURE 4. CCD Application Example. OE RD SD ® 15 VSP3010 +5V +5V 1µF 1µF 1µF 1µF TP0 48 47 46 45 44 43 42 41 40 39 38 37 VDDA VREF VDDA REFT REFB GNDA GNDA GNDD VDDD VDRV TP0 CM 1 2 RINP CLP GNDA RINP RINN GNDA GINP GINN GNDA BINP VSP3010 (MSB) B11 36 B10 (A2) 35 B9 (A1) 34 B8 (A0) 33 B7 (D7) 32 B6 (D6) 31 B5 (D5) 30 B4 (D4) 29 B3 (D3) 28 B2 (D2) 27 B1 (D1) 26 (LSB) B0 (D0) 25 ADCCK GNDD SCLK STRT VDDD WRT CK1 CK2 P/S OE RD SD (MSB) B11 B10 (A2) B9 (A1) B8 (A0) B7 (D7) B6 (D6) B5 (D5) B4 (D4) B3 (D3) B2 (D2) B1 (D1) (LSB) B0 (D0) 3 4 5 GINP 6 7 8 BINP BINN 9 10 BINN 11 GNDA 12 VDDA 13 14 15 16 17 18 19 20 21 22 23 24 STRT CK1 ADCCK WRT SD SCLK FIGURE 5. CIS Application Example. ® VSP3010 16