VSP5610
VSP5611
VSP5612
SBES021 – JUNE 2011
www.ti.com
16-Bit, 4-Channel, CCD/CMOS Sensor
Analog Front-End with Timing Generator
Check for Samples: VSP5610, VSP5611, VSP5612
FEATURES
APPLICATIONS
•
•
•
•
1
23
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Four-Channel CCD/CMOS Signal: 2-Channel,
3-Channel, and 4-Channel Selectable
Power Supply: 3.3 V Only, Typ
(Built-in LDO, 3.3 V to 1.8 V)
Maximum Conversion Rate:
– VSP5610: 35 MSPS
– VSP5611: 50 MSPS
– VSP5612: 70 MSPS
16-Bit Resolution
CDS/SH Selectable
Maximum Input Signal Range: 2.0 V
Analog and Digital Hybrid Gain:
– Analog Gain: 0.5 V/V to 3.5 V/V in
3/64-V/V Steps
– Digital Gain: 1 V/V to 2 V/V in
1/256-V/V Steps
Offset Correction DAC: ±250 mV, 8-Bit
Standard LVDS/CMOS Selectable Output:
– LVDS:
– Data Channel: 2-Channel, 3-Channel
– Clock Channel: 1-Channel
– 8-Bit/7-Bit Serializer Selectable
– CMOS: 4 Bits × 4, 8 Bits × 2
Timing Generator:
– Fast Transfer Clock: Eight Signals
– Slow Transfer Clock: Six Signals
Timing Adjustment Resolution: tMCLK/48
Input Clamp/Input Reference Level
Internal/External Selectable
Reference DAC: 0.5 V, 1.1 V, 1.5 V, 2 V
SPI™: Three-Wire Serial
GPIO: Four-Port
Copiers
Facsimile Machines
Scanners
DESCRIPTION
The
VSP5610/11/12
are
high-speed,
high-performance, 16-bit analog-to-digital-converters
(ADCs) that have four independent sampling circuit
channels for multi-output charge-coupled device
(CCD)
and
complementary
metal
oxide
semiconductor (CMOS) line sensors. Pixel data from
the sensor are sampled by the sample/hold (SH) or
correlated double sampler (CDS) circuit, and are then
converted to digital data by an ADC. Data output is
selectable in low-voltage differential signaling (LVDS)
or CMOS modes.
The VSP5610/11/12 include a programmable gain to
support the pixel level inflection caused by luminance.
The integrated digital-to-analog-converter (DAC) can
be used to adjust the offset level for the analog input
signal. Furthermore, the timing generator (TG) is
integrated in these devices for the control of sensor
operation.
The VSP5610/11/12 use 1.65 V to 1.95 V for the core
voltage and 3.0 V to 3.6 V for I/Os. The core voltage
is supplied by a built-in low-dropout regulator (LDO).
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
VSP5610
VSP5611
VSP5612
SBES021 – JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA
VSP5610
QFN-56
RSH
0°C to +85°C
VSP5610
VSP5610RSHR
Tape and Reel
VSP5611
QFN-56
RSH
0°C to +85°C
VSP5611
VSP5611RSHR
Tape and Reel
VSP5612
QFN-56
RSH
0°C to +85°C
VSP5612
VSP5612RSHR
Tape and Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VSP5610, VSP5611, VSP5612
UNIT
Supply voltage: VDD, DVDD_IO, LVDD
4.0
V
Supply voltage difference: VDD, DVDD_IO, LVDD
±0.6
V
Ground voltage difference: VSS, DVSS, LVSS
±0.1
V
Digital voltage input
–0.3 to DVDD_IO + 0.3
V
Analog voltage input
–0.3 to VDD + 0.3
V
Digital input current
±10
mA
Analog input current
±10
mA
Ambient temperature under bias
–40 to +125
°C
Storage temperature
–55 to +150
°C
Junction temperature
+150
°C
Package temperature (IR reflow, peak)
+260
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
LDO and analog I/O power-supply voltage
VDD
3.0
3.3
3.6
V
Digital power-supply voltage
DVDD_IO
3.0
3.3
3.6
V
LVDS/CMOS power-supply voltage
LVDD
3.0
3.3
3.6
V
Supply voltage difference
VDD, DVDD_IO, LVDD
0.3
V
Digital input logic family
Master clock frequency (MCLK)
–0.3
Low-voltage CMOS
VSP5610
1
11.66
MHz
VSP5611
1
16.66
MHz
VSP5612
1
23.33
MHz
10
MHz
+85
°C
Serial I/O clock frequency (SCLK)
Operating free-air temperature
2
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5610 VSP5611 VSP5612
VSP5610
VSP5611
VSP5612
SBES021 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VSP5610
All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 8.75 MHz, and four-channel mode, unless
otherwise noted.
VSP5610
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Allowable input voltage
0
Full-scale range
Gain = 1 V/V
Input capacitor
VDD
V
1
VPP
5
pF
DIGITAL INPUT
Positive-going threshold
VT+
Negative-going threshold
VT–
Hysteresis (VT+ – VT–)
ΔVT
Input current
DVDD_IO × 0.7
V
DVDD_IO × 0.3
V
DVDD_IO × 0.13
V
±1
IIN
Input capacitor
µA
5
pF
DIGITAL OUTPUT
High-level output voltage
VOH
Low-level output voltage
VOL
TG output timing skew
IOH = –2 mA
DVDD_IO – 0.45
V
IOH = –4 mA
DVDD_IO – 0.50
V
IOH = –8 mA
DVDD_IO – 0.50
V
IOL = 2 mA
0.35
V
IOL = 4 mA
0.50
V
IOL = 8 mA
0.65
V
ns
XP1, XP2, XP3, XP4
–1
1
Other signals
–2
2
ns
80
MHz
400
mV
CMOS data output bit rate
LVDS DRIVER (TA, TB, TC, TCLK)
Differential steady-state output
voltage adjustment range
|VOD|
Differential steady-state output
adjustment step
|VOD|
Differential steady-state output
voltage tolerance
|VOD|
Change in the steady-state
differential output voltage magnitude
between opposite binary states
Δ|VOD|
Steady-state common-mode output
voltage
VOC(SS)
Peak-to-peak common-mode output
voltage
VOC(PP)
RL = 100 Ω
350
3
–30
RL = 100 Ω
Short-circuit output current
IOS
VO = 0 V (VO = TA, TB, TC, TCLK)
Hi-Z output current
IOZ
VO = 0 V to LVDD
(VO = TA, TB, TC, TCLK)
Transition time, differential output
voltage
300
1.125
tLR/tLF
8
30
%
35
mV
1.375
V
80
150
mV
–6
±24
mA
±10
µA
1.5
ns
35
MHz
100
mV
0.75
TCLK clock rate
Steps
LVDS RECEIVER (RCLK)
Positive-going differential input
threshold voltage
VIT+
Negative-going differential input
threshold voltage
VIT–
–100
RCLK clock rate
1
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5610 VSP5611 VSP5612
mV
11.66
MHz
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VSP5610
VSP5611
VSP5612
SBES021 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VSP5610 (continued)
All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 8.75 MHz, and four-channel mode, unless
otherwise noted.
VSP5610
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
LDO and analog I/O supply voltage
Digital I/O supply voltage
VDD
3.0
3.3
3.6
V
DVDD_IO
3.0
3.3
3.6
V
LVDD
3.0
3.3
3.6
V
LVDS/CMOS supply voltage
LDO and analog I/O current
Digital I/O current
VDD
DVDD_IO
CMOS current
LVDD
LVDS current
LVDD
Power consumption
Load = 10 pF
74.9
mA
3.8
mA
10
mA
Three-pair data, one-pair clock
24
mA
LVDS, three-pair
339
mW
CMOS output
317
mW
Standby mode (MCLK = 0 MHz)
15
mW
TEMPERATURE RANGE
Operation temperature
TA
Thermal resistor (junction-to-air)
θJA
Thermal resistor (junction-to-case)
θJC
0
PCB (50 mm × 50 mm, four-layer),
0 lfm airflow
+85
°C
29
°C/W
24
°C/W
DLL, PLL
MCLK input frequency
fMCLK
1
MCLK > 5 MHz
MCLK modulated frequency
–3.5
MCLK modulated amplitude
DLL tap number
Maximum DLL and PLL lock-up time
MCLK = 1 MHz
11.66
MHz
35
kHz
0
%
48
Taps
10
ms
TRANSFER CHARACTERISTICS
Channels
2
Resolution
4
16
Conversion rate
Channels
Bits
LVDS, two- and three-channel mode
1
11.66
MHz/Ch
LVDS, four-channel mode
1
8.75
MHz/Ch
CMOS 8-bit × 2, two-channel mode
1
11.66
MHz/Ch
CMOS 4-bit × 4, two-channel mode
1
10
MHz/Ch
CMOS 8-bit × 2, three-channel
mode
1
11.66
MHz/Ch
CMOS 4-bit × 4, three-channel
mode
1
6.7
MHz/Ch
CMOS 8-bit × 2, four-channel mode
1
8.75
MHz/Ch
CMOS 4-bit × 4, four-channel mode
1
5
MHz/Ch
Maximum differential nonlinearity
Gain = 1 V/V, 12-bit
±0.5
LSB
Maximum integral nonlinearity
Gain = 1 V/V, 12-bit
±2
LSB
No missing codes
Signal-to-noise ratio
Analog channel crosstalk
Specified
SNR
Gain = 1 V/V
72 (1)
Gain = 1 V/V, 12-bit, full-scale step
–10
Total absolute gain error
(1)
4
76
dB
±3
LSB
10
%
Specified by design.
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VSP5610
VSP5611
VSP5612
SBES021 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VSP5610 (continued)
All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 8.75 MHz, and four-channel mode, unless
otherwise noted.
VSP5610
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG PROGRAMMABLE GAIN (APG)
Gain range
APG_x
0.5
Gain step
3.5
63
Gain relative error
Basis gain = 1 V/V
Gain monotonicity
Only APG_x
–10
V/V
Steps
10
%
2.0
V/V
Specified
DIGITAL PROGRAMMABLE GAIN (DPG)
Gain range
DPG_x
1.0
Gain step
255
Gain monotonicity
Only DPG_x
Steps
Specified
AIN REFERENCE LEVEL (REF_AIN)
Internal DAC output
VRINT
Internal DAC output tolerance
Setting code = 2
0.5
V
Setting code = 3
1.1
V
Setting code = 0 (default)
1.5
V
Setting code = 1
2.0
V
VRINT
Internal DAC output temperature
drift
VRINT
External reference range
VREXT
TA = 0°C to +85°C
(2)
–10
10
%
–2
2
%
0.5
VDD – 0.9
V
INPUT CLAMP
Clamp level
VCLP
Internal reference level clamp
VRINT
V
External reference level clamp
VREXT
V
Fixed level clamp
Clamp-on resistance
RCLP
2.2
V
500
Ω
OFFSET DAC
Resolution
8
Setting tolerance
Temperature drift
(2)
Bits
±250
Output range
TA = 0°C to +85°C
(2)
mV
–10
10
%
–2
2
%
Specified by design.
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5610 VSP5611 VSP5612
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VSP5610
VSP5611
VSP5612
SBES021 – JUNE 2011
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ELECTRICAL CHARACTERISTICS: VSP5611
All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 12.5 MHz, and four-channel mode, unless
otherwise noted.
VSP5611
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Allowable input voltage
0
Full-scale range
Gain = 1 V/V
Input capacitor
VDD
V
1
VPP
5
pF
DIGITAL INPUT
Positive-going threshold
VT+
Negative-going threshold
VT–
Hysteresis (VT+ – VT–)
ΔVT
Input current
DVDD_IO × 0.7
DVDD_IO × 0.3
V
DVDD_IO × 0.13
V
±1
IIN
Input capacitor
V
5
µA
pF
DIGITAL OUTPUT
High-level output voltage
Low-level output voltage
VOH
VOL
TG output timing skew
IOH = –2 mA
DVDD_IO – 0.45
V
IOH = –4 mA
DVDD_IO – 0.50
V
IOH = –8 mA
DVDD_IO – 0.50
V
IOL = 2 mA
0.35
V
IOL = 4 mA
0.50
V
IOL = 8 mA
0.65
V
ns
XP1, XP2, XP3, XP4
–1
1
Other signals
–2
2
ns
80
MHz
400
mV
CMOS data output bit rate
LVDS DRIVER (TA, TB, TC, TCLK)
Differential steady-state output
voltage adjustment range
|VOD|
Differential steady-state output
adjustment step
|VOD|
Differential steady-state output
voltage tolerance
|VOD|
Change in the steady-state
differential output voltage magnitude
between opposite binary states
Δ|VOD|
Steady-state common-mode output
voltage
VOC(SS)
Peak-to-peak common-mode output
voltage
VOC(PP)
RL = 100 Ω
350
3
–30
RL = 100 Ω
Short-circuit output current
IOS
VO = 0 V (VO = TA, TB, TC, TCLK)
Hi-Z output current
IOZ
VO = 0 V to LVDD
(VO = TA, TB, TC, TCLK)
Transition time, differential output
voltage
300
1.125
tLR/tLF
8
30
%
35
mV
1.375
V
80
150
mV
–6
±24
mA
±10
µA
1.5
ns
50
MHz
100
mV
0.75
TCLK clock rate
Steps
LVDS RECEIVER (RCLK)
Positive-going differential input
threshold voltage
VIT+
Negative-going differential input
threshold voltage
VIT–
–100
RCLK clock rate
6
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1
mV
16.66
MHz
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5610 VSP5611 VSP5612
VSP5610
VSP5611
VSP5612
SBES021 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VSP5611 (continued)
All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 12.5 MHz, and four-channel mode, unless
otherwise noted.
VSP5611
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
LDO and analog I/O supply voltage
Digital I/O supply voltage
VDD
3.0
3.3
3.6
V
DVDD_IO
3.0
3.3
3.6
V
LVDD
3.0
3.3
3.6
V
LVDS/CMOS supply voltage
LDO and analog I/O current
Digital I/O current
VDD
DVDD_IO
CMOS current
LVDD
LVDS current
LVDD
Power consumption
Load = 10 pF
99.6
mA
5.4
mA
10
mA
Three-pair data, one-pair clock
24
mA
LVDS, three-pair
426
mW
CMOS output
398
mW
Standby mode (MCLK = 0 MHz)
15
mW
TEMPERATURE RANGE
Operation temperature
TA
Thermal resistor (junction-to-air)
θJA
Thermal resistor (junction-to-case)
θJC
0
PCB (50 mm × 50 mm, four-layer),
0 lfm airflow
°C
+85
29
°C/W
24
°C/W
DLL, PLL
MCLK input frequency
fMCLK
1
MCLK > 5 MHz
MCLK modulated frequency
–3.5
MCLK modulated amplitude
DLL tap number
Maximum DLL and PLL lock-up time
MCLK = 1 MHz
16.66
MHz
35
kHz
0
%
48
Taps
10
ms
TRANSFER CHARACTERISTICS
Channel
2
Resolution
4
Channels
16
Conversion rate
Bits
LVDS, two- and three-channel mode
1
16.66
MHz/Ch
LVDS, four-channel mode
1
12.5
MHz/Ch
CMOS 8-bit × 2, two-channel mode
1
16.66
MHz/Ch
CMOS 4-bit × 4, two-channel mode
1
10
MHz/Ch
CMOS 8-bit × 2, three-channel
mode
1
13.3
MHz/Ch
CMOS 4-bit × 4, three-channel
mode
1
6.7
MHz/Ch
CMOS 8-bit × 2, four-channel mode
1
10
MHz/Ch
CMOS 4-bit × 4, four-channel mode
1
5
MHz/Ch
Maximum differential nonlinearity
Gain = 1 V/V, 12-bit
±0.5
LSB
Maximum integral nonlinearity
Gain = 1 V/V, 12-bit
±2
LSB
No missing codes
Specified
Signal-to-noise ratio
SNR
Analog channel crosstalk
Gain = 1 V/V
72 (1)
–10
Total absolute gain error
(1)
76
dB
±6.5
Gain = 1 V/V, 12-bit, full-scale step
LSB
10
%
Specified by design.
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5610 VSP5611 VSP5612
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VSP5610
VSP5611
VSP5612
SBES021 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VSP5611 (continued)
All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 12.5 MHz, and four-channel mode, unless
otherwise noted.
VSP5611
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG PROGRAMMABLE GAIN (APG)
Gain range
APG_x
0.5
Gain step
3.5
63
Gain relative error
Basis gain = 1 V/V
Gain monotonicity
Only APG_x
–10
V/V
Steps
10
%
2.0
V/V
Specified
DIGITAL PROGRAMMABLE GAIN (DPG)
Gain range
DPG_x
1.0
Gain step
255
Gain monotonicity
Only DPG_x
Steps
Specified
AIN REFERENCE LEVEL (REF_AIN)
Internal DAC output
Internal DAC output tolerance
VRINT
Setting code = 2
0.5
V
Setting code = 3
1.1
V
Setting code = 0 (default)
1.5
V
Setting code = 1
2.0
V
VRINT
Internal DAC output temperature
drift
VRINT
External reference range
VREXT
TA = 0°C to +85°C
(2)
–10
10
%
–2
2
%
0.5
VDD – 0.9
V
INPUT CLAMP
Clamp level
VCLP
Internal reference level clamp
VRINT
V
External reference level clamp
VREXT
V
Fixed level clamp
Clamp-on resistance
RCLP
2.2
V
500
Ω
OFFSET DAC
Resolution
8
Setting tolerance
Temperature drift
(2)
8
Bits
±250
Output range
TA = 0°C to +85°C
(2)
mV
–10
10
%
–2
2
%
Specified by design.
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VSP5610
VSP5611
VSP5612
SBES021 – JUNE 2011
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ELECTRICAL CHARACTERISTICS: VSP5612
All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 17.5 MHz, and four-channel mode, unless
otherwise noted.
VSP5612
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Allowable input voltage
0
Full-scale range
Gain = 1 V/V
Input capacitor
VDD
V
1
VPP
5
pF
DIGITAL INPUT
Positive-going threshold
VT+
Negative-going threshold
VT–
Hysteresis (VT+ – VT–)
ΔVT
Input current
DVDD_IO × 0.7
V
DVDD_IO × 0.3
V
DVDD_IO × 0.13
V
±1
IIN
Input capacitor
µA
5
pF
DIGITAL OUTPUT
High-level output voltage
VOH
Low-level output voltage
VOL
TG output timing skew
IOH = –2 mA
DVDD_IO – 0.45
V
IOH = –4 mA
DVDD_IO – 0.50
V
IOH = –8 mA
DVDD_IO – 0.50
V
IOL = 2 mA
0.35
V
IOL = 4 mA
0.50
V
IOL = 8 mA
0.65
V
ns
XP1, XP2, XP3, XP4
–1
1
Other signals
–2
2
ns
80
MHz
400
mV
CMOS data output bit rate
LVDS DRIVER (TA, TB, TC, TCLK)
Differential steady-state output
voltage adjustment range
|VOD|
Differential steady-state output
adjustment step
|VOD|
Differential steady-state output
voltage tolerance
|VOD|
Change in the steady-state
differential output voltage magnitude
between opposite binary states
Δ|VOD|
Steady-state common-mode output
voltage
VOC(SS)
Peak-to-peak common-mode output
voltage
VOC(PP)
RL = 100 Ω
350
3
–30
RL = 100 Ω
Short-circuit output current
IOS
VO = 0 V (VO = TA, TB, TC, TCLK)
Hi-Z output current
IOZ
VO = 0 V to LVDD
(VO = TA, TB, TC, TCLK)
Transition time, differential output
voltage
300
1.125
tLR/tLF
8
30
%
35
mV
1.375
V
80
150
mV
–6
±24
mA
±10
µA
1.5
ns
70
MHz
100
mV
0.75
TCLK clock rate
Steps
LVDS RECEIVER (RCLK)
Positive-going differential input
threshold voltage
VIT+
Negative-going differential input
threshold voltage
VIT–
–100
RCLK clock rate
1
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP5610 VSP5611 VSP5612
mV
23.33
MHz
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9
VSP5610
VSP5611
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ELECTRICAL CHARACTERISTICS: VSP5612 (continued)
All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 17.5 MHz, and four-channel mode, unless
otherwise noted.
VSP5612
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
LDO and analog I/O supply voltage
Digital I/O supply voltage
VDD
3.0
3.3
3.6
V
DVDD_IO
3.0
3.3
3.6
V
LVDD
3.0
3.3
3.6
V
LVDS/CMOS supply voltage
LDO and analog I/O current
Digital I/O current
VDD
DVDD_IO
CMOS current
LVDD
LVDS current
LVDD
Power consumption
Load = 10 pF
133
mA
7.5
mA
10
mA
Three-pair data, one-pair clock
24
mA
LVDS, three-pair
542
mW
CMOS output
507
mW
Standby mode (MCLK = 0 MHz)
15
mW
TEMPERATURE RANGE
Operation temperature
TA
Thermal resistor (junction-to-air)
θJA
Thermal resistor (junction-to-case)
θJC
0
PCB (50 mm × 50 mm, four-layer),
0 lfm airflow
+85
°C
29
°C/W
24
°C/W
DLL, PLL
MCLK input frequency
fMCLK
1
MCLK > 5 MHz
MCLK modulated frequency
–3.5
MCLK modulated amplitude
DLL tap number
Maximum DLL and PLL lock-up time
MCLK = 1 MHz
23.33
MHz
35
kHz
0
%
48
Taps
10
ms
TRANSFER CHARACTERISTICS
Channel
2
Resolution
4
16
Conversion rate
Channels
Bits
LVDS, two- and three-channel mode
1
23.33
MHz/Ch
LVDS, four-channel mode
1
17.5
MHz/Ch
CMOS 8-bit × 2, two-channel mode
1
20
MHz/Ch
CMOS 4-bit × 4, two-channel mode
1
10
MHz/Ch
CMOS 8-bit × 2, three-channel
mode
1
13.3
MHz/Ch
CMOS 4-bit × 4, three-channel
mode
1
6.7
MHz/Ch
CMOS 8-bit × 2, four-channel mode
1
10
MHz/Ch
CMOS 4-bit × 4, four-channel mode
1
5
MHz/Ch
Maximum differential nonlinearity
Gain = 1 V/V, 12-bit
±0.5
LSB
Maximum integral nonlinearity
Gain = 1 V/V, 12-bit
±2
LSB
No missing codes
Signal-to-noise ratio
Analog channel crosstalk
Specified
SNR
Gain = 1 V/V
72 (1)
Gain = 1 V/V, 12-bit, full-scale step
–10
Total absolute gain error
(1)
10
75
dB
±15
LSB
10
%
Specified by design.
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ELECTRICAL CHARACTERISTICS: VSP5612 (continued)
All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 17.5 MHz, and four-channel mode, unless
otherwise noted.
VSP5612
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG PROGRAMMABLE GAIN (APG)
Gain range
APG_x
0.5
Gain step
3.5
63
Gain relative error
Basis gain = 1 V/V
Gain monotonicity
Only APG_x
V/V
Steps
–10
10
%
2.0
V/V
Specified
DIGITAL PROGRAMMABLE GAIN (DPG)
Gain range
DPG_x
1.0
Gain step
255
Gain monotonicity
Only DPG_x
Steps
Specified
AIN REFERENCE LEVEL (REF_AIN)
Internal DAC output
VRINT
Internal DAC output tolerance
Setting code = 2
0.5
V
Setting code = 3
1.1
V
Setting code = 0 (default)
1.5
V
Setting code = 1
2.0
V
VRINT
Internal DAC output temperature
drift
VRINT
External reference range
VREXT
TA = 0°C to +85°C
(2)
–10
10
%
–2
2
%
0.5
VDD – 0.9
V
INPUT CLAMP
Clamp level
VCLP
Internal reference level clamp
VRINT
V
External reference level clamp
VREXT
V
Fixed level clamp
Clamp-on resistance
RCLP
2.2
V
500
Ω
OFFSET DAC
Resolution
8
Setting tolerance
Temperature drift
(2)
Bits
±250
Output range
TA = 0°C to +85°C
(2)
mV
–10
10
%
–2
2
%
Specified by design.
THERMAL INFORMATION
VSP561xRSH
THERMAL METRIC
(1)
RSH
UNITS
56 PINS
θJA
Junction-to-ambient thermal resistance
25.8
θJCtop
Junction-to-case (top) thermal resistance
13.2
θJB
Junction-to-board thermal resistance
3.5
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
3.5
θJCbot
Junction-to-case (bottom) thermal resistance
0.4
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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PARAMETERIC MEASUREMENT INFORMATION
Analog Input Specification (AIN1, AIN2, AIN3, AIN4)
The analog input specification has two signal inputs: negative and positive. These inputs are shown in Figure 1a
and Figure 1b, respectively.
1/fPIX
VDD
1/fPIX
VDD
VSIG
VRST
VSIG
VOFFSET
VOFFSET
VSS
VSS
a) Negative Signal Input (AINx_POL
(1)
= 0)
b) Positive Signal Input (AINx_POL
(1)
= 1)
Figure 1. Analog Input Definition
Table 1. Timing Characteristics for Figure 1
PARAMETER
Input pixel rate
TEST CONDITIONS
fPIX
Signal range
VSIG
Maximum full-scale range
VSIG
Reset field through noise
range
VRST
MAX
UNIT
VSP5610
1
11.66
MHz/Ch
VSP5611
1
16.66
MHz/Ch
VSP5612
1
23.33
MHz/Ch
Negative (AINx_POL
(1)
MIN
= 0)
VOFFSET
V
Positive (AINx_POL (1) = 1)
VDD – VOFFSET
V
Gain = 0.5 V/V
1.8
–VOFFSET
Fixed level clamp mode (REF_SEL = 0)
Offset level
(1)
12
VOFFSET
TYP
2
2.2
V
VDD – VOFFSET
V
2.2
V
Internal reference level clamp mode
(REF_SEL = 1)
VRINT
V
External reference level clamp mode
(REF_SEL = 2)
VREXT
V
AINx_POL = Analog input polarity setting register (x = 1, 2, 3, and 4).
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LVDS Output Voltage Specification
The test load and voltage definition for the LVDS outputs are shown in Figure 2.
RL/2
Tx+
(1)
VOD
RL/2
Tx-
(1)
VOC
100%
80%
VOD(H)
0V
VOD(L)
20%
0%
tLF
tLR
VOC(PP)
VOC(SS)
VOC(SS)
0V
(1) RL/2 = 49.9 Ω ± 1%
Figure 2. Test Load and Voltage Definition for LVDS Outputs
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PIN CONFIGURATION
14
XRS
XCP
X2L
X1L
XP4
XP3
XP2
XP1
XCLR
XST/GPIO3
SDO/GPIO1
XLSYNC
DVSS
DVDD_IO
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RSH PACKAGE
QFN-56
(TOP VIEW)
TC+/D4
AIN3
8
35
TC-/D5
AINGND3
9
34
TCLK+/CK0/D6
AIN4
10
33
TCLK-/CK1/D7
AINGND4
11
32
SCLK
VSS
12
31
SDI
REF_AIN
13
30
SEN
ISET
14
29
DVSS
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RCLKP
28
36
27
7
RCLKN
AINGND2
26
TB-/D3
DVSS
37
25
6
SDO/GPIO2
AIN2
24
TB+/D2
GPIO0
38
23
5
XSH4
AINGND1
22
TA-/D1
XSH3
39
21
4
XSH2
AIN1
20
TA+/D0
XSH1
40
19
3
VDD
VSS
18
LVDD
VSS
41
17
2
REFN
AVDD_LDO
16
LVSS
REFP
42
15
1
VSS
TEST
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PIN ASSIGNMENTS
PIN
NUMBER
PIN NAME
TYPE (1)
1
TEST
DI3.3
Internal test pin; connect to DGND
2
AVDD_LDO
AP1.8
Analog core power voltage output; not connected, open
3
VSS
AGND
LDO and analog I/O ground
4
AIN1
AI3.3
First channel analog signal input (2)
5
AINGND1
AI3.3
First channel analog signal ground (2)
6
AIN2
AI3.3
Second channel analog signal input (2)
7
AINGND2
AI3.3
Second channel analog signal ground (2)
8
AIN3
AI3.3
Third channel analog signal input (2)
9
AINGND3
AI3.3
Third channel analog signal ground (2)
10
AIN4
AI3.3
Fourth channel analog signal input (2)
11
AINGND4
AI3.3
Fourth channel analog signal ground (2)
12
VSS
AGND
LDO and analog I/O ground
13
REF_AIN
AI3.3/AO3.3
14
ISET
LVO1.8
Internal reference voltage output;bypass to ground with a 10-kΩ ±1% resister
15
VSS
AGND
LDO and analog I/O ground
16
REFP
AO1.8
Positive reference; bypass to AGND with a 0.1-μF capacitor
17
REFN
AO1.8
Negative reference; bypass to AGND with a 0.1-μF capacitor
18
VSS
AGND
LDO and analog I/O ground
19
VDD
AP3.3
LDO and analog I/O power supply
20
XSH1
DO3.3
Sensor shift gate output 1
21
XSH2
DO3.3
Sensor shift gate output 2
22
XSH3
DO3.3
Sensor shift gate output 3
23
XSH4
DO3.3
Sensor shift gate output 4
24
GPIO0
DIO3.3
DESCRIPTION
REF_DAC_IN
0 = Analog signal reference output (default)
1 = Analog signal reference input
GPIO0_SEL
0 = GPI0, general-purpose input port 0 (default) (In case of input, internal pull-down resistor)
1 = GPO0, general-purpose output port 0
GPIO2_SDO_SEL
25
0
1
2
3
= GPI2, general-purpose input port 2 (default) (In case of input, internal pull-down resistor)
= GPO2, general-purpose output port 2
= Reserved
= SDO, serial I/F data output
SDO/GPIO2
DIO3.3
26
DVSS
DGND
Digital ground
27
RCLKN
LVI3.3
LVDS clock input
28
RCLKP
LVI3.3
CMOS master clock input/positive LVDS clock input
29
DVSS
DGND
Digital ground
30
SEN
DI3.3
Serial I/F enable; active low, internal pull-up resistor
31
SDI
DIO3.3
32
SCLK
DI3.3
33
TCLK–/CK1/
D7
LVO3.3
Negative LVDS clock output/Clock output 1/Data output bit 7
34
TCLK+/CK0/
D6
LVO3.3
Positive LVDS clock output/Clock output 0/Data output bit 6
SDI_BUFF_CTRL
(1)
(2)
0 = Serial I/F data input
1 = Serial I/F data input/output (Internal pull-down resistor)
Serial I/F clock (internal pull-down resistor)
AP3.3 = 3.3-V analog power supply; AP1.8 = 1.8-V analog power supply; AGND = analog ground; GND = ground; AO3.3 = 3.3-V analog
output; AO1.8 = 1.8-V analog output; AI3.3 = 3.3-V analog input; DP3.3 = 3.3-V digital power supply; DP1.8 = 1.8-V digital power
supply; DGND = digital ground; DO3.3 = 3.3-V digital output; DI3.3 = 3.3-V digital input; DIO3.3 = 3.3-V digital I/O; LVP3.3 = 3.3-V
LVDS power supply; LVGND = LVDS ground; LVO3.3 = 3.3-V LVDS output; LVI3.3 = 3.3-V LVDS input; and LVO = 3.3-V LVDS output.
If these pins are unused, they can be opened or decoupled to GND with a decoupling capacitor.
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PIN ASSIGNMENTS (continued)
PIN
NUMBER
PIN NAME
TYPE (1)
35
TC–/D5
LVO3.3
Negative TC channel LVDS data output/Data output bit 5
36
TC+/D4
LVO3.3
Positive TC channel LVDS data output/Data output bit 4
37
TB–/D3
LVO3.3
Negative TB channel LVDS data output/Data output bit 3
38
TB+/D2
LVO3.3
Positive TB channel LVDS data output/Data output bit 2
39
TA–/D1
LVO3.3
Negative TA channel LVDS data output/Data output bit 1
40
TA+/D0
LVO3.3
Positive TA channel LVDS data output/Data output bit 0
41
LVDD
LVP3.3
LVDS/CMOS output power supply
42
LVSS
LVGND
LVDS/CMOS output ground
43
DVDD_IO
DP3.3
Digital I/O power supply
44
DVSS
DGND
Digital ground
DESCRIPTION
XLSYNC_SEL
45
XLSYNC
DIO3.3
0 = Internal line synchronous signal output (default)
(In case of input, internal pull-down resistor)
1 = External line synchronous signal input. Polarity is set by the XLSYNC_POL register
(default is active high).
GPIO1_SDO_SEL
46
SDO/GPIO1
DIO3.3
0
1
2
3
= GPI1, general-purpose input port 1 (default) (In case of input, internal pull-down resistor)
= GPO1, general-purpose output port 1
= Reserved, internal test input
= SDO, serial I/F data output
GPIO3_XST_SEL
16
0
1
2
3
= GPI3, general-purpose input port 3 (default) (In case of input, internal pull-down resistor)
= GPO3, general-purpose output port 3
= Reserved, internal test input
= XST, storage pulse output
47
XST/GPIO3
DIO3.3
48
XCLR
DO3.3
Sensor clear gate output
49
XP1
DO3.3
Fast transfer clock output φ1
50
XP2
DO3.3
Fast transfer clock output φ2
51
XP3
DO3.3
Fast transfer clock output φ3
52
XP4
DO3.3
Fast transfer clock output φ4
53
X1L
DO3.3
Fast transfer clock output 1L
54
X2L
DO3.3
Fast transfer clock output 2L
55
XCP
DO3.3
Clamp gate clock output
56
XRS
DO3.3
Reset gate clock output
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FUNCTIONAL BLOCK DIAGRAM
3.3 V
CDS
/SH
+
MUX
CDS
/SH
AINGND2
APG
16
AIN3
4:1
MUX
8-Bit
DAC
Clamp
TA+/D0
Serializer
Parallel Load
7- or 8-Bit Shift
Register
LVDS
Serializer
Parallel Load
7- or 8-Bit Shift
Register
LVDS
Serializer
Parallel Load
7- or 8-Bit Shift
Register
LVDS
TA /D1
APG
8-Bit
DAC
Clamp
LVSS
ISET
VSS
VDD
+
AINGND1
AIN2
4
LDO
3.3 V to 1.8 V
8-Bit
DAC
Clamp
LVDD
AVDD_LDO
DVSS
DVDD_IO
10 kΩ
±1%
Ref
DAC
REF_AIN
AIN1
3.3 V
3.3 V
16-Bit
ADC
TB+/D2
TB /D3
TC+/D4
TC /D5
DPG
TCLK+/CK0/D6
LVDS
+
CDS
/SH
AINGND3
TCLK /CK1/D7
APG
PLL
8-Bit
DAC
Clamp
AIN4
+
ADCK
CDS
/SH
AINGND4
LVCK
SHD_A, SHD_B,
SHP_A, SHP_B
APG
DLL
48 Taps
DLL Tap Selector
REFP
REFN
Internal
Reference
Line
Sync
Timing Generator
Serial Interface/Register
RCLKP
LVDS
RCLKN
XLSYNC
XP1
XP2
X2L
X1L
XRS
XCP
XP3
XP4
XSH4
XSH3
XSH2
XSH1
XCLR
XST/GPIO3
SDO/GPIO2
SDO/GPIO1
GPIO0
SDI
SEN
SCLK
TEST
Figure 3. VSP5610/11/12 Block Diagram
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SYSTEM OVERVIEW
INTRODUCTION
The VSP5610/11/12 are analog front-end (AFE) devices for CCD and CMOS line image sensor applications such
as copiers, facsimile machines, etc. The VSP5610/11/12 each provide four independent data processing
channels.
The data from each image sensor channel are sampled and held by either the SH or CDS circuit and are then
converted into digital data by an ADC. The digital data for each channel are later converted into serial data that
can be output in either LVDS mode or CMOS mode.
AFE BLOCK
ANALOG SIGNAL INPUT
These devices have four channels that can be used as analog input ports for an image sensor. In addition to the
four-channel input, this AFE device also supports three-channel and two-channel inputs. Table 2 shows the
register settings required to select the different channel modes.
Table 2. Analog Input Channel Mode Selection
MODE
AIN_CH_SEL
AIN1
AIN2
AIN3
AIN4
Two-channel
2
Active
Standby
Active
Standby
Three-channel
1
Active
Active
Active
Standby
Four-channel
0
Active
Active
Active
Active
Each analog input supports CDS and simple SH circuits to accommodate CCD and CMOS image sensors. The
sampling mode can be selected independently for each channel by configuring the internal registers. As shown in
Table 3, if AINx_SH_CDS is set to '0', then the corresponding channel operates in CDS mode.
Table 3. CDS/SH Mode Selection
(1)
AINx_SH_CDS (1)
SH/CDS
0
CDS
1
SH
AINx_POL = Analog input polarity setting register (x = 1, 2, 3, and 4).
In addition, these devices also support independent selection of the input signal polarity for each channel. Input
signal polarity can be set using the AINx_POL register, where x = 1, 2, 3, or 4. The input signal range and
polarity are defined in the Analog Input Specification section.
18
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Correlated Double Sampler (CDS) Mode (AINx_SH_CDS = 0)
CDS mode is designed to accommodate inputs from the CCD sensor. The output signal of a CCD image sensor
is sampled twice during one pixel period. First, the reference interval is sampled by the SHP pulse, then the data
interval is sampled by the SHD pulse. Subtracting these two samples provides the video information of the pixel
as well as removes any noise common to both intervals. Thus, CDS plays an important role in reducing the reset
noise and other low-frequency noises that are present on the CCD output signal. Figure 4 shows a diagram of
CDS mode.
OFDAC_x[7:0]
VCLP
CLPDM
SHP_y
SH_REFx_EN
CLP_y
CLP_y
(1)
Offset
DAC
SHP AINx_POL
/SHD
RCLP
CSx
CFBx
CSx
AINx
+
AINGNDx(1)
VP
VN
CSx
SHP
CSx
CFBx
Figure 4. CDS Mode Input Circuit for CCD Signal
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Sample Hold (SH) Mode (AINx_SH_CDS = 1)
SH mode supports CCD and CMOS sensors. For the CCD sensor, the sensor signal pedestal level is clamped to
the VCLP level using an internal clamp circuit. SH samples only once during a pixel period. The SHD pulse is
used to sample the CCD signal data interval. After sampling, the SH circuit takes the difference of the data and
VCLP levels to extract the video information.
For the CMOS input, the input clamp function should be set according to the requirements. If the sensor output is
within the allowable input range, an ac-coupling capacitor for analog input may not be needed. When the sensor
signal is directly input to the AFE, the SH circuit requires a reference voltage to set the black level. To use VCLP
as a reference, SH_REFx_EN should be enabled and AINGNDx then opened or coupled to GND with a
capacitor. To use an external reference, it can be input to AINGNDx with sensor signals connected to AINx.
Figure 5 shows a diagram of the SH mode.
VCLP
OFDAC_x[7:0]
CLPDM
SHP_y
SH_REFx_EN
CLP_y
CLP_y
AINx
(1)
SHD
RCLP
Offset
DAC
CSx
AINx_POL
CFBx
CSx
+
VP
AINGNDx(1)
VN
CSx
SHD
CSx
CFBx
(1) Under some conditions, the sensor signal can be directly input to the AFE without requiring an external capacitor.
(2) In SH mode, the SHP clock should be programmed so that it does not overlap the SHD clock.
Figure 5. SH Mode Input Circuit for CCD or CMOS Signal
INPUT CLAMP AND SENSOR REFERENCE
The CCD output signal has a large dc offset that may exceed the input range of the AFE input circuit. Therefore,
this output signal is ac-coupled to the AFE through a capacitor, and the internal dc level is set to the clamp
voltage (VCLP) by an internal clamp circuit. The VSP5610/11/12 provide three modes for clamp operation: pixel
clamp, line clamp, and not clamped. These modes are shown in Table 4. The clamp mode can be set
independently for each channel by configuring the AINx_CLP_SEL register.
Table 4. Clamp Mode Selection
MODE SETTING
CLAMP MODE
20
CDS/SH
CLP_y (2)
CLPDM AND
SHP_y (2)
SH_REF_EN
Pixel clamp
0 (default)
CDS/SH
Active
Active
Off
Line clamp
1
CDS/SH
—
Active
Off
2
Only SH
—
—
On
3
Only SH
—
—
Off
Not clamped
(1)
(2)
AINx_CLP_SEL
CLAMP ACTIVE CONDITION AND SETTING
(1)
AINx_CLP_SEL (x = 1, 2, 3, and 4).
y = A and B.
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In pixel clamp mode, CLP_A/B is used for clamping. The input signal is clamped to VCLP via the CLP_A/B pulse
during each pixel period, as shown in Figure 6a. Because the ac-coupling capacitor is charged on a pixel-to-pixel
basis, the clamp level droop can be controlled by the clamp pulse width.
In line clamp mode, SHP_A/B is used for clamping when CLPDM is active, as shown in Figure 6b. The input
signal is clamped only in the CLPDM period within one line cycle of the sensor. The signal is clamped in this
method because the charge leaks the least from the coupling capacitor during the CLPDM period. Accordingly,
because there may be a large droop in the clamp level, this device does not support line clamp in the SH mode.
The not-clamped mode is mainly used in for a CMOS sensor input. If the sensor signal is directly connected to
the AFE, this mode should be configured without an ac-coupling capacitor at the input port. This mode has two
options to select a reference for the sensor black level: internal reference and external input. In the internal
reference option, the internal reference (VCLP) is used with AINx_CLP_SEL = 2. In the external input option, the
external input is used from AINGNDx with AINx_CLP_SEL = 3.
MCLK
MCLK
AINx
(1)
(1)
AINx
tFC_y
tCW_y
CLP_y
(2)
tRP_y
SHP_y
SHD_y
tPW_y
tRP_y
(2)
SHP_y
(2)
SHD_y
tPW_y
(2)
(2)
a) Pixel Clamp
b) Clamp During CLPDM Active
(1) x = AIN channel number, x = 1, 2, 3, and 4.
(2) y = Group code of sample pulse signals. When x = 1 or 2, y = A. When x = 3 or 4, y = B.
Figure 6. Input Clamp Function
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As shown in Figure 7, the internal VCLP node provides the clamp reference voltage. As for the clamp level, it is
possible to select three reference voltage modes by setting the AINx_REF_SEL register. The first mode provides
a fixed 2.2 V, the second mode provides selectable outputs (0.5 V, 1.1 V, 1.5 V, and 2.0 V) of an internal DAC,
and the third mode allows an external input from the REF_AIN pin to be used as the clamp reference. This
REF_AIN pin is bidirectional and also acts as an output of the internal DAC. Table 5 shows the relationship
between the register and clamp level. Table 6 shows the DAC configuration.
(1) If the sensor signal is directly input to the AFE, the enternal capacitor should not be connected.
Figure 7. VCLP Block Diagram
Table 5. Clamp Level Selection
MODE SETTING
AINx_REF_SEL[1:0] (1)
(1)
CLAMP LEVEL
0
2.2 V
1
VRINT
Reference DAC (0.5 V, 1.1 V, 1.5 V, and
2.0 V)
2
VREXT
REF_AIN external input
AINx_CLP_SEL (x = 1, 2, 3, and 4).
Table 6. VRINT Voltage Selection
22
SETTING CODE VRINT_SEL
REF DAC VRINT (V)
2
0.5
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3
1.1
0
1.5 (default)
1
2.0
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If line clamp mode is used, the CLPDM period should be configured by the internal registers. The CLPDM period
is determined with reference to the line cycle signal for the sensor (LS). Thus, the start and end of CLPDM are
each defined as the number of pixels from the LS falling edge. Because CLPDM is used as the clamp period, it
should be assigned for the interval of any dummy or optical black pixels. Figure 8 shows the relationship
between LS and CLPDM.
Dummy Pixels
Optical Black
Active Pixels
AINx
(External)
LS
(Internal)
DM_END
DM_STR
CLPDM
(Internal)
Clamp with CLP_y
Clamp with CLP_y
Clamp with SHP_y
Figure 8. Line Clamp Period Setting
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Pixel Clamp Period Setting
In pixel clamp mode, without CLPDM, the sensor signal is clamped with CLP_A and CLP_B pulses. CLP_A
corresponds to AIN1 and AIN2; CLP_B corresponds to AIN3 and AIN4. The start of these pulses is synchronized
with the SHP_y rising edge (where y = A or B). There are two options to configure the end position: first, to
automatically set the pulse width to 50% that of SHP_y; and second, to manually configure the end position
using an internal register. Figure 9 and Figure 10 illustrate the details of the clamp pulse function in automatic
and manual modes, respectively.
Automatic Mode (CLP_TF_AT_DIS = 0)
Figure 9 shows the automatic mode when CLP_TF_AT_DIS is '0'.
DLL Setting
Number
36
0
12
24
36
48
0
12
48
SHP_y_TF
tPW_Y
SHP_y_TR
SHP_y
tCW_y = tPW_Y/2
CLP_y
Figure 9. Automatic Mode
Manual Mode (CLP_TF_AT_DIS = 1)
Figure 10 shows the manual mode when CLP_TF_AT_DIS is '1'.
DLL Setting
Number
36
0
12
24
36
48
0
12
48
SHP_y_TF
SHP_y_TR
SHP_y
CLP_y
CLP_y_TF
Figure 10. Manual Mode
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In pixel clamp mode when CLPDM is active, the sensor signal is clamped with SHP_y. Therefore, the pixel clamp
operation is closely related with the status of CLPDM. The condition of CLPDM should be properly defined with
the internal registers. Because CLPDM is always high during a default condition after reset or power up, the
status of CLPDM should be defined according to this sequence. Furthermore, the CLPDM status should be
defined in the second step of the flowchart shown in Figure 11 for either configuration. All other user-dependent
settings, except XLSYNC_SEL and EN_OUT of the software reset sequence, are described in Figure 11.
(1) Internal registers: AINx_CLP_SEL = addresses 16 and 17; LINT = address 7; DM_STR = address 8; DM_END = address 9; and
EN_CLPDM = address 399, bit 1.
Figure 11. Configuration Sequence for Pixel Clamp
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ANALOG PROGRAMMABLE GAIN (APG)
The SH output can be amplified using programmable analog gain. This gain can be set from 0.5 V/V to 3.5 V/V
with a step size of 3/64 V/V.
The gain setting can be controlled by an internal register (APG_x). Equation 1 shows the relationship between
the setting code and gain. The gain of each of the four channels can be set independently using different
registers. Note that the black pixel level may possibly change as a result of the change in the gain; therefore, the
appropriate timing of the gain change should be used to avoid degradation in image quality. Figure 12 shows
analog gain as a function of gain control code in terms of V/V. Figure 13 shows the maximum allowed input
signal as a function of gain control code.
3
APG (V/V) =
(Code = 0 LSB to 63 LSB)
´ Code + 0.5
63
(1)
3.5
2
1.8
3
1.6
Input Range (V)
Gain (V/V)
2.5
2
1.5
1
1.4
1.2
1
0.8
0.6
0.4
0.5
0.2
0
0
0
8
16
24
32
40
48
0
64
56
8
16
24
32
40
48
56
64
Input Code for Analog Gain Control (0 LSB to 63 LSBs)
Input Code for Analog Gain Control (0 LSB to 63 LSBs)
Figure 12. Analog Gain vs Setting Code
Figure 13. Input Range vs Analog Gain Setting
Code
DIGITAL PROGRAMMABLE GAIN (DPG)
The VSP5610/11/12 provide a maximum digital gain of 2 V/V. The total gain is fixed by the combination of
CDS/SH analog gain (APG) and digital gain (DPG). DPG is controlled by an 8-bit internal register (DPG_x) that
can set the gain from 1 V/V to 2 V/V, as defined by Equation 2. This register is included in each of the four
channels, so the gain of each channel can be set independently.
Figure 14 shows the relationship between the digital gain and register code. Note that the default value is 1 V/V.
1
DPG (V/V) =
(Code = 0 LSB to 255 LSB)
´ Code + 1
256
(2)
2
1.9
Digital Gain (V/V)
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0
32
64
96
128
160
192
256
224
Input Code for Digital Gain Control (0 LSB to 255 LSBs)
Figure 14. Digital Gain Setting Code
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ADC
The ADC output format is selectable as twos complement or offset binary by configuring a register. Table 7
shows the relationship between register setting and condition.
Table 7. ADC Data Format Configuration
ADC_DAT_FRM
MODE
0 (default)
Twos complement
1
Offset binary
OFFSET DAC
The VSP5610/11/12 have an independent DAC in each channel for offset level correction of the input signal. The
correction range is ±250 mV and resolution is 8 bits. The DAC output voltage can be set by register settings.
Table 8 and Figure 15 show the relationship between the output and setting codes. The setting code is defined in
twos complement format. The DAC output offset voltage in millivolts as a function of the register setting is given
in Equation 3.
Table 8. Offset DAC Setting Code
(1)
SETTING CODE
OFDAC_x[7:0] (1)
OUTPUT (mV)
7Fh
248.05
7Eh
246.09
…
…
01h
1.95
00h
0
FFh
–1.95
…
…
81h
–248.05
80h
–250.00
× = 1, 2, 3, and 4.
250
DAC Output (mV) =
´ OFDAC_x[7:0]
128
where:
x = 1, 2, 3, and 4
(3)
300
DAC Output (mV)
200
100
0
-100
-200
-300
-128
-96
-64
-32
0
32
64
96
128
8-Bit DAC Code (LSB)
Figure 15. Offset DAC Setting Code vs Output Voltage
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TIMING GENERATOR (TG)
The image sensor timing generator (TG) is incorporated into these devices. The TG provides six signals that
function as slow transfer clocks and eight signals that function as fast transfer clocks. In addition, the fast clock
signals can also be used as slow clock signals. The TG signals are synchronized with LS (which is the image
sensor line cycle) and are completely controlled by the internal registers. Because the TG output is locked under
the default setting, EN_OUT (address 2, bit 10) should be set to '1' to enable the outputs.
LINE SYNCHRONOUS FUNCTION
The VSP5610/11/12 have two modes for synchronizing the sensor line cycle: internal line (Figure 16) and
external line syncronous mode (Figure 17). In internal line synchronous mode, the line cycle signal (LS) is
generated after a certain number of MCLK cycles that are counted by an internal counter (PIX_CNT). The
number of MCLK cycles is determined by the LINT[19:0] register; the counter clears after LS is generated. The
active LS period is equal to one MCLK cycle period.
MCLK
(External)
・・・・・
MCK
(Internal)
・・・・・
PIX_CNT[19:0]
(Internal)
LINT-3
LINT-2
LINT-1
LINT
0
1
2
・・・・・
LINT-3
LINT-2
LINT-1
LINT
0
1
3
0
1
tLINE
LS_INT
(Internal)
LS
(Internal)
Figure 16. Internal Line Synchronous Mode (XLSYNC_SEL = 1)
tXLS_ACT
XLSYNC
(External)
More Than 3 Clocks
XLSYNC_POL = 0 (Active High)
tXLS_H
MCLK
(External)
・・・・・
MCK
(Internal)
・・・・・
PIX_CNT[19:0]
(Internal)
LINT - 1
LINT
tXLS_S
tXLS_H
tXLS_S
LINT + 1
XLSYNC Mask Period
XLSYNC Unmask Period
XLSYNC Mask Period
LS_MSK
(Internal)
LS
(Internal)
Figure 17. External Line Synchronous Mode (XLSYNC_SEL = 0, default)
Table 9. Timing Requirements for Figure 16 and Figure 17
MIN
TYP
MAX
tLINE
Line cycle period setting
PARAMETER
XLSYNC = 1
3
LINT + 1
220 – 1
tXLS_ACT
XLSYNC active period
XLSYNC = 0
3
Clocks
tXLS_S
XLSYNC setup to MCLK
XLSYNC = 0
10
ns
tXLS_H
XLSYNC hold to MCLK
XLSYNC = 0
10
ns
28
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TEST CONDITION
UNIT
Clocks
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The other mode is the external line synchronous mode which requires an external signal (XLSYNC). In this
mode, if the logic circuit detects an active XLSYNC period for more than three MCLK cycles, the internal line
synchronous signal (LS) is generated. This mode has a function that mask XLSYNC in order to avoid noise
interference. The duration of the XLSYNC mask can be set by the LINT[19:0] register, which is also used in the
internal line synchronous mode.
The two line synchronous modes and the polarity can be selected by the XLSYNC_SEL and XLSYNC_POL
registers, respectively. The default settings are external mode and active high polarity. XLSYNC can be used to
output some internal signals. Table 10 shows the register settings required to select the desired output signals.
PIX_CNT can be automatically reset by LS_CNT_RST (which is an internal register). Before performing this
function, a software reset must be executed in order set RST_ALL to '1'. If LS_CNT_RST is set to '1' after a
software reset, the pixel counter is then held at '0'. To make the counter active, LS_CNT_RST should return to
'0'.
Table 10. XLSYNC Output Signal (XLSYNC_SEL = 1)
REGISTER SETTING
XLSYNC_OUT
OUTPUT SIGNAL
0
LS
1
CLPDM
2
Reserved
3
Reserved
SLOW TRANSFER CLOCK SETTING (XST, XSHn, XCLR)
XST, XSHn (where n = 1 to 4), and XCLR are slow transfer clocks that can be configured by setting the initial
polarity and toggle points. As shown in Table 11, the predetermined number of toggle points is different for each
signal. Because the two toggles generate one pulse, the number of pulses is half the number of toggles.
Table 11. Toggle Number and Generated Pulse
SIGNAL
TOGGLE
PULSE
XST
8
4
XSHn
16
8
XCLR
48
24
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Each toggle position is defined by a register that is exclusive for each signal. The toggle position is synchronized
with LS and the gap between the toggle position and the LS falling edge. The LS falling edge is defined in terms
of tMCLK, the cycle period of MCLK. This gap is set by register settings and is defined by Equation 4:
t = (Xn_T(k) + 1) × tMCLK
where:
n = ST, SHn, CLR
k = 0 to 7 (XST); k = 0 to 15 (XSHn); k = 0 to 47 (XCLR)
Xn_T(k) is less than LINT and is the register value of the toggle setting
(4)
The toggle for each signal can be disabled with register settings. To make the toggle active, Xn_TGL_EN should
be set to '1'. However, because XST shares a pin with GPIO3, pin function should be configured with the
GPIO3_XST_SEL register. Figure 18 shows the configuration regarding the slow transfer clock.
1 Line Cycle (Max = MCLK
2 )
LS
(Internal)
XST Configuration
XST_T7 + 1
XST_T6 + 1
・・
Toggle
Setting
XST_T1 + 1
XST_T0 + 1
XST_P = 0 (Initial Polarity = Low)
XST
(Output)
・・・
XST_P = 1 (Initial Polarity = High)
XST
(Output)
・・・
XSHn Configuration (n = 1 to 4)
・・
Toggle
Setting
XSHn_T15 + 1
XSHn_T2 + 1
XSHn_T1 + 1
XSHn_T0 + 1
XSHn_P = 0 (Initial Polarity = Low)
XSHn
(Output)
・・・
XSHn_P = 1 (Initial Polarity = High)
XSHn
(Output)
・・・
XCLR Configuration
・・
Toggle
Setting
XCLR_T47 + 1
XCLR_T3 + 1
XCLR_T1 + 1
XCLR_T0 + 1
XCLR_P = 0 ( Initial Polarity = Low)
XCLR
(Output)
・・・
XCLR_P = 1 (Initial Polarity = High)
XCLR
(Output)
・・・
(1) If Xn_Tn is set to '0', the toggle position is ignored (except for Xn_T0).
(2) The period between the toggle position and LS falling edge = (Xn_T(k) + 1) × tMCLK.
(3) The following requirement must be satisfied: Xn_T(k) < Xn_T(k + 1).
(4) The signal is set to the desired polarity settings at the falling edge of LS.
Figure 18. Slow Transfer Gate Signal Setting for XST, XSHn, and XCLR
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FAST TRANSFER CLOCK PULSE SETTING
XP1/2, X1L, X2L, XRS, XCP, and XP3/4 are fast transfer clock signals with rising and falling edges that are
configurable via register settings. Figure 19 shows the block diagram of the fast clock configuration. In Figure 19,
the DLL Tap Selector is used to select both the rising and the falling edges of each signal from among 48 tap
positions.
The XP2 clock signal is an inverse of XP1 and shares rising and falling edge settings. Similarly, XP4 is an
inverse of XP3 and likewise shares rising and falling edge settings. The other signals have individual
configuration registers for setting the position of both edges.
In addition, it is possible to change the clock rate of each signal with register settings. The clock rate is based on
the frequency of MCLK. XP1 and XP2 can select x1, x2, or x4 modes with common settings. XP3 and XP4 can
also select x1, x2, or x4 modes with common settings. The other signals can choose between the x1 and x2 rate
settings.
Note that two independent sets of registers are available to set the clock rate, the clock rising edge, and the
clock falling edge for operation in x1-mode and x2-mode.
DLL
48 Taps
DLL Tap Selector
x1
x2
x4
x1 x1
x2 x2
x1
x2
x1
x2
MCLK
x1
x2
x4
XP1
XP2
X1L
X2L
XRS
XCP
XP3
XP4
Timing Generator
Figure 19. Fast Transfer Clock Pulse Generator
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Fast Transfer Clock Pulse Timing
This section describes the timing of the fast transfer clock pulse for XRS (Figure 20), XCP (Figure 21), XP1 and
XP2 (Figure 22), XP3 and XP4 (Figure 23), and X1L and X2L (Figure 24).
tMCLK
MCLK
(External)
tMCKD
MCK
(Internal)
x1 Mode
tTR_RS
tRS
tTF_RS
tW_RS
XRS
(Output)
x2 Mode
tTR_RS
tRS
tTF_RS
tW_RS
XRS
(Output)
Figure 20. XRS Fast Transfer Clock Pulse Setting
Table 12. Timing Requirements for Figure 20
PARAMETER
fMCLK
MCLK frequency
tMCLK
MCLK period
tMCKD
MCLK to MCK delay
tRS
tTR_RS
TEST CONDITIONS
XRS period
XRS rising edge delay from MCK
tTF_RS
XRS falling edge delay from MCK
tW_RS
XRS pulse width
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MAX
UNIT
VSP5610
MIN
1
TYP
11.66
MHz
VSP5611
1
16.66
MHz
VSP5612
1
23.33
MHz
1/fMCLK
ns
2
ns
x1 mode
tMCLK
ns
x2 mode
tMCLK × 1/2
ns
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
x1 mode
2
tMCLK – 2
ns
x2 mode
2
tMCLK × 1/2 – 2
ns
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tMCLK
MCLK
(External)
tMCKD
MCK
(Internal)
x1 Mode
tTR_CP
tTF_CP
tCP
tW_CP
XCP
(Output)
x2 Mode
tTR_CP
tTF_CP
tRS
tW_CP
XCP
(Output)
Figure 21. XCP Fast Transfer Clock Pulse Setting
Table 13. Timing Requirements for Figure 21
PARAMETER
fMCLK
MCLK frequency
tMCLK
MCLK period
tMCKD
MCLK to MCK delay
tCP
tTR_CP
TEST CONDITIONS
XCP period
XCP rising edge delay from MCK
tTF_CP
XCP falling edge delay from MCK
tW_CP
XCP pulse width
MAX
UNIT
VSP5610
MIN
1
TYP
11.66
MHz
VSP5611
1
16.66
MHz
VSP5612
1
23.33
MHz
1/fMCLK
ns
2
ns
x1 mode
tMCLK
ns
x2 mode
tMCLK × 1/2
ns
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
x1 mode
2
tMCLK – 2
ns
x2 mode
2
tMCLK × 1/2 – 2
ns
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tMCLK
MCLK
(External)
tMCKD
MCK
(Internal)
x1 Mode
tTR_P1_x1
tP1
tTF_P1_x1
tW_P1
XP1
(Output)
XP2
(Output)
x2 Mode
tTR_P1_x2
tP1
tTF_P1_x2
tW_P1
XP1
(Output)
XP2
(Output)
x4 Mode
tTR_P1_x4
tP1
tTF_P1_x4
tW_P1
XP1
(Output)
XP2
(Output)
Figure 22. XP1 and XP2 Fast Transfer Clock Pulse Setting
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Table 14. Timing Requirements for Figure 22
PARAMETER
fMCLK
TEST CONDITIONS
MCLK frequency
tMCLK
MCLK period
tMCKD
MCLK to MCK delay
tPn
XP1, XP2 period
tTR_P_x1
tTR_P_x2
XP1, XP2 rising edge delay from MCK
tTR_P_x3
tTF_P_x1
tTF_P_x2
XP1, XP2 falling edge delay from MCK
tTF_P_x3
tW_P1
XP1, XP2 pulse width
MAX
UNIT
VSP5610
MIN
1
TYP
11.66
MHz
VSP5611
1
16.66
MHz
VSP5612
1
23.33
MHz
1/fMCLK
ns
2
ns
x1 mode
tMCLK
ns
x2 mode
tMCLK × 1/2
ns
x4 mode
tMCLK × 1/4
ns
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
x4 mode
0
tMCLK × 11/12
ns
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
x4 mode
0
tMCLK × 11/12
ns
x1 mode
2
tMCLK – 2
ns
x2 mode
2
tMCLK × 1/2 – 2
ns
x4 mode
2
tMCLK × 1/4 – 2
ns
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tMCLK
MCLK
(External)
tMCKD
MCK
(Internal)
x1 Mode
tTR_P3_x1
tP3
tTF_P3_x1
tW_P3
XP3
(Output)
XP4
(Output)
x2 Mode
tTR_P3_x2
tP3
tTF_P3_x2
tW_P3
XP3
(Output)
XP4
(Output)
x4 Mode
tTR_P3_x4
tP3
tTF_P3_x4
tW_P3
XP3
(Output)
XP4
(Output)
Figure 23. XP3 and XP4 Fast Transfer Clock Pulse Setting
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Table 15. Timing Requirements for Figure 23
PARAMETER
fMCLK
TEST CONDITIONS
MCLK frequency
tMCLK
MCLK period
tMCKD
MCLK to MCK delay
tP3
XP3, XP4 period
tTR_P3_x1
tTR_P3_x2
XP3, XP4 rising edge delay from MCK
tTR_P3_x3
tTF_P3_x1
tTF_P3_x2
XP3, XP4 falling edge delay from MCK
tTF_P3_x3
tW_P3
XP3, XP4 pulse width
MAX
UNIT
VSP5610
MIN
1
TYP
11.66
MHz
VSP5611
1
16.66
MHz
VSP5612
1
23.33
MHz
1/fMCLK
ns
2
ns
x1 mode
tMCLK
ns
x2 mode
tMCLK × 1/2
ns
x4 mode
tMCLK × 1/4
ns
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
x4 mode
0
tMCLK × 11/12
ns
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
x4 mode
0
tMCLK × 11/12
ns
x1 mode
2
tMCLK – 2
ns
x2 mode
2
tMCLK × 1/2 – 2
ns
x4 mode
2
tMCLK × 1/4 – 2
ns
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tMCLK
MCLK
(External)
tMCKD
MCK
(Internal)
tTR_Ln
x1 Mode
tLn
tTF_Ln
tW_Ln
XnL (n = 1, 2)
(Output)
tTR_Ln
x2 Mode
tLn
tTF_Ln
tW_Ln
XnL (n = 1, 2)
(Output)
Figure 24. X1L and X2L Fast Transfer Clock Pulse Setting
Table 16. Timing Requirements for Figure 24
PARAMETER
TEST CONDITIONS
MAX
UNIT
VSP5610
MIN
1
TYP
11.66
MHz
VSP5611
1
16.66
MHz
VSP5612
1
23.33
MHz
fMCLK
MCLK frequency
tMCLK
MCLK period
tMCKD
MCLK to MCK delay
tLn
XLn period
(n = 1,2)
tTR_Ln
XLn rising edge delay from MCK
(n = 1,2)
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
tTF_Ln
XLn falling edge delay from MCK
(n = 1,2)
x1 mode
0
tMCLK × 47/48
ns
x2 mode
0
tMCLK × 23/24
ns
XLn pulse width
(n = 1,2)
x1 mode
2
tMCLK – 2
ns
x2 mode
2
tMCLK × 1/2 – 2
ns
tW_Ln
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1/fMCLK
ns
2
ns
x1 mode
tMCLK
ns
x2 mode
tMCLK × 1/2
ns
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SERIAL INTERFACE
All device functions and settings are controlled through the serial interface. The serial interface consists of three
signals (SCLK, SEN, and SDI) for register writing, and a fourth signal (SDO) for readback. SDO shares the
terminal with the GPIO signal; thus, a register setting is required to activate the SDO function. Other signals are
assigned to individual terminals.
Serial data are composed of 30 bits total, as shown in Figure 25. 10 bits are assigned for the register address
and 20 bits for register data. The input serial data at SDI are sequentially stored in a shift register at the SCLK
rising edge. Data shift operation is performed at the SCLK rising edges with SEN low. All 30 input data bits are
loaded to a parallel latch in an internal register at the rising edge of SEN.
This device has two modes: read and write. The mode selection can be made via the SPL_RW internal register,
located at bit 0 of address 0. SPL_RW = 0 implies a write mode and SPL_RW = 1 implies read mode.
10-Bit Address
A9
A8
¼
A1
20-Bit Data
A0
D19
D18
¼
D1
MSB
D0
LSB
Figure 25. Serial I/F Data Format
WRITE MODE (SPI_RW = 0, Default)
Normally, one serial interface command is sent by one address and data combination. The address should be
sent MSB first. Data are stored into the respective register, as indicated by the address. If the serial data at the
end of the data stream are less than 30 bits, the last incomplete serial data are discarded. Figure 26 shows the
SPI signal flow while in write mode.
SEN
SCLK
SDI
XX
A[9:0]
D[19:0]
XX
A[9:0]
Figure 26. SPI Signal Flow of Write Mode
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READ MODE (SPI_RW = 1)
In read mode, two types of connections are possible between the AFE and external systems such as an ASIC or
CPU. One connection is the four-wire connection in which the SDI and SDO pins are separately connected to the
system as shown in Figure 27a.
The other connection is a three-wire connection in which only the SDI pin is connected to the bidirectional I/O
port of the external system, as shown in Figure 27b. In this case, SDI_BUFF_CTRL should be set to '1' to create
an SPI bidirectional port. The bit flow of the four-wire connection is shown in Figure 28. The bit flow of the
three-wire connection is shown in Figure 29. As shown in Figure 29, SDI changes from an input to an output at
the SCLK falling edge after the end of the A[9:0] input. Because the SDI port is always in pull down mode, the
external pull down resistance is unnecessary.
Device
ASIC/CPU
SEN
SEN
SCLK
SCLK
Device
SEN
SEN
SCLK
SCLK
SDI
ASIC/CPU
SDI
SDI
SDIO
SDO
SDO
SDO
SDO_EN
SDO_EN
a) Four-Wire Connection
SDI Input Port: SDI_BUFF_CTRL = 0
b) Three-Wire Connection
SDI Bidirectional Port: SDI_BUFF_CTRL = 1
Figure 27. SPI Connection Between AFE and System
SEN
SCLK
SDI
XX
A[9:0], Input
Hi-Z
SDO
D[19:0], Input
XX
A[9:0], Input
Hi-Z
D[19:0], Output
SDO_EN
(Internal)
20 SCLK Cycles
for 20-Bit Data
Figure 28. SPI Signal Flow of Read Mode for Four-Wire Connection
SEN
SCLK
SDI/SDO
XX
A[9:0], Input
D[19:0], Input
XX
A[9:0], Input
SDO_EN
(Internal)
20 SCLK Cycles
for 20-Bit Data
Figure 29. SPI Signal Flow of Read Mode for Three-Wire Connection
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
VSP5610RSHR
ACTIVE
VQFN
RSH
56
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
VSP
5610
VSP5611RSHR
ACTIVE
VQFN
RSH
56
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
VSP
5611
VSP5612RSHR
ACTIVE
VQFN
RSH
56
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
VSP
5612
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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