Product
Folder
Sample &
Buy
Tools &
Software
Technical
Documents
Support &
Community
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
RF430FRL15xH NFC ISO 15693 Sensor Transponder
1 Device Overview
1.1
Features
1
• ISO/IEC 15693, ISO/IEC 18000-3 (Mode 1)
Compliant RF Interface
• Power Supply System With Either Battery or
13.56-MHz H-Field Supply
• 14-Bit Sigma-Delta Analog-to-Digital Converter
(ADC)
• Internal Temperature Sensor
• Resistive Sensor Bias Interface
• CRC16 CCITT Generator
• MSP430™ Mixed-Signal Microcontroller
– 2KB of FRAM
– 4KB of SRAM
– 8KB of ROM
– Supply Voltage Range: 1.45 V to 1.65 V
– Low Power Consumption
• Active Mode (AM): 140 µA/MHz (1.5 V)
• Standby Mode (LPM3): 16 µA
– 16-Bit RISC Architecture
– Up to 2-MHz CPU System Clock
– Compact Clock System
• 4-MHz High-Frequency Clock
1.2
•
256-kHz Internal Low-Frequency Clock
Source
• External Clock Input
– 16-Bit Timer_A With Three Capture/Compare
Registers
– LV Port Logic
• VOL Lower Than 0.15 V at 400 µA
• VOH Higher Than (VDDB – 0.15 V) at 400 µA
• Timer_A PWM Signal Available on All Ports
– eUSCI_B Module Supports 3-Wire and 4-Wire
SPI and I2C
– 32-Bit Watchdog Timer (WDT_A)
– ROM Development Mode (Map ROM Addresses
to SRAM to Enable Firmware Development)
– Full 4-Wire JTAG Debug Interface
• For Complete Module Descriptions, See the
RF430FRL15xH Family Technical Reference
Manual (SLAU506)
• For Application Operation and Programming, See
the RF430FRL15xH Firmware User's Guide
(SLAU603)
Applications
Industrial Wireless Sensors
1.3
•
•
Medical Wireless Sensors
Description
The RF430FRL15xH device is a 13.56-MHz transponder chip with a programmable 16-bit MSP430™ lowpower microcontroller. The device features embedded universal FRAM nonvolatile memory for storage of
program code or user data such as calibration and measurement data. The RF430FRL15xH supports
communication, parameter setting, and configuration through the ISO/IEC 15693, ISO/IEC 18000-3
compliant RFID interface and the SPI or I2C interface. Sensor measurements are supported by the
internal temperature sensor and the onboard 14-bit sigma-delta analog-to-digital converter (ADC), and
digital sensors can be connected through SPI or I2C.
The RF430FRL15xH device is optimized for operation in fully passive (battery-less) or single-cell batterypowered (semi-active) mode to achieve extended battery life in portable and wireless sensing applications.
FRAM is a nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the
stability and reliability of flash, all at lower total power consumption.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
Device Information (1)
PACKAGE
BODY SIZE (2)
RF430FRL152H
VQFN (24)
4 mm x 4 mm
RF430FRL153H
VQFN (24)
4 mm x 4 mm
RF430FRL154H
VQFN (24)
4 mm x 4 mm
PART NUMBER
(1)
(2)
1.4
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI web site at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Functional Block Diagram
Figure 1-1 shows the block diagram of the RF430FRL15xH device.
RST/NMI
P1.0 to P1.7
Reset
Int-Logic
IO Port
8 I/Os
with
interrupt
capability
VDDB VSS VDDH
LF-OSC
VDDSW
HF-OSC
CLKIN
Clock
System
ACLK
8KB
ROM
4KB
RAM
2KB
FRAM
CRC
16 bit
SMCLK
Power
Supply
System
VDD2X
VDDD
CP1
CP2
MCLK
MAB
CPU and
Working
Registers
TMS, TCK,
TDI, TDO
ANT2
4W-JTAG
Debug
support
eUSCI_B0
Timer_A
SPI
I2C
3 CC
Registers
Watchdog
WDTA
32/16 Bit
14-Bit
SigmaDelta
ADC
ISO
15693
Decode
and
Encode
ISO
15693
Analog
Front End
CRES
LRES
ANT1
ADC0/ADC1/ADC2
TEMP1/TEMP2
Figure 1-1. Functional Block Diagram
2
Device Overview
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Table of Contents
1
2
3
4
Device Overview ......................................... 1
5.18
RFPMM, Power Supply Switch
1.1
Features .............................................. 1
5.19
RFPMM, Bandgap Reference ....................... 19
1.2
Applications ........................................... 1
5.20
RFPMM, Voltage Doubler ........................... 19
1.3
Description ............................................ 1
5.21
RFPMM, Voltage Supervision
1.4
Functional Block Diagram ............................ 2
5.22
SD14, Performance ................................. 20
Revision History ......................................... 4
Device Comparison ..................................... 5
Terminal Configuration and Functions .............. 6
5.23
SVSS Generator
5.24
Thermistor Bias Generator .......................... 21
5.25
5.26
Temperature Sensor ................................ 21
RF13M, Power Supply and Recommended
Operating Conditions ................................ 21
5.27
RF13M, ISO/IEC 15693 ASK Demodulator ......... 21
5.28
RF13M, ISO/IEC 15693 Compliant Load Modulator 21
.......................................... 6
4.2
Signal Descriptions ................................... 7
4.3
Pin Multiplexing ....................................... 9
4.4
Connections for Unused Pins ........................ 9
Specifications ........................................... 10
5.1
Absolute Maximum Ratings ........................ 10
5.2
ESD Ratings ........................................ 10
5.3
Recommended Operating Conditions ............... 10
4.1
5
5.4
5.5
5.6
Pin Diagram
Recommended Operating Conditions, Resonant
Circuit................................................ 11
Active Mode Supply Current Into VDDB Excluding
External Current .................................... 11
Low-Power Mode Supply Current (Into VDDB)
Excluding External Current.......................... 11
5.7
Digital I/Os (P1, RST/NMI) .......................... 12
5.8
.......
......
Wake-Up From Low-Power Modes .................
Timer_A .............................................
5.9
5.10
5.11
5.12
High-Frequency Oscillator (4 MHz), HFOSC
12
Low-Frequency Oscillator (256 kHz), LFOSC
12
6
13
13
eUSCI (SPI Master Mode) Recommended
Operating Conditions ................................ 14
5.13
eUSCI (SPI Master Mode) .......................... 14
5.14
eUSCI (SPI Slave Mode)
5.15
eUSCI (I2C Mode) ................................... 18
5.16
FRAM................................................ 18
5.17
JTAG ................................................ 18
...........................
16
9
......................
....................................
19
19
20
Detailed Description ................................... 22
.................................................
6.1
CPU
6.2
Instruction Set ....................................... 22
6.3
Operating Modes .................................... 23
6.4
Interrupt Vector Addresses.......................... 24
6.5
Memory .............................................. 26
..........................................
6.7
Port Schematics .....................................
6.8
Device Descriptors (TLV) ...........................
Applications, Implementation, and Layout .......
Device and Documentation Support ...............
8.1
Device Support ......................................
8.2
Documentation Support .............................
8.3
Related Links ........................................
8.4
Community Resources ..............................
8.5
Trademarks..........................................
8.6
Electrostatic Discharge Caution .....................
8.7
Glossary .............................................
6.6
7
8
.....................
Peripherals
22
27
33
41
42
43
43
44
44
45
45
45
45
Mechanical Packaging and Orderable
Information .............................................. 45
9.1
Packaging Information
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
..............................
Table of Contents
45
3
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from November 13, 2014 to December 8, 2014
•
•
•
•
4
Page
Corrected all instances of the title of the RF430FRL15xH Family Technical Reference Manual .......................... 1
Corrected all instances of the title of the RF430FRL15xH Firmware User's Guide ......................................... 1
Moved Tstg to Absolute Maximum Ratings table ................................................................................ 10
Changed title of Section 5.2 to ESD Ratings .................................................................................... 10
Revision History
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison (1)
(1)
Device
FRAM
(KB)
SRAM
(KB)
Timer
13.56-MHz
ISO/IEC 15693
Front End
eUSCI_B
SD14
RF430FRL152H
2
4
Yes
Yes
Yes
Yes
RF430FRL153H
2
4
Yes
Yes
No
Yes
RF430FRL154H
2
4
Yes
Yes
Yes
No
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9,
or see the TI web site at www.ti.com.
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Device Comparison
5
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagram
TMS/P1.7/TA0.1/TA0.0/CCI0.2
TDI/P1.5/TA0.2/MCLK/CCI0.1
TDO/P1.6/TA0.0/TA0.2/CCI0.2
VDDH
TCK/P1.4/TA0.1/SMCLK/CCI0.1
VDDD
Figure 4-1 shows the pin assignments on the 24-pin RGE package.
24 23 22 21 20 19
ADC2/TEMP2
2
17
ADC1/TEMP1
VDDSW
3
16
TST1
VDDB
4
15
SVSS
CP1
5
14
TST2
CP2
6
13
ADC0
P1.0/SPI_SIMO/SDA/SMCLK/TA0.1/CCI0.0
9 10 11 12
RST/NMI
8
P1.1/SPI_SOMI/SCL/ACLK/TA0.2/CCI0.0
7
P1.2/SPI_CLK/MCLK/TA0.0
18
ANT2
VDD2X
1
P1.3/SPI_STE/TA0.2/ACLK/TA0CLK
ANT1
VSS
Exposed die
attached pad
Figure 4-1. 24-Pin RGE Package (Top View)
6
Terminal Configuration and Functions
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
4.2
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Signal Descriptions
Table 4-1 describes the signals.
Table 4-1. Signal Descriptions
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
ANT1
1
I
Antenna input 1
ANT2
2
I
Antenna input 2
VDDSW
3
Switched supply voltage
VDDB
4
Battery supply voltage
CP1
5
Charge pump flying cap terminal 1
CP2
6
Charge pump flying cap terminal 2
VDD2X
7
Voltage doubler output
P1.3
General-purpose digital I/O
SPI_STE
TA0.2
SPI slave transmit enable
8
I/O
Timer_A TA0 OUT2 output
ACLK
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
TA0CLK
Timer_A TA0 clock signal TA0CLK input
P1.2
General-purpose digital I/O
SPI_CLK
9
I/O
SPI clock
MCLK
MCLK output
TA0.0
Timer_A TA0 OUT0 output
RST/NMI
10
I
Reset input active low
Non-maskable interrupt input
P1.1
General-purpose digital I/O
SPI_SOMI
SPI slave out master in
SCL
11
I/O
I2C clock
ACLK
ACLK output (divided by 1, 2, 4, or 8 )
TA0.2
Timer_A TA0 OUT2 output
CCI0.0
Timer_A TA0 CCR0 capture: CCI0B input, compare
P1.0
General-purpose digital I/O
SPI_SIMO
SPI slave in master out
SDA
12
I/O
I2C data
SMCLK
SMCLK output
TA0.1
Timer0_A3 OUT1 output
CCI0.0
Timer_A TA0 CCR0 capture: CCI0A input, compare
ADC0
13
TST2
14
Internal; connect to GND
SVSS
15
Sensor reference potential
TST1
16
Internal; connect to GND
ADC1 / TEMP1
17
ADC input pin 1 / Resistive bias pin 1
ADC2 / TEMP2
18
ADC input pin 2 / Resistive bias pin 2
(1)
I
ADC input pin 0
I = input, O = output
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Copyright © 2012–2014, Texas Instruments Incorporated
7
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
I/O (1)
TMS
DESCRIPTION
JTAG test mode select
P1.7
General-purpose digital I/O
19
TA0.1
I/O
Timer_A TA0 OUT1 output
TA0.0
Timer_A TA0 OUT0 output
CCI0.2
Timer_A TA0 CCR2 capture: CCI2B input, compare
TDO
JTAG test data output
P1.6
General-purpose digital I/O
20
TA0.0
I/O
Timer_A TA0 OUT0 output
TA0.2
Timer_A TA0 OUT2 output
CCI0.2
Timer_A TA0 CCR2 capture: CCI2A input, compare
TDI
JTAG test data input
P1.5
General-purpose digital I/O
21
TA0.2
I/O
Timer_A TA0 OUT2 output
MCLK
MCLK output
CCI0.1
Timer_A TA0 CCR1 capture: CCI1B input, compare
TCK
JTAG test clock
P1.4
General-purpose digital I/O
TA0.1
22
I/O
Timer_A TA0 OUT1 output
SMCLK
SMCLK output
CCI0.1
Timer_A TA0 CCR1 capture: CCI1A input, compare
CLKIN
External clock input pin
VDDH
23
VDDD
24
VSS
(2)
8
Pad
O
Rectified voltage from RF-AFE
Digital supply voltage
Ground reference, bonded to exposed pad (2)
VSS combines both digital ground (DVSS) and analog ground (AVSS)
Terminal Configuration and Functions
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
4.3
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Pin Multiplexing
The GPIO port pins are multiplexed with other functions including analog peripherals and serial
communication modules. The pin functions are selected by a combination of register values and device
modes. For schematics of the port pins and details of the multiplexing for each, refer to Section 6.7.
4.4
Connections for Unused Pins
The correct termination of all unused pins is listed in Table 4-2.
Table 4-2. Connection of Unused Pins
Pin
Potential
Comment
TDI/TMS/TCK
Open
When used for JTAG function
RST/NMI
VCC or VSS
10-nF capacitor to GND/VSS
Px.0 to Px.7
Open
Set to port function, output direction
TDO
Open
Convention: leave TDO terminal as JTAG function
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Copyright © 2012–2014, Texas Instruments Incorporated
9
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
5 Specifications
Absolute Maximum Ratings (1)
5.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN
MAX
UNIT
Voltage applied at VDDB referenced to VSS (VAMR)
-0.3
1.65
V
Voltage applied at VANT referenced to VSS (VAMR)
-0.3
3.6
V
Voltage applied to any pin (references to VSS)
-0.3
VDDB + 0.3
Diode current at any device pin (2)
±2
Current derating factor when I/O ports are switched in parallel electrically and logically (3)
0.9
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
(5)
(6)
-40
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are referenced to VSS.
The diode current increases to ±4.5 mA when two pins are connected, it increases to ±6.75 mA when three pins are connected, and so
on.
Soldering during board manufacturing must follow the current JEDEC J-STD-020 specification with peak reflow temperatures not higher
than classified on the device label on the shipping boxes or reels. If hand soldering is required for application prototyping, peak
temperature must not exceed 250°C for a total of 5 minutes for any single device.
Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, Tstg.
Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
5.2
ESD Ratings
Electrostatic discharge (ESD)
performance
VESD
(1)
(2)
(4) (5) (6)
V
mA
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1) (2)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Low leakage pin: ADC0 has reduced ESD tolerance of ±500 V HBM.
5.3
Recommended Operating Conditions
Typical data are based on VDDB = 1.5 V, TA = 25°C (unless otherwise noted)
MIN
VDDB
Supply voltage during program execution
VSS
Supply voltage (GND reference)
TA
Operating free-air temperature
CVDDB
Capacitor on VDDB
(1)
CVDDSW
Capacitor on VDDSW
CFLY
Charge pump capacitor between CP1 and CP2.
Recommended ratio between CFLY and CVDD2X is ≥ 1:10.
CVDD2X
Capacitor on VDD2x.
Recommended ratio between CFLY and CVDD2X is ≥ 1:10. (1)
Capacitor on VDDD
Capacitor between SVSS and VSS
System frequency
fCLKIN
External clock input frequency
(3)
10
UNIT
1.65
V
70
°C
(1)
V
100
nF
2.2
µF
10
nF
100
nF
1
µF
1
µF
(2) (3)
fSYSTEM
(1)
(2)
(1)
(1)
CSVSS
MAX
0
0
(1)
CVDDD
NOM
1.45
2
32
MHz
kHz
Low equivalent series resistance (ESR) capacitor
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Specifications
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
5.4
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Recommended Operating Conditions, Resonant Circuit
MIN
fc
Carrier frequency
VANT_peak
Antenna input voltage
Z
Impedance of LC circuit
LRES
Coil inductance
CRES
Resonance capacitance
QT
Tank quality factor
(1)
NOM
MAX
UNIT
13.56
MHz
3.6
6.5
V
15.5
kΩ
2.66
µH
(1)
pF
51.8 – CIN
30
See the RF13M parameter section.
5.5
Active Mode Supply Current Into VDDB Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
Frequency (fMCLK = fSMCLK)
EXECUTION
MEMORY
PARAMETER
VDDB
1 MHz
TYP
(2)
FRAM
IAM, RAM (2)
IAM, ROM (2)
IAM,
(1)
(2)
2 MHz
MAX
TYP
UNIT
MAX
FRAM
1.5 V
330
420
480
580
µA
RAM
1.5 V
220
300
250
320
µA
ROM
1.5 V
220
300
230
300
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
fACLK = 256 kHz, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
5.6
Low-Power Mode Supply Current (Into VDDB) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VDDB
0ºC
20ºC
TYP
MAX
TYP
45ºC
MAX
TYP
70ºC
MAX
TYP
MAX
UNIT
ILPM0
(2)
fMCLK = off, fSMCLK =
1 MHz, fACLK = 32 kHz,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
1.5 V
170
230
190
210
260
340
µA
ILPM3
(3)
fMCLK = fSMCLK = off,
fACLK = 16 kHz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
1.5 V
12
20
13
16
25
65
µA
ILPM4
(4)
fMCLK = fSMCLK = fACLK =
0 Hz
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
1.5 V
11
16
12
15
24
60
µA
(1)
(2)
(3)
(4)
Including current for WDT clocked by ACLK.
CSS: SELM=SELS=HF_CLK, SELA=LF_CLK, DIVM=/2 (2MHz), DIVS=/4 (1MHz), DIVA=/8 (32kHz)
SD14: reset values
RFPMM: battery switch on (EN_BATSWITCH=1)
CSS: SELM=HF_CLK, SELS=SELA=LF_CLK, DIVM=/2 (2MHz), DIVS=/32 (8kHz), DIVA=/16 (16kHz)
SD14: reset values
RFPMM: EN_BATSWITCH=1(battery switch enabled)
CSS: SELM=HF_CLK, SELS=SELA=LF_CLK, DIVM=/2 (2MHz), DIVS=/32 (8kHz), DIVA=/16 (16kHz)
SD14: reset values
RFPMM: EN_BATSWITCH=1(battery switch enabled)
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Specifications
11
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
5.7
www.ti.com
Digital I/Os (P1, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
High-level output voltage
VOL
Low-level output voltage
VDDB = 1.5 V, IOH = -400 µA (1) for port P1
VDDB = 1.5 V, IOL = 400 µA
(2)
MIN
TYP
MAX
VDDB
– 0.15
UNIT
V
for port P1
0.15
0.7 ×
VDDB
V
VIH
High-level input voltage
VDDB = 1.5 V
VIL
Low-level input voltage
VDDB = 1.5 V
IOH
High-level output current
VDDB = 1.45 V to 1.65 V for port P1
IOL
Low-level output current
VDDB = 1.45 V to 1.65 V for port P1
ILKG
High-impedance leakage current
VDDB = 1.45 V to 1.65 V
tINT
External interrupt timing (3)
P1.x, VDDB = 1.45 V to 1.65 V
RPULL
Pullup or pulldown resistor
VDDB=1.5 V, For pullup: VIN = VSS,
For pulldown: VIN = VDDB for port P1
RRST
Pullup on RST/NMI
REXT
External pullup resistor on RST
terminal (optional)
47
kΩ
CEXT
External capacitor on RST terminal
10
nF
(1)
(2)
(3)
V
0.3 ×
VDDB
-400
V
µA
-100
400
µA
100
nA
200
ns
30
35
40
kΩ
30
35
40
kΩ
The maximum total current IOH, for all outputs combined should not exceed 500 µA to hold the maximum voltage drop specified, limited
by low leakage switches.
The maximum total current IOL, for all outputs combined should not exceed 500 µA to hold the maximum voltage drop specified.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration tINT is met.
5.8
High-Frequency Oscillator (4 MHz), HFOSC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fHFOSC
TEST CONDITIONS
±20%
Duty cycle
MIN
TYP
MAX
UNIT
3.04
3.8
4.56
MHz
45%
50%
55%
tSTART
5.9
1
µs
Low-Frequency Oscillator (256 kHz), LFOSC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fLFO
TEST CONDITIONS
trimmed ±5%
Duty cycle
tSTART
12
MIN
TYP
MAX
UNIT
243
256
269
kHz
45%
50%
55%
11
Specifications
µs
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
5.10 Wake-Up From Low-Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDDB
MIN
TYP
MAX
UNIT
tWAKE-UP LPM0
Wake-up time from LPM0 to active
mode (1)
1.5 V
3.2
6
µs
tWAKE-UP LPM34
Wake-up time from LPM3 or LPM4 to
active mode (1)
1.5 V
160
260
µs
tWAKE-UP RESET
Wake-up time from RST to active
mode. (2)
1.5 V
210
310
µs
(1)
(2)
VDDB stable
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is fetched. This time includes the activation of the FRAM during wake-up. fMCLK = 2 MHz.
The wake-up time is measured from the rising edge of the RST signal until the first instruction of the user program is fetched. This time
includes the activation of the FRAM during wake-up. fMCLK = 2 MHz.
5.11 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
All capture inputs, Minimum pulse
duration required for capture
VDDB
1.5 V
1.5 V
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
MIN
TYP
MAX
UNIT
4
MHz
20
ns
Specifications
13
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
5.12 eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
feUSCI
CONDITIONS
eUSCI input clock frequency
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
VDDB
MIN
TYP
1.5 V
MAX
UNIT
fSYSTEM
MHz
5.13 eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
tSTE,LEAD
tSTE,LAG
tSTE,ACC
TEST CONDITIONS
STE lead time, STE active to clock
STE lag time, Last clock to STE
inactive
STE access time, STE active to SIMO
data out
STE disable time, STE inactive to
SIMO high impedance
tSTE,DIS
VDDB
MIN
TYP
MAX
UCSTEM = 0,
UCMODEx = 01 or 10
1.5 V
1
UCSTEM = 1,
UCMODEx = 01 or 10
1.5 V
1
UCSTEM = 0,
UCMODEx = 01 or 10
1.5 V
1
UCSTEM = 1,
UCMODEx = 01 or 10
1.5 V
1
UCSTEM = 0,
UCMODEx = 01 or 10
1.5 V
55
UCSTEM = 1,
UCMODEx = 01 or 10
1.5 V
35
UCSTEM = 0,
UCMODEx = 01 or 10
1.5 V
40
UCSTEM = 1,
UCMODEx = 01 or 10
1.5 V
30
UNIT
UCxCLK
cycles
UCxCLK
cycles
ns
ns
tSU,MI
SOMI input data setup time
1.5 V
35
ns
tHD,MI
SOMI input data hold time
1.5 V
0
ns
tVALID,MO
SIMO output data valid time (2)
tHD,MO
(1)
(2)
(3)
14
SIMO output data hold time
(3)
UCLK edge to SIMO valid,
CL = 20 pF
1.5 V
CL = 20 pF
1.5 V
30
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-1 and Figure 5-2.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 51 and Figure 5-2.
Specifications
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tSTE,DIS
tVALID,MO
tSTE,ACC
SIMO
Figure 5-1. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tSTE,ACC
tVALID,MO
tSTE,DIS
SIMO
Figure 5-2. SPI Master Mode, CKPH = 1
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Specifications
15
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
5.14 eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VDDB
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
1.5 V
7
tSTE,LAG
STE lag time, Last clock to STE inactive
1.5 V
0
tSTE,ACC
STE access time, STE active to SOMI data out
1.5 V
65
ns
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
1.5 V
40
ns
tSU,SI
SIMO input data setup time
1.5 V
2
ns
tHD,SI
SIMO input data hold time
1.5 V
5
ns
tVALID,SO
SOMI output data valid time (2)
tHD,SO
(1)
(2)
(3)
16
SOMI output data hold time
(3)
UCLK edge to SOMI valid,
CL = 20 pF
1.5 V
CL = 20 pF
1.5 V
ns
ns
30
4
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-3 and Figure 5-4.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-3
and Figure 5-4.
Specifications
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tDIS
tVALID,SOMI
SOMI
Figure 5-3. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tVALID,SO
tDIS
SOMI
Figure 5-4. SPI Slave Mode, CKPH = 1
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Specifications
17
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
5.15 eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-5)
PARAMETER
TEST CONDITIONS
VDDB
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
1.5 V
0
ns
tSU,DAT
Data setup time
1.5 V
250
ns
tSU,STO
1.5 V
fSCL = 100 kHz
fSCL = 100 kHz
1.5 V
fSCL > 100 kHz
fSCL = 100 kHz
Setup time for STOP
1.5 V
fSCL > 100 kHz
Pulse duration of spikes suppressed by input
filter
tSP
1.5 V
fSCL > 100 kHz
0
4.0
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
UCGLITx = 0
50
600
ns
UCGLITx = 1
25
300
ns
12.5
150
ns
6.25
75
1.5 V
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
tTIMEOUT
Clock low time-out
UCCLTOx = 2
1.5 V
UCCLTOx = 3
tSU,STA
tHD,STA
tHD,STA
ns
27
ms
30
ms
33
ms
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-5. I2C Mode Timing
5.16 FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tWRITE
TEST CONDITIONS
MIN
TYP
Word or byte write time
125
Read/write endurance
tRetention
Data retention duration
MAX
TJ = 25°C
UNIT
ns
1015
cycles
10
years
5.17 JTAG
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fTCK
(1)
18
TCK input frequency, 4-wire JTAG (1)
VDDB
MIN
1.5 V
0
TYP
MAX
UNIT
4
MHz
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
5.18 RFPMM, Power Supply Switch
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VTH+
Positive going switching threshold
VTH+ = VDDB-VDDR
VTH-
Negative going switching threshold
VTH- = VDDB-VDDR
VHYST
Switching voltage hysteresis
VHYST = VTH+-VTH-
IBASVBAT
VDDB input leakage current
VDROP
VDROP= VDDB - VDDSW
(1)
TEST CONDITIONS
MIN
TYP
MAX
35
60
-60
-35
30
70
VDDB = 1.65 V, Battery switch open
(1)
UNIT
mV
mV
110
mV
20
nA
50
mV
Battery switch closed. Current = 400 µA
5.19 RFPMM, Bandgap Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VREF
Output voltage
TEST CONDITIONS
MIN
VDDSW = 1.4 V to 1.65 V
TYP
892
MAX
UNIT
908
mV
5.20 RFPMM, Voltage Doubler
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VDD2X
Output voltage
VDDSW = 1.4 V, IDD2X = 1 µA, cont = 0
2×
VDDSW –
74mV
VDD2X
Output voltage
VDDSW = 1.4 V, IDD2X = 100 µA, cont = 1
2×
VDDSW –
104mV
TYP
MAX
UNIT
mV
mV
5.21 RFPMM, Voltage Supervision
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VDDSW
MIN
TYP
MAX
UNIT
VDDBTH+
Positive threshold
1.5 V
1.45
V
VDDBTH-
Negative threshold
1.5 V
1.40
V
VDDSWTH+
Positive threshold
1.40
V
VDDSWTH-
Negative threshold
1.35
V
VDDDTH+
Positive threshold
1.5 V
1.00
V
VDDDTH-
Negative threshold
1.5 V
0.90
V
VDD2XTH+
Positive threshold
1.5 V
2.70
V
VDD2XTH-
Negative threshold
1.5 V
2.475
V
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Specifications
19
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
5.22 SD14, Performance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Modulator clock frequency
RES
Resolution
OSR
Oversampling ratio
B
Bandwidth of input signal
VI
Input voltage range
VI = VADCx - VSVSS
Voffset
Offset error
VGErr
Gain error (2)
∆EG/∆T
Gain error temperature coefficient.
EUnadjusted
Total unadjusted error
tStart
Startup time
(3)
NOM
Internal LF oscillator as clock source for
SD14 module
fM
(1)
(2)
MIN
(3)
MAX
2
UNIT
kHz
8
14
40
2048
Bit
1
Hz
0
VREF
mV
Complete signal chain
-0.75
0.75
% of
FSR (1)
complete signal chain
-2%
2%
complete signal chain
-2
100
ppm/K
2
% of
FSR (1)
CLK
cycles
20
FSR = Full Scale Range (SD14 pre-amplifier Gain PGA gain - SD14 gain =1) .
The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process,
temperature and supply voltage variations.
Not production tested.
5.23 SVSS Generator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSVSS
Output voltage
ISVSS = -5uA .. 0uA
tSettling
Settling time after switching SVSS on
(95% of final voltage)
Switch from VIRTGND = 1 to VIRTGND = 0
20
Specifications
MIN
TYP
MAX
UNIT
80
125
165
mV
400
1000
ms
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
5.24 Thermistor Bias Generator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IOUT,TH
TEST CONDITIONS
Output current
VOUT = 0 to 0.7 V
MIN
TYP
MAX
UNIT
2.0
2.4
3.0
TYP
MAX
µA
5.25 Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tc
TEST CONDITIONS
MIN
Temperature coefficient
35.7
UNIT
LSB/K
5.26 RF13M, Power Supply and Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDDH
Antenna rectified voltage
IDDH = 100 µA
CIN
Input capacitance
2 V RMS
MIN
TYP
MAX
1.8
2
3.6
UNIT
V
31.5
35
38.5
pF
TYP
MAX
UNIT
kbps
5.27 RF13M, ISO/IEC 15693 ASK Demodulator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
DR100
Input signal data rate 100% downlink modulation, 100% ASK, ISO/IEC 15693
6
26
m100
Modulation depth 100%, test as defined in ISO10373
90%
100%
m10
Modulation depth 10%, test as defined in ISO10373
7%
30%
|tPLH– tPHL| Delta propagation delay of RXD_10 to VIN
0
2.35
µs
tPLH, tPHL
Propagation delay of RXD_10 to VIN
0
7.07
µs
tpd100
Propagation delay of RXD_100
7.07
µs
tD100
Minimum pulse duration of RxD_100
5
µs
5.28 RF13M, ISO/IEC 15693 Compliant Load Modulator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
1
MHz
fPICC
Uplink subcarrier modulation frequency
0.2
VA_MOD
Modulated antenna voltage, VA_unmod = 2,3V
0.5
V
VSUB15
Uplink modulation subcarrier level, ISO/IEC 15693
10
mV
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Specifications
21
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-Bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
6.2
Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes.
Each instruction can operate on word and byte data.
22
Detailed Description
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
6.3
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Operating Modes
The device has one active mode and three software selectable low-power modes of operation. An
interrupt event can wake up the device from any of the three low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
NOTE
The software-selected low-power mode might not be reached if at least one module still
requests a clock on MCLK, SMCLK, or ACLK. The CPU, however, remains off until an
interrupt occurs.
The following operating modes can be configured by software:
• Active mode AM
– CPU is enabled
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled
– MCLK is disabled
– SMCLK is active
– ACLK is active
– HFOSC is off, if not selected for SMCLK or ACLK
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK is disabled
– SMCLK is disabled
– ACLK is active
– HFOSC is off, if not selected for ACLK
• Low-power mode 4 (LPM4)
– CPU is disabled
– MCLK is disabled
– SMCLK is disabled
– ACLK is disabled
– HFOSC is off, LFOSC is on
LPM1 is identical to LPM0, and LPM2 is identical to LPM3, because the SCG0 bit has no influence on
HFOSC.
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Detailed Description
23
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
6.4
www.ti.com
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFE0h.
Address Range 0FFDFh to 0FFD0h is reserved for bootcode signatures. The vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence.
Table 6-1. Interrupt Sources, Flags, and Vectors
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
WDTIFG (1)
Reset
FFFEh
15, highest
SVMIFG, VMAIFG (1)
(Non)maskable
0FFFCh
14
NMIIFG (1) (2)
(Non)maskable
0FFFAh
13
TimerA0_A3
TA0CCR0 CCIFG0 (3)
Maskable
0FFF8h
12
TimerA0_A3
TA0CCR1 CCIFG1
TA0CCR2 CCIFG2
TA0CTL TAIFGTA0IV (1) (3)
Maskable
0FFF6h
11
WDTIFG
Maskable
0FFF4h
10
RF13MRXIFG, RF13MTXIFG, RF13MRXWMIFG,
RF13MTXWMIFG, RF13MSLIFG,
RF13MOUFLIFG, RF13MRXEIFG,
RF13MIVx (1) (3)
Maskable
0FFF2h
9
Maskable
0FFF0h
8
SD14OVIFG, SD14IFG (1) (3)
Maskable
0FFEEh
7
P1IFG.0 to P1IFG.7
(P1IV) (1) (3)
Maskable
0FFECh
6
RFPMMIFGV2X, RFPMMIFGVH, RFPMMIFGVR,
RFPMMIFGVB, RFPMMIFGVF, RFPMMIV
Maskable
0FFEAh
5
0FFE8h
4
INTERRUPT SOURCE
System Reset
Power-Up
External Reset
Watchdog
System NMI
Vacant memory access
User NMI
NMI
Watchdog,
Interval Timer Mode
RF13M Module
eUSCIB
(SPI mode)
UCB0RXIFG, UCB0TXIFG
(I2C mode)
UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG,
UCB0STPIFG, UCB0RXIFG3, UCB0TXIFG3,
UCB0RXIFG2, UCB0TXIFG2, UCB0RXIFG1,
UCB0TXIFG1, UCB0RXIFG0, UCB0TXIFG0,
UCB0CNTIFG, UCB0CLTOIFG, UCB0BIT9IFG
(SD14IV) (1) (3)
Sigma Delta ADC
I/O Port P1
RFPMM
Reserved
(1)
(2)
(3)
(4)
24
Reserved (4)
⋮
⋮
0FFDCh
0
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
Reserved interrupt vectors at these addresses are not used in this device and can be used for regular program code if necessary. To
maintain compatibility with other devices, it is recommended to reserve these locations.
Detailed Description
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Table 6-1. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
Signatures
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
CRC Value
0FFDAh
CRC Length
0FFD8h
Loader Signature 1
0FFD6h
Loader Signature 0
0FFD4h
JTAG Signature 1
0FFD2h
JTAG Signature 0
0FFD0h
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
PRIORITY
Detailed Description
25
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
6.5
www.ti.com
Memory
Table 6-2 shows the memory organization of the devices.
Table 6-2. Memory Map RF430FRL152H, RF430FRL153H, RF430FRL154H
TYPE
RF430FRL152H
RF430FRL153H
RF430FRL154H
ROM Development Mode
Memory (FRAM)
Main: interrupt vector
Total Size
FRAM
2048 B = 2 KB
0FFFFh-0FFE0h
Main: Code Memory
Bank A (1) (2)
512 B
0FFFFh-0FE00h
Bank B (1)
512 B
0FDFFh-0FC00h
Bank C (1)
512 B
0FBFFh-0FA00h
Bank D
448 B
0F9FFh-0F840h
Boot Data (TLV)
Size
FRAM
64 B
01A3Fh-01A00h
64 B
01A3Fh-01A00h
Application ROM
Size
ROM
7168 B = 7 KB
05FFFh-04400h
3584 B = 3.5 KB
051FFh-04400h
ROM Development Memory
Size
SRAM
-
3584 B = 3.5 KB
02BFFh-01E00h
SRAM Memory
Size
SRAM
4096 B = 4 KB
02BFFh-01C00h
512 B = 0.5 KB
01DFFh-01C00h
Peripherals
Size
4096 B = 4 KB
00FFFh-00000h
4096 B = 4 KB
00FFFh-00000h
(1)
(2)
6.5.1
RF430FRL152H
RF430FRL153H
RF430FRL154H
Normal Mode
Write protectable. See also Table 6-3
Address range includes interrupt vector.
FRAM
The FRAM can be programmed through the JTAG port or in-system by the CPU, data are received
through RF, SPI or I2C Sensor Interface.
Features of the FRAM include:
• Low-power ultra-fast-write non-volatile memory
• Byte and word access capability
• Automated wait state generation
The following address ranges can be write protected by setting the corresponding bit in the SYSCNF
register, see the RF430FRL15xH Family Technical Reference Manual (SLAU506).
Table 6-3. Write Protectable FRAM Address Ranges
26
Detailed Description
BIT
Address Range
FRAMLCK2
512 B
0FFFFh-0FE00h
FRAMLCK1
512 B
0FDFFh-0FC00h
FRAMLCK0
512 B
0FBFFh-0FA00h
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
6.5.2
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
SRAM
The SRAM memory is made up of 8 sectors. Each sector can be completely powered down to save
leakage; however, all data is lost. Features of the SRAM memory include:
• SRAM memory has 8 sectors of 512 B each.
• Each sector 0 to 8 can be complete disabled; however, data retention is lost.
• Each sector 0 to 8 automatically enters low-power retention mode when possible.
6.5.3
Application ROM
The Application ROM consists of four parts. The RF Library provides ISO/IEC 15693 functions necessary
for operating the 13.65 MHz front end. The Function library holds the device and memory function used by
the boot code and RF library. These functions are user accessible. The ROM contains the predefined
application FW. The boot code checks the password and releases control to the application or enables
JTAG on password match, enters LPM4 and waits for debug session, see the RF430FRL15xH Firmware
User's Guide (SLAU603).
6.6
Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
managed using all instructions. For complete module descriptions, see the RF430FRL15xH Family
Technical Reference Manual (SLAU506).
6.6.1
Digital I/O, (P1.x)
There is one I/O port implemented, P1, with eight I/O lines RF430FRL15xH.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown resistor on all ports.
• Edge-selectable interrupt input capability for all ports on P1.
• Read and write access to port-control registers is supported by all instructions.
6.6.2
Versatile I/O Port P1
The versatile I/O ports P1 feature device dependent reset values. The reset values for the
RF430FRL15xH devices are shown in Table 6-4.
Table 6-4. Versatile Port Reset Values
PORT
NUMBER
PxOUT
PxDIR
PxREN
PxSEL0
PxSEL1
RESET
PORTS ON
P1.0
0
0
0
0
0
PUC
yes
P1.0, input
P1.1
0
0
0
0
0
PUC
yes
P1.1, input
P1.2
0
0
0
0
0
PUC
yes
P1.2, input
P1.3
0
0
0
0
0
PUC
yes
P1.3, input
P1.4
1
0
1
1
1
PUC
yes
JTAG TCK, P1.4, input
P1.5
1
0
1
1
1
PUC
yes
JTAG TDI, P1.5, input
P1.6
0
0
0
1
1
PUC
yes
JTAG TDO, P1.6, output
P1.7
1
0
1
1
1
PUC
yes
JTAG TMS, P1.7, input
6.6.3
COMMENT
Oscillator and System Clock
The clock system in the RF430FRL15xH devices is supported by the Compact Clock System (CCS)
module that includes support for an internal trimmable 256-kHz current-controlled low-frequency oscillator
(LFOSC) and an internal 4-MHz current-controlled high-frequency oscillator (HFOSC).
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Detailed Description
27
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
The CCS module is designed to meet the requirements of both low system cost and low power
consumption. The CCS provides a fast turn-on of the oscillators in less than 1 ms. The CCS module
provides the following clock signals:
• Auxiliary clock (ACLK), sourced from the 256-kHz internal LFOSC.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
6.6.4
Compact System Module (C-SYS_A)
The Compact SYS module handles many of the system functions within the device. These include poweron reset and power-up clear handling, NMI source selection and management, reset interrupt vector
generators, as well as, configuration management. It also includes a data exchange mechanism through
JTAG called a JTAG mailbox that can be used in the application.
Table 6-5. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
INTERRUPT VECTOR
WORD ADDRESS
OFFSET
SYSRSTIV, System Reset
No interrupt pending
019Eh
00h
Brownout (BOR)
02h
SVMBOR (BOR)
04h
RST/NMI (BOR)
06h
DoBOR (BOR)
08h
Security violation (BOR)
0Ah
DoPOR (POR)
0Ch
WDT time-out (PUC)
0Eh
WDT key violation (PUC)
10h
CCS key violation
12h
PMM key violation
14h
Peripheral area fetch (PUC)
16h
Reserved
SYSSNIV, System NMI
SYSUNIV, User NMI
SYSBERRIV, Bus Error
No interrupt pending
02h
VMAIFG
04h
JMBINIFG
06h
JMBOUTIFG
08h
Reserved
0Ah-3Eh
No interrupt pending
019Ah
02h
OFIFG
04h
BERR
06h
Reserved
08h-3Eh
0198h
Lowest
Highest
Lowest
00h
NMIFG
No interrupt pending
Highest
00h
SVMIFG
Reserved
6.6.5
18h-3Eh
019Ch
PRIORITY
Highest
Lowest
00h
02h-3Eh
Lowest
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart
after a software problem occurs. If the selected time interval expires, a system reset is generated. If the
watchdog function is not needed in an application, the module can be configured as an interval timer and
can generate interrupts at selected time intervals.
28
Detailed Description
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
6.6.6
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Reset, NMI, SVMOUT System
The reset system of the RF430FRL15xH devices features the function reset input, reset output, and NMI
input.
6.6.7
Timer_A (Timer0_A3)
Timer_A is a 16-bit timer/counter with three capture/compare registers. Timer_A can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-6. Timer0_A3 Signal Connections
INPUT PIN
NUMBER
8 – P1.3
DEVICE INPUT
SIGNAL
MODUL INPUT
SIGNAL
TA0CLK
TACLK
MODULE BLOCK
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
OUTPUT PIN
NUMBER
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
TA0CLK
TACLK
12 – P1.0
TA0.0
CCI0A
9 – P1.2
11 – P1.1
TA0.0
CCI0B
20 – P1.6
VSS
GND
VDDB
Vcc
22 – P1.4
TA0.1
CCI1A
21 – P1.5
TA0.1
CCI1B
VSS
GND
VDDB
Vcc
20 – P1.6
TA0.2
CCI2A
19 – P1.7
TA0.2
CCI2B
VSS
GND
VDDB
Vcc
6.6.8
Timer
CCR0
NA
TA0
NA
TA0.0
19 – P1.7
12 – P1.0
CCR1
TA1
TA0.1
22 – P1.4
19 – P1.7
11 – P1.1
CCR2
TA2
TA0.2
8 – P1.3
21 – P1.5
20 – P1.6
Enhanced Universal Serial Communication Interface (eUSCI_B0)
The eUSCI_B0 module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin) and I2C.
The eUSCI_B0 module provides support for SPI (3 pin or 4 pin) or I2C.
6.6.9
ISO/IEC 15693 Analog Front End (RF13M)
The ISO/IEC 15693 module supports contact-less communication over the analog front end according to
ISO/IEC 15693 with data rates up to 26.48 kbps for receive and 26.48 kbps for transmit. It includes
decode of receive data and encode of transmit data, both synchronous with the AFE carrier clock.
6.6.10 ISO/IEC 15693 Decoder/Encoder (RF13M)
The module interfaces directly to the analog front end to ensure correct timing for transmit and receive of
data derived from the 13.56-MHz carrier frequency.
6.6.11 CRC16 Module (CRC16)
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data
checking purposes. The CRC16 module is compliant with ISO/IEC 13239, it is 16 bits long, polynominal is:
x16 + x12 + x5 + 1, direction is backward, and preset is 0xFFFF. For more information see ISO/IEC 13239.
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Detailed Description
29
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
6.6.12 14-Bit Sigma-Delta ADC (SD14)
A
•
•
•
sigma-delta modulator is provided for high resolution analog-to-digital conversion of quasi-dc voltages:
First-order integrator, 1-bit comparator, 1-bit DAC
Sampling frequency of up to 2 kHz
Fully differential
6.6.13 Programmable Gain Amplifier (SD14)
The PGA features a very high-impedance input and a programmable gain combined with full offset
compensation, very low offset drift, and low noise.
6.6.14 Peripheral Register Map
Table 6-7. Peripheral Register Map
REGISTER
BASE
ADDRESS
RF13M RX/TX High/Low Watermark Configuration Register
RF13MWMCFG
0800h
RF13M RX/TX FIFO Fill Level register
RF13MFIFOFL
0Ch
RF13M CRC accumulator Register
RF13MCRC
0Ah
RF13M Transmit Data FIFO Register
RF13MTXF
08h
RF13M Receive Data FIFO Register
RF13MRXF
06h
MODULE NAME
RF13M
REGISTER DESCRIPTION
RF13M Interrupt Vector Register
SD14
RF13MIV
04h
RF13MINT
02h
RF13M Control Register
RF13MCTL
SD14IV
00h
0700h
0Ch
SD14 Intermediate Conversion Result Register
SD14MEM3
0Ah
SD14 Intermediate Conversion Result Register
SD14MEM2
08h
SD14 Intermediate Conversion Result Register
SD14MEM1
06h
SD14 Conversion Result
SD14MEM0
04h
SD14 Control Register 1
SD14CTL1
02h
SD14 Control Register 0
SD14CTL0
00h
Interrupt Vector Word Register
Interrupt Flags Register
Interrupt Enable Register
I2C Slave Address Register
Address Mask Register
30
0Eh
RF13M Interrupt Register
SD14 Interrupt Vector Register
eUSCI_B0
OFFSET
UCB0IV
0640h
2Eh
UCB0IFG
2Ch
UCB0IE
2Ah
UCB0I2CSA
20h
UCB0ADDMASK
1Eh
Received Address Register
UCB0ADDRX
1Ch
I2C Own Address 3 Register
UCB0I2COA3
1Ah
I2C Own Address 2 Register
UCB0I2COA2
18h
I2C Own Address 1 Register
UCB0I2COA1
16h
I2C Own Address 0 Register
UCB0I2COA0
14h
Transmit Buffer Register
UCB0TXBUF
0Eh
Receive Buffer Register
UCB0RXBUF
0Ch
Byte Counter Threshold Register
UCB0TBCNT
0Ah
Status Word Register
UCB0STATW
08h
Bit Rate 1 Register
UCB0BR1
07h
Bit Rate 0 Register
UCB0BR0
06h
Control Word 1 Register
UCB0CTLW1
02h
Control Word 0 Register
UCB0CTLW0
00h
Detailed Description
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Table 6-7. Peripheral Register Map (continued)
MODULE NAME
Timer0_A3
REGISTER DESCRIPTION
Timer0_A Interrupt Vector Register
2Eh
16h
14h
Capture/Compare Register 0
TA0CCR0
12h
TA0R
10h
Capture/Compare Control 2 Register
TA0CCTL2
06h
Capture/Compare Control 1 Register
TA0CCTL1
04h
Capture/Compare Control 0 Register
TA0CCTL0
02h
Port P1 Interrupt Flag Register
TA0CTL
P1IFG
00h
0200h
P1IE
1Ch
1Ah
Port P1 Interrupt Edge Select Register
P1IES
18h
Port P1 Interrupt Vector Word Register
P1IV
0Eh
Port P1 Selection 1 Register
P1SEL1
0Ch
Port P1 Selection 0 Register
P1SEL0
0Ah
Port P1 Pullup/Pulldown Enable Register
P1REN
06h
Port P1 Direction Register
P1DIR
04h
Port P1 Outout Register
P1OUT
02h
Reset Vector Generator Register
P1IN
SYSRSTIV
00h
0180h
1Eh
System NMI Vector Generator Register
SYSSNIV
1Ch
User NMI Vector Generator Register
SYSUNIV
1Ah
Bus Error Vector Generator Register
SYSBERRIV
18h
System Configuration Actuator 0 Register
SYSCA0
14h
System Configuration Register
SYSCNF
10h
JTAG Mailbox Output Register 1
SYSJMBO1
0Eh
JTAG Mailbox Output Register 0
SYSJMBO0
0Ch
JTAG Mailbox Input Register 1
SYSJMBI1
0Ah
JTAG Mailbox Input Register 0
SYSJMBI0
08h
JTAG Mailbox Control Register
SYSJMBC
06h
System Control Register
SYSCTL
CCS Control 8 Register
CCSCTL8
CCS Control 7 Register
CCSCTL7
0Eh
CCS Control 6Register
CCSCTL6
0Ch
CCS Control 5 Register
CCSCTL5
0Ah
CCS Control 4 Register
CCSCTL4
08h
CCS Control 1 Register
CCSCTL1
02h
CCS Control 0 Register
CCSCTL0
Watchdog Timer Control Register
WDTCTL
00h
0160h
10h
00h
0150h
0Ch
CRC Result Reverse Register
CRCRESR
06h
CRC Initialization and Result Register
CRCINIRES
04h
CRCDIRB
02h
CRCDI
00h
CRC Data In Reverse Byte Register
CRC Data In Register
FRAM Control
0340h
TA0CCR1
Port P1 Input Register
WDT_A, CRC
TA0IV
Capture/Compare Register 1
Port P1 Interrupt Enable Register
CCS
OFFSET
TA0CCR2
Timer0_A Control Register
CSYS_A
BASE
ADDRESS
Capture/Compare Register 2
Timer0_A Counter Register
Port P1
REGISTER
General Control 1 Register
GCCTL1
General Control 0 Register
GCCTL0
04h
FRAM Control 0 Register
FRCTL0
00h
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
0140h
06h
Detailed Description
31
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
Table 6-7. Peripheral Register Map (continued)
MODULE NAME
RFPMM
REGISTER DESCRIPTION
RFPMM Interrupt Vector Register
RFPMM Interrupt Flag Register
OFFSET
RFPMMIV
0120h
08h
06h
RFPMMIE
04h
RFPMM Control Register 1
RFPMMCTL1
02h
RFPMM Control Register 0
RFPMMCTL0
SFR Reset Pin Control Register
SFR Interrupt Flag Register
SFR Interrupt Enable Register
32
BASE
ADDRESS
RFPMMIFG
RFPMM Interrupt Enable Register
Special Functions
REGISTER
Detailed Description
SFRRPCR
00h
0100h
04h
SFRIFG1
02h
SFRIE1
00h
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
6.7
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Port Schematics
6.7.1
Port P1.0 Input/Output
Pad Logic
P1REN.x
P1DIR.x
eUSCI_B0
Vss
Vcc
00
01
10
11
0
1
PortsOn
P1OUT.x
SPI_SIMO/SDA
SMCLK
TA 0.1
00
01
10
11
P1.0/SPI_SIMO/SDA/SMCLK/TA 0.1/CCI0.0
P1SEL0.x
P1SEL1.x
P1IN.x
# EN1
EN2
Modul x IN
D
P1IES.x
Set
Bus
Keeper
Q
P1IRQ.x
P1IFG.x
P1IE.x
Table 6-8. Port P1.0 Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/SPI_SIMO/SDA/SMCLK/TA0.1/CCI0.0
(1)
(2)
0
P1DIR.x
P1SEL1.x
P1SEL0.x
RSELx/
ASELx
I:0; O:1
0
0
0
SPI_SIMO/SDA (2)
1
0
1
0
SMCLK
1
1
0
0
TA0.1
1
1
1
0
Timer A0, CCI0A
0
≠0
≠0
X
X = Don't care
Module controls direction of port, depending on whether RF430 device is master or slave.
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Detailed Description
33
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
6.7.2
www.ti.com
Port P1.1 Input/Output
Pad Logic
P1REN.x
P1DIR.x
eUSCI_B0
Vss
Vcc
00
01
10
11
0
1
PortsOn
P1OUT.x
SPI_SOMI/SCL
ACLK
TA 0.2
00
01
10
11
P1.1/SPI_SOMI/SCL/ACLK/TA 0.2/CCI0.0
P1SEL0.x
P1SEL1.x
P1IN.x
# EN1
EN2
Modul x IN
D
P1IES.x
Set
Bus
Keeper
Q
P1IFG.x
P1IE.x
P1IRQ.x
Table 6-9. Port P1.1 Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x)
x
FUNCTION
P1.1 (I/O)
P1.1/SPI_SOMI/SCL/ACLK/TA0.2/CCI0.0
(1)
(2)
34
1
P1DIR.x
P1SEL1.x
P1SEL0.x
RSELx/ASE
Lx
I:0; O:1
0
0
0
SPI_SOMI/SCL (2)
1
0
1
0
ACLK
1
1
0
0
TA0.2
1
1
1
0
Timer A1, CCI0B
0
≠0
≠0
X
X = Don't care
Module controls direction of port, depending on whether RF430 device is master or slave.
Detailed Description
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
6.7.3
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Port P1.2 Input/Output
Pad Logic
P1REN.x
P1DIR.x
eUSCI_B0
Vss
Vcc
00
01
10
11
0
1
PortsOn
P1OUT.x
SPI_CLK
MCLK
TA 0.0
00
01
10
11
P1.2/SPI_CLK/MCLK /TA 0.0
P1SEL0.x
P1SEL1.x
P1IN.x
# EN1
EN2
Modul x IN
D
P1IES.x
Set
Bus
Keeper
Q
P1IFG.x
P1IE.x
P1IRQ.x
Table 6-10. Port P1 (P1.2) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x)
x
FUNCTION
P1.2 (I/O)
P1.2/SPI_CLK/MCLK/TA0.0
(1)
(2)
2
P1DIR.x
P1SEL1.x
P1SEL0.x
RSELx/ASEL
x
I:0; O:1
0
0
0
SPI_CLK (2)
1
0
1
0
MCLK
1
1
0
0
TA0.0
1
1
1
0
X = Don't care
Module controls direction of port, depending on whether RF430 device is master or slave.
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Detailed Description
35
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
6.7.4
www.ti.com
Port P1.3 Input/Output
Pad Logic
P1REN.x
P1DIR.x
eUSCI_B0
Vss
Vcc
00
01
10
11
0
1
PortsOn
P1OUT.x
SPI_STE
TA 0.2
00
01
10
11
P1.3/SPI_STE/TA 0.2/ACLK/TA 0CLK
P1SEL0.x
P1SEL1.x
P1IN.x
# EN1
EN2
Modul x IN
D
P1IES.x
Set
Bus
Keeper
Q
P1IFG.x
P1IE.x
P1IRQ.x
Table 6-11. Port P1 (P1.3) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x)
x
FUNCTION
P1.3 (I/O)
P1.3/SPI_STE/TA0.2/ACLK/TA0CLK
(1)
(2)
36
3
P1DIR.x
P1SEL1.x
P1SEL0.x
RSELx/ASE
Lx
I:0; O:1
0
0
0
SPI_STE (2)
1
0
1
0
TA0.2
1
1
0
0
ACLK
1
1
1
0
TA0CLK
X
≠0
≠0
X
X = Don't care
Module controls direction of port, depending on whether RF430 device is master or slave.
Detailed Description
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
6.7.5
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Port P1.4 Input/Output
Pad Logic
to clock system
Pad Logic
P1REN.x
P1DIR.x
Vss
Vcc
00
01
10
11
0
1
PortsOn
P1OUT.x
TA 0.1
SMCLK
RFU
00
01
10
11
P1.4/TA 0.1/SMCLK/TCK/CCI0.1/CLKIN
P1SEL0.x
P1SEL1.x
P1IN.x
TCK to JTAG logic
Enable from JTAG logic
# EN1
EN2
Module X IN
D
P1IES.x
Set
Bus
Keeper
Q
P1IFG.x
P1IE.x
P1IRQ.x
Table 6-12. Port P1.4 Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
JTAG Mode
I:0; O:1
0
0
0
Timer_A0.1
1
0
1
0
SMCLK
1
1
0
0
Reserved
1
1
1
0
Timer_A0.CCI1A
0
≠0
≠0
0
JTAG-TCK (2) (3) (4)
X
X
X
1
CLKIN from bypass
X
X
X
0
P1.4 (I/O)
TCK/P1.4/TA0.1/SMCLK/CCI0.1
(1)
(2)
(3)
(4)
4
CONTROL BITS OR SIGNALS (1)
X = Don't care
JTAG signals TMS, TCK, and TDI read as 1 when not configured as explicit JTAG terminals.
JTAG overrides digital output control when configured as explicit JTAG terminals.
JTAG function with enabled pullup resistors is default after power up.
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Detailed Description
37
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
6.7.6
www.ti.com
Port P1.5 Input/Output
Pad Logic
P1REN.x
P1DIR.x
Vss
Vcc
00
01
10
11
0
1
PortsOn
P1OUT.x
TA 0.2
MCLK
RFU
00
01
10
11
P1.5/TA 0.2/MCLK/TDI/CCI0.1
P1SEL0.x
P1SEL1.x
P1IN.x
TDI to JTAG logic
Enable from JTAG logic
# EN1
EN2
Module X IN
D
P1IES.x
Set
Bus
Keeper
Q
P1IFG.x
P1IE.x
P1IRQ.x
Table 6-13. Port P1.5 Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.5 (I/O)
TDI/P1.5/TA0.2/MCLK/CCI0.1
(1)
(2)
(3)
(4)
38
5
CONTROL BITS OR SIGNALS (1)
P1DIR.x
P1SEL1.x
P1SEL0.x
JTAG Mode
I:0; O:1
0
0
0
Timer_A0.2
1
0
1
0
MCLK
1
1
0
0
1
1
1
0
Timer_A0 CCI1B
0
≠0
≠0
0
JTAG-TDI (2) (3) (4)
X
X
X
1
X = Don't care
JTAG signals TMS, TCK, and TDI read as 1 when not configured as explicit JTAG terminals.
JTAG overrides digital output control when configured as explicit JTAG terminals.
JTAG function with enabled pullup resistors is default after power up.
Detailed Description
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
6.7.7
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Port P1.6 Input/Output
Pad Logic
P1REN.x
P1DIR.x
from JTAG logic
Vss
Vcc
00
01
10
11
0
1
PortsOn
P1OUT.x
TA 0.0
TA 0.2
TDO from JTAG
00
01
10
11
TDO/P1.6/TA 0.0/TA 0.2/CCI0.2
P1SEL0.x
P1SEL1.x
P1IN.x
enable JTAG Mode
# EN1
EN2
Module X IN
D
P1IES.x
Set
Bus
Keeper
Q
P1IFG.x
P1IE.x
P1IRQ.x
Table 6-14. Port P1.6 Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1SEL1.x
P1SEL0.x
I:0; O:1
0
0
Timer_A0.0
1
0
1
Timer_A0.2
1
1
0
JTAG-TDO (1) (2)
1
1
1
Timer_A0 CCI2A
0
≠0
≠0
P1.6 (I/O)
TDO/P1.6/TA0.0/TA0.2/CCI0.2
(1)
(2)
6
CONTROL BITS OR SIGNALS
P1DIR.x
JTAG signals TMS, TCK, and TDI read as 1 when not configured as explicit JTAG terminals.
JTAG overrides digital output control when configured as explicit JTAG terminals.
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Detailed Description
39
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
6.7.8
www.ti.com
Port P1.7 Input/Output
Pad Logic
P1REN.x
Vss
Vcc
00
01
10
11
P1DIR.x
0
1
PortsOn
P1OUT.x
TA 0.1
TA 0.0
RFU
00
01
10
11
P1.7/TA0.1/TA0.0/TMS/CCI0.2
P1SEL0.x
P1SEL1.x
P1IN.x
TMS to JTAG logic
Enable from JTAG logic
# EN1
EN2
Module X IN
D
P1IES.x
Set
Bus
Keeper
Q
P1IFG.x
P1IE.x
P1IRQ.x
Table 6-15. Port P1.7 Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
JTAG Mode
I:0; O:1
0
0
0
Timer_A0.1
1
0
1
0
Timer_A0.0
1
1
0
0
Reserved
1
1
1
0
Timer_A0.CCI2B
0
≠0
≠0
0
JTAG-TMS (2) (3) (4)
X
X
X
1
P1.7 (I/O)
TMS/P1.7/TA0.1/TA0.0/CCI0.2
(1)
(2)
(3)
(4)
40
7
CONTROL BITS OR SIGNALS (1)
X = Don't care
JTAG signals TMS, TCK, and TDI read as 1 when not configured as explicit JTAG terminals.
JTAG overrides digital output control when configured as explicit JTAG terminals.
JTAG function with enabled pullup resistors is default after power up.
Detailed Description
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
6.8
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Device Descriptors (TLV)
Table 6-16 list the complete contents of the device descriptor tag-length-value (TLV) structure for each
device type.
Table 6-16. RF430FRL15xH Boot Data and Device Descriptor Table
Info Block
Description
Address
Size
bytes
FRL152H
FRL153H
FRL154H
Boot Data Length
01A00h
1
03h
03h
03h
CRC length
01A01h
1
03h
03h
03h
Boot Data CRC value
01A02h
2
per unit
per unit
per unit
Device ID
01A04h
1
E7h
FBh
FCh
Device ID
01A05h
1
81h
81h
81h
Lot #0
01A06h
1
per unit
per unit
per unit
Lot #1
01A07h
1
per unit
per unit
per unit
UID0
01A08h
1
per unit
per unit
per unit
UID1
01A09h
1
per unit
per unit
per unit
UID2
01A0Ah
1
per unit
per unit
per unit
UID3
01A0Bh
1
per unit
per unit
per unit
UID4
01A0Ch
1
per unit
per unit
per unit
UID5
01A0Dh
1
A2h / A3h
A2h / A3h
A2h / A3h
per unit
Die Record
Calibration
ECC
Lot #2
01A0Eh
1
per unit
per unit
Fab ID / Wafer Number
01A0Fh
1
per unit
per unit
per unit
Reserved
01A10h
2
0FFFFh
0FFFFh
0FFFFh
Reserved
01A12h
2
0FFFFh
0FFFFh
0FFFFh
Calibration Pointer
01A14h
2
01A14h
01A14h
01A14h
Reserved
01A16h
2
per unit
per unit
per unit
Reserved
01A18h
2
per unit
per unit
per unit
Reserved
01A1Ah
2
per unit
per unit
per unit
Reserved
01A1Ch
2
per unit
per unit
per unit
Reserved
01A1Eh
2
per unit
per unit
per unit
ECC of previous data
01A3E 01A20h
32
per unit
per unit
per unit
Table 6-17. UID (Unique Identifier) Definition
Description
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Lot ID 0
0x1A06
LotNr[7]
LotNr[6]
LotNr[5]
LotNr[4]
LotNr[3]
LotNr[2]
LotNr[1]
LotNr[0]
Lot ID 1
0x1A07
LotNr[15]
LotNr[14]
LotNr[13]
LotNr[12]
LotNr[11]
LotNr[10]
LotNr[9]
LotNr[8]
UID0
0x1A08
TI[7]
TI[6]
TI[5]
TI[4]
TI[3]
TI[2]
TI[1]
TI[0]
UID1
0x1A09
TI[15]
TI[14]
TI[13]
TI[12]
TI[11]
TI[10]
TI[9]
TI[8]
UID2
0x1A0A
TI[23]
TI[22]
TI[21]
TI[20]
TI[19]
TI[18]
TI[17]
TI[16]
UID3
0x1A0B
TI[31]
TI[30]
TI[29]
TI[28]
TI[27]
TI[26]
TI[25]
TI[24]
UID4
0x1A0C
TI[39]
TI[38]
TI[37]
TI[36]
TI[35]
TI[34]
TI[33]
TI[32]
UID5
0x1A0D
1
0
1
0
0
0
1
TI[40]
Lot ID 2
0x1A0E
LotNr[23]
LotNr[22]
LotNr[21]
LotNr[20]
LotNr[19]
LotNr[18]
LotNr[17]
LotNr[16]
FabID
0x1A0F
Wafer[4]
Wafer[3]
Wafer[2]
Wafer[1]
Wafer[0]
FabNr[2]
FabNr[1]
FabNr[0]
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Detailed Description
41
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
7 Applications, Implementation, and Layout
JTAG signals
C9
ANT2
C2
VDDSW
VDDB
CP1
B1
C3
C4
CP2
TDO
TMS
ADC2
18
17
2
3
16
4
15
5
14
6
13
8
ADC1/TEMP1
R2
TST1
SVSS
C7
TST2
ADC0
VDD2X
9 10 11 12
RST/NMI
7
C5
TCK
24 23 22 21 20 19
1
VDD2X
SCL
ANT1
SDA
C1
L1
TDI
VDD
VDDH
C8
Analog
Sensor 1
SVSS
C6
Analog
Sensor 2
SVSS
Two analog sensors connected through I2C, supplied by VDD2X (≈3 V)
Figure 7-1. Application Circuit
Table 7-1 lists the bill of materials for this application.
Table 7-1. Bill of Materials
42
Name
Value
L1
3 µH
C1
8.2 pF
RF tuning capacitor (nominal)
C2
2.2 µF
Decoupling cap at VDDSW
C3
100 nF
Decoupling cap at VDDB
C4
10 nF
Charge pump capacitor
C5
100 nF
Decoupling cap at VDD2X
C6
10 nF
Decoupling cap at RST
C7
1µF
C8
100 nF
Decoupling cap at VDD
C9
100 nF
Decoupling cap at VDDH
B1
1.5 V
R2
100 kΩ
Applications, Implementation, and Layout
Description
RF inductance (nominal)
Bypass capacitor between SVSS and VSS
Battery
Reference resistor
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
8 Device and Documentation Support
8.1
8.1.1
Device Support
Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
For an overview of the development tool and driver support for NFC transponders, visit the Tools &
Software for NFC / RFID page.
8.1.2
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
RF430 MCU devices and support tools. Each commercial family member has one of three prefixes: RF, P,
or X (for example, RF430FRL152H). Texas Instruments recommends two of three possible prefix
designators for its support tools: RF and X. These prefixes represent evolutionary stages of product
development from engineering prototypes (with X for devices and tools) through fully qualified production
devices and tools (with RF for devices tools).
Device development evolutionary flow:
X – Experimental device that is not necessarily representative of the final device's electrical specifications
P – Final silicon die that conforms to the device's electrical specifications but has not completed quality
and reliability verification
RF – Fully qualified production device
Support tool development evolutionary flow:
X – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
RF – Fully-qualified development-support product
X and P devices and X development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
RF devices and RF development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X and P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RGE) and temperature range (for example, T). Figure 8-1 provides a legend
for reading the complete device name for any family member.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Copyright © 2012–2014, Texas Instruments Incorporated
43
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
www.ti.com
RF 430 FRL 152 H A I RGE R XX
Processor Family
Optional: Additional Features
430 MCU Platform
Optional: Tape and Reel
Packaging
Device Type
Device Designator
Wireless Technology
Processor Family
430 MCU Platform
Optional: Temperature Range
Optional: Revision
RF = Embedded RF Radio
X = Experimental Silicon
P = Prototype Device
TI’s Low Power Microcontroller Platform
Device Type
FR = FRAM Memory
L = Low-Power Series
Device Designator
Various Levels of Integration Within a Series
Wireless Technology
HF = High Frequency
Optional: Revision
A = Device Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = -40°C to 85°C
T = -40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel (7 inch)
R = Large Reel (11 inch)
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (-40°C to 105°C)
-HT = Extreme Temperature Parts (-55°C to 150°C)
Figure 8-1. Device Nomenclature
8.2
Documentation Support
The following documents describe the RF430FRL15xH devices.
8.3
SLAU506
RF430FRL15xH Family Technical Reference Manual. Detailed description of all modules
and peripherals available in this device family.
SLAU603
RF430FRL15xH Firmware User's Guide. Detailed description of the firmware that is provided
for these devices.
Related Links
Table 8-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
44
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
RF430FRL152H
Click here
Click here
Click here
Click here
Click here
RF430FRL153H
Click here
Click here
Click here
Click here
Click here
RF430FRL154H
Click here
Click here
Click here
Click here
Click here
Device and Documentation Support
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
8.4
SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.5
Trademarks
MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical Packaging and Orderable Information
9.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Copyright © 2012–2014, Texas Instruments Incorporated
45
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
RF430FRL152HCRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
RF430
FRL152H
RF430FRL153HCRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
RF430
FRL153H
RF430FRL154HCRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
RF430
FRL154H
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Apr-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
RF430FRL152HCRGER
Package Package Pins
Type Drawing
VQFN
RGE
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
4.3
B0
(mm)
K0
(mm)
P1
(mm)
4.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Apr-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
RF430FRL152HCRGER
VQFN
RGE
24
3000
338.1
338.1
20.6
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated
工商网监
湘ICP备2023018690号
