XIO2001
Evaluation Module (EVM)
User's Guide
Literature Number: SCPU031B
February 2009 – Revised June 2014
Contents
1
2
Overview ............................................................................................................................. 4
EVM Features ...................................................................................................................... 4
................................................................................................. 4
......................................................................................................... 4
2.3
EEPROM Interface ...................................................................................................... 5
2.4
Test Header ............................................................................................................... 5
2.5
Clock Run (CLKRUN) ................................................................................................... 6
2.6
JTAG Header ............................................................................................................. 6
2.7
LEDs ...................................................................................................................... 6
3
FAQ/Troubleshooting ........................................................................................................... 7
3.1
BIOS Fails to Assign Memory Window to Bridge .................................................................... 7
3.2
×16 Slots Only Support INTA .......................................................................................... 7
3.3
System Turns On When PCI Card Is Inserted Into EVM Or When EVM Is Plugged Into Slot ................. 7
3.4
What To Do If EVM Is Not Working ................................................................................... 8
4
Schematics ......................................................................................................................... 9
5
Bill of Materials ................................................................................................................. 13
Revision History .......................................................................................................................... 15
2
2.1
PCI Express Connector
2.2
PCI Add-In Slots
Table of Contents
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User's Guide
SCPU031B – February 2009 – Revised June 2014
XIO2001 Evaluation Module (EVM)
Read This First
About This Manual
This manual describes the operation of the XIO2001 evaluation module (EVM) from Texas Instruments.
How to Use This Manual
This document contains the following sections:
• Overview
• EVM Features
• FAQ/Troubleshooting
• Schematics
• Bill of Materials
Information About Cautions and Warnings
This manual may contain cautions and warnings.
CAUTION
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your
software or equipment.
WARNING
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
Related Documentation from Texas Instruments
Related TI Documentation contains a list of data manuals that have detailed descriptions of the integrated
circuits used in the design of the TAS3208EVM-LC. The data manuals can be obtained at www.ti.com.
Related TI Documentation
DOCUMENT
LITERATURE NUMBER
XIO2001 Implementation Guide
SCPA045
XIO2001 Data Manual
SCPS212
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XIO2001 Evaluation Module (EVM)
3
Overview
1
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Overview
The XIO2001 evaluation board (EVM) implements a peripheral component interconnect (PCI) express to
PCI bridge circuit using the Texas Instruments XIO2001 PCI Express to PCI Bus Translation Bridge.
Designed as an ×1 add-in card, it is routed on FR4 as a 8-layer (4 signals, 2 power, and 2 ground) board
with a 100-Ω differential impedance (50-Ω single-ended) using standard routing guidelines and
requirements. (1)
Power for the XIO2001 EVM and any PCI add-in card connected to the EVM is provided or derived from
the standard voltages provided on the PCI Express connector. Power for the 3.3-V rail is provided directly
from the add-in connector, 5-V and 12-V is provided from the IDE power connector, while regulators are
present to derive 1.5-V for the XIO2001 and -12-V for the PCI connectors.
Upon request, gerber files for the EVM can be provided that illustrate techniques that achieve fan-out of
the μ*BGA, use of split power planes, placement of filters and other critical components, and methods
used to match lengths on PCI and PCI Express signals on a standard 8-layer board.
Schematics and a Bill of Materials are provided to illustrate the design of this EVM.
NOTE: Observe proper ESD procedures when handling the EVM. Failure to observe proper
procedures may result in damage either to the EVM or the XIO2001 silicon which may cause
the board to malfunction.
2
EVM Features
2.1
PCI Express Connector
The EVM is designed as a half-width PCI Express add-in card. The card fits into any standard ×1, ×2, ×4,
×8, or ×16 add-in connector that is compliant with the PCI Express Electromechanical Specification,
Revision 2.0 or earlier. In addition to the standard transmit-and-receive pairs, the connector must supply
3.3 V, 12 V, PERST, a 100-MHz differential clock, and VAUX. The WAKE signal is also supported by the
EVM although, as an optional pin, the system is not required to support this signal.
The height of the board is nonstandard due to the presence of PCI slots. Inserting PCI add-in cards into
the EVM will, in most cases, prohibit the EVM from being placed in a case. If possible, provide some
mechanical support to the EVM. Otherwise, the weight of PCI add-in cards can strain the board in the PCI
Express add-in slot and may result in the board making poor contact with the connector. Poor connector
contact can lead to signal integrity issues.
2.2
PCI Add-In Slots
The XIO2001 EVM provides three standard PCI add-in slots. While reversible, these slots, as shipped, are
keyed as 5-V slots and provide a 5-V VIO clamping voltage that provides accessibility to any 5-V or
universally keyed PCI add-in cards. All standard voltages (3.3 V, 5 V, 12 V, and –12 V) are provided
through the PCI connectors, enabling standard PCI add-in cards to function without requiring external
power.
Cards placed into the PCI add-in slots must be inserted into the slots in accordance with labeling on the
EVM. Referencing the component side of the EVM as front and the PCI express edge connector as down,
boards must be inserted with the component side of the board down and the mounting bracket to the left
of the EVM.
WARNING
Inserting either a 3.3-V card or a universally keyed card into the
EVM backwards will damage the EVM and possibly the add-in card
as well.
(1)
4
As specified in PCI Express Electromechanical Specification, Revision 1.0a and PCI Local Bus Specification, Revision 2.3
XIO2001 Evaluation Module (EVM)
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EVM Features
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The PCI bus operates at 66 MHz only when 66-MHz-capable PCI add-in cards are placed in the socket. If
a 33-MHz card is inserted into the socket, then the XIO2001 detects the presence of the lower speed
device and automatically sets the bus speed to 33 MHz. If 66-MHz operation is desired, place no more
than two add-in cards into board slots. (This limitation is due to bus loading issues inherent to the PCI
specification.) If a third 66-MHz device is added to the bus, signal integrity may still permit proper
functioning of the interface, but such functionality cannot be assured and is beyond the scope of this
document.
Two of the reserved pins on the PCI add-in connectors are used to route PME and VAUX to any add-in
cards. These assignments, while not part of the PCI Local Bus Specification, are used by many in the
industry as de facto standards and must not interfere with any add-in cards. If cards are used that use
these terminals for other purposes, the following modifications may be made to the EVM to isolate the
signals from the PCI add-in connectors:
• PME (routed to reserved terminal A19 on each connector). Remove resistors R55, R53, and R54 (for
slots 0, 1, and 2, respectively).
• VAUX (routed to reserved terminal A14 on each connector). Remove resistors R50, R51, and R52 (for
slots 0, 1, and 2, respectively).
2.3
EEPROM Interface
Each XIO2001 EVM provides an on-board EEPROM. As shipped, each EEPROM is programmed with
values that will allow the EVM to function in most systems. The EEPROM interface is left as
programmable (not write-protected) so that EEPROM contents may be modified for testing other optional
settings. TI recommends that you do not change the EEPROM values. To change EEPROM contents, use
the EEPROM access registers as detailed in the XIO2001 data manual or request the WinROM access
tool.
2.4
Test Header
Each XIO2001 EVM provides accessibility to the GPIO pins on the XIO2001. From header J1, all five
GPIOs have external visibility and can be used in any manner consistent with their functionality as detailed
in the XIO2001 data manual. All GPIO signals are labeled on the header and are terminated with an onboard pullup resistor.
By default, GPIO3 and GPIO4 are configured as the EEPROM interface which was detailed in the
previous section. The EEPROM interface can be removed from the XIO2001 by removing resistors R28
and R29. This allows these GPIO pins to be used for another purpose, although any configuration done by
the EEPROM will then have to be done in some other fashion. While removing R28 and R29 will
physically disconnect the EEPROM from GPIO3/GPIO4, in order to release the pins from this functionality,
GPIO4 (SCL) must be held low at the deassertion of PERST. As no pulldown is available for this purpose,
the pin must be externally shorted at boot time (deassertion of reset) by shorting J1 pin 5 to J1 pin 11.
Once the system has booted, this short may be removed and GPIO3 and GPIO4 will be available for other
uses.
Pin 9 on the J1 header is a global reset (GRST ) for the XIO2001. Driving this pin low will cause all
registers and state machines within the XIO2001 to return to a default power-up state. This pin generally
must remain disconnected.
Pin 10 is an access point for the PME signal and may be used to externally wire this signal to any PCI
add-in card that has the signal available but does not route the signal to pin A19 on the PCI expansion
connector.
Pin 8 on header J1 is CLKREQ for the XIO2001. Driving this pin low will allow the REFCLK to stop when
the XIO2001 is in PCI PM L1. The CLKREQ protocol as described in the PCI Express Base Specification
and Express Card standard is supported.
Pin 7 on header J1 is PERST for the XIO2001. When asserted, this signal generates an internal PCI
Express reset, clears all non-sticky bit registers and is deasserted when system power is stable.
Pin 12 on header J1 is PCLK66_SEL for the XIO2001 controlling the PCI clock frequency. When this
signal is pulled high, the PCI clock will operate at 33 or 66 Mz depending on the state of M66EN. When
this signal is low, the PCI clock will operate at 25 MHz or 50 MHz, depending on the state of M66EN. Most
applications will pull this pin high.
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EVM Features
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Pin 2 on the connector is a 3.3-V test point and pin 11 is a ground test point. These signals may be used
to externally toggle GPIOs for any required testing.
2.5
Clock Run (CLKRUN)
The CLKRUN signal is a power-saving mechanism (defined in the PCI Mobile Design Guide) that stops
the PCI bus clock when the bus is idle. Because devices that do not support this protocol are unable to
restart the system clock, this feature is disabled by default on the XIO2001 EVM. This feature may be
enabled to function with PCI add-in cards that also support this feature.
Enabling CLKRUN requires that resistor R24 be populated with a 0805 form factor 10-kΩ resistor. When
this option is populated at the de-assertion of the reset pin, GPIO0 will internally map to CLKRUN. When
this happens, GPIO0 will be unavailable for other purposes. An external wire must then be connected from
GPIO0/CLKRUN (available on J1 pin 1) to all add-in cards being tested with this functionality.
2.6
JTAG Header
Each XIO2001 EVM provides access to JTAG interface pins for boundary scan testing on test header JP1.
The JTAG interface for the XI02001 complies with IEEE standard 1149 using the standard 5 pin interface
(TCK, TDI, TDO, TMS and TRST). If boundary scan testing is not needed, TCK (JP1 pin 10) and TRST
(JP1 pin 2) should be connected to GND (JP1 pins 1, 3, 5, 7 or 9). The remainder of the JTAG signals can
be left unconnected. By default the EVM is configured with 0 Ω option resistors R40 and R77 that connect
TRST and TCK to ground.
If boundary scan testing is needed, TI can provide the appropriate BDSL file upon request.
2.7
LEDs
The XIO2001 EVM has LEDs onboard to indicate availability of power and status of certain control signals.
The onboard LEDs are as follows:
• LED1: 5 V power indicator
• LED2: 3.3 V power indicator
• LED4: 12 V power indicator
• LED5: –12 V power indicator
6
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FAQ/Troubleshooting
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3
FAQ/Troubleshooting
To
•
•
•
use the EVM
Plug the PCI add-in cards into the EVM, oriented as indicated on the board
Place the EVM into a PCI express add-in slot
Turn the system on
From the operating system perspective, the XIO2001 appears to be a standard PCI-to-PCI bridge (PCI
header type 1) and the OS will configure the bridge and any devices behind the bridge accordingly using
legacy PCI configuration transactions. Following sections of this chapter describe issues that may impair
use of the bridge in a system.
3.1
BIOS Fails to Assign Memory Window to Bridge
Microsoft operating systems generally attempt to respect the resource allocations made by system BIOS.
The XIO2001 requires a memory window in order to access some registers used by the device. If the
Microsoft OS determines that the BIOS failed to assign a memory window to the XIO2001, it will assume
that one cannot be assigned and that the device is nonfunctional. The OS will then assume the bridge is
not functional and will not enumerate devices behind the bus. Consequently, these devices will never be
configured or assigned resources.
This failure can be determined by examining device manager in the OS. If failure has occurred, the bridge
will appear “banged out” and if the bridge properties are examined the OS will reveal this device cannot
find enough free resources that it can use. (Code 12) If you want to use this device, you will need to
disable one of the other devices on this system.
3.2
×16 Slots Only Support INTA
As the x16 PCI express add-in slots are designed as a graphics expansion port, many only support a
single interrupt (INTA ), as this is the only interrupt that will be required by a graphics card. The XIO2001
EVM supports all interrupts and balances interrupt loading by rotating the interrupts to each add-in slot as
required by the PCI Local Bus Specification. Accordingly, any PCI add-in card behind the bridge that
asserts an interrupt other than INTA will not be serviced as the interrupt is not supported by the chipset.
Consequently, the add-in card will fail. Any devices that do not require interrupts or that only assert INTA
(as routed to the specific slot they are placed in) will still function normally.
3.3
System Turns On When PCI Card Is Inserted Into EVM Or When EVM Is Plugged Into
Slot
As mentioned previously, PME is routed on the EVM to the various PCI slots through a reserved pin that
many PCI add-in cards use for this purpose. On occasion, when a PCI card is inserted into the EVM
(while the EVM is plugged into a board), the add-in card may be inserted in such a way as to pull the PME
line low on the EVM. When this happens, the XIO2001 sees a PCI device trying to wake the system and
will appropriately assert WAKE , which may cause the system to turn on.
Similarly, when the EVM is inserted into the slot, VAUX from the connector may not have had enough time
to pull the PME line high (as the on-board pullup resistors dictate), yet VAUX may have powered the
XIO2001 which now samples PME as low and again wakes the system. This is a limitation of the inability
to appropriately power the pullup resistors before the XIO2001 is powered. If this occurs, turn power to the
system off and reboot to ensure the EVM receives a clean reset from the system.
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FAQ/Troubleshooting
3.4
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What To Do If EVM Is Not Working
3.4.1
Check EVM Power
Diodes LED1, LED2, LED4 and LED5 show the status of the 5-V, 3.3-V, 12-V, and –12-V rails,
respectively. 1.5 V may be probed on the top pad of C44 (directly next to U3), and –12 V may be probed
from C100. A ground reference is available at J1 pin 11 and JP1 pins 2, 4, 6, 8 and 10. If any of these
voltages fail, a problem is likely to occur with EVM functionality. The XIO2001 requires 3.3 V and 1.5 V;
other voltages are supplied for use by PCI add-in cards, and PCI VIO is by default 5 V (which will cause
the entire PCI bus to be clamped to 0.7 V if this voltage is not present). If any of these voltages fail, it is
likely that the EVM won’t function because:
• XIO2001 will not be powered
• The add-in card will not be powered
• Neither the XIO2001 or the add-in card will be powered
All
•
•
•
3.4.2
voltages have resettable fuses to prevent overcurrent conditions, so if a particular power rail fails:
Detach all devices from the EVM
Remove the EVM from the system
Wait for 30 minutes before trying again
Check If Bridge Is Link Training
If the system does not boot, remove all PCI add-in cards from EVM and try again. If the system hangs
before the OS loads, then probably the system and the EVM are having difficulty completing link training (
probably an issue with signal integrity on the differential pairs). If a PCI Express analyzer is unavailable,
then try a different express slot or a different system if possible. Re-check the 1.5-V rail and examine the
differential clock on an oscilloscope to ensure it is clean.
If link training successfully completes, the system will boot and the XIO2001 will appear in the device
manager. If the bridge does not appear in the device manager, then the system may not have detected
the presence of the bridge, perform the previous checks again.
Also, if the PCI add-in cards have enough weight and there is no mechanical support, the EVM may flex
and some components may crack or become disconnected. Check the coupling capacitors on the EVM
transmit lines (C102 and C103). These 0.1-μF 0402 components have a tendency to crack if enough
weight is put on the board; they will need to be replaced if they are damaged.
3.4.3
Check If Bridge Has Been Configured
Once the bridge is communicating with the system, the BIOS and/or the OS are expected to configure the
bridge for proper operation. As the bridge appears to software to be a standard PCI-to-PCI bridge, most
existing BIOS and OS software must be capable of configuring the bridge with no special considerations
for PCI Express. In addition to the memory window the bridge requests for internal resources, the
following items are required for bridge operation:
• Command register – PCI offset 0×4 : The bus master enable (bit 2), memory enable (bit 1), and I/O
enable (bit 0) must be set to enable the bridge to send upstream transactions.
• Cache line size register – PCI offset 0×C : Must be set to the cache line size for the system. Failure to
set this bit will not cause the bridge to fail but will cause the bridge to limit all upstream transactions to
1 DWord.
• Primary, secondary, and subordinate bus numbers– PCI offsets 0×18, 0×19, and 0×1A : The bridge
must have the bus numbers configured so that it can determine which transactions are targeting the
bridge, which transactions are targeting devices directly attached to the bridge, and which transactions
are farther downstream from the bridge.
• I/O base and limit registers and I/O base upper 16 bits and I/O limit upper 16 bits registers –PCI offsets
0×1C, 0×1D, 0×30 and 0×32: If any devices downstream from the bridge require I/O resources, the
bridge must be programmed with a window that contains the I/O resources of all devices downstream.
Failure to program these windows will cause the bridge to respond to I/O transactions with a response
of Unsupported Request. Any transactions initiated on the secondary side of the bus that fall within this
8
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Schematics
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•
•
•
range will not be claimed by the bridge. The I/O window for the XIO2001 has a minimum size of 4
KBytes and is naturally 4K-aligned. Typically, most systems use only 16-bit addressing for I/O
transactions, so the upper base and limit registers remain 0.
Memory base and memory limit registers – PCI offsets 0×20 and 0×22 : Similar to the I/O base and
limit registers, the bridge must be programmed with a memory address window containing the
nonprefetchable memory resources of all downstream PCI devices requiring nonprefetchable memory.
Memory windows have a minimum size of 1 MByte and are naturally 1M-aligned. The bridge does not
claim either a memory transaction initiated from upstream that does not fall within its memory window
nor memory transactions initiated downstream that do fall within its memory window.
Prefetchable memory base, prefetchable memory limit, prefetchable base upper 32-bit, and
prefetchable limit upper 32-bit registers – PCI offsets 0x24, 0x26, 0x28, and 0×2C: Identical to the
memory base and limit registers but for prefetchable memory resources. The prefetchable base upper
32-bit, and prefetchable limit upper 32-bit registers are only used if 64-bit addressing is in use and in
most systems both of these registers will remain all zeroes. If 64-bit addressing is desired and the
memory window for devices behind the XIO2001 resides all or in part in 64-bit memory space then the
prefetchable base upper 32-bit register will combine with the prefetchable base register and the
prefetchable limit upper 32-bit register will combine with the prefetchable limit register to create 64-bit
base and limit registers. All memory addresses between the two addresses will be considered to be
located behind the bridge.
For all base and limit registers any case in which the limit register contains a lower address than the
base register will be considered invalid. In this situation the bridge will react as if all resources of that
type resided upstream of the bridge. The bridge will respond to all downstream transactions of that
type with Unsupported Request and will claim and forward upstream any transactions of that type that
initiate on the PCI bus.
Depending on desired functionality, other PCI registers on the XIO2001 may have to be configured.
Consult the XIO2001 Data Manual for a description of the previous registers or for any other XIO2001
registers.
3.4.4
Check Devices Downstream From Bridge
Once the bridge is communicating and is properly configured, check if devices downstream from the
bridge have been configured as required. Check the Windows Device Manager to determine if the device
drivers have been loaded or if other problems exist with the device. Once you have performed these
checks, you can perform PCI transactions on the bus and examine them with any standard PCI analyzer.
4
Schematics
Schematics for the XIO2001 EVM are shown on the following pages.
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Schematics
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XVDDA_3.3V
XPCI_VIO_1
XPCI_VIO_2
XDVcc_1.5V
cc0402
C2
10nF
cc0402
C3
1000pF
R71
0
RR0805
XVaux
J9
Head 2x1
DNA
1
ECJ0EB1C103K
P1_REQ64#
P2_REQ64#
P3_REQ64#
PCI_ACK64#
2
ECJ-0EB1H102K
C1
cc0402
GRM155R61A105JE15D
1uF
Pull Ups/Pull Downs
Bridge Power
Filtering/Decoupling
DVcc_1.5V
XVDDA_1.5V
XVDD15_PLL
XDVcc_3.3V
XIO2001
N9
M9
N10
N11
M10
L12
N13
N8
A13
C10
REFCLK_SEL
PCLK66_SEL
B13
B12
GRST#
3
3
H11
M13
PERST#
WAKE#
3
3
RR0805
R32
RR0805
R33
14.3K
232
C12
C13
ClkClk+
RXn
RXp
3
3
TXn
TXp
RXn
RXp
E12
E13
TXn
TXp
G12
G13
INTA#
INTB#
INTC#
INTD#
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKOUT6
CLKREQ#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
REQ5#
REFCLK125_SEL
PCLK66_SEL
PERST#
WAKE#
REF0_PCIE
REF1_PCIE
REFCLKREFCLK+
RXN
RXP
PCIE
3
3
K12
K13
PME#
GRST#
SERIRQ
CLKRUN_EN
EXT_ARB_EN
CLK
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
PERR#
SERR#
PRST#
M66EN
LOCK#
Misc
CLKRUN_EN
EXTARB_EN
PCI_PME#
SERIRQ
GPIO0_CLKRUN#
GPIO1_PWR_OVER
GPIO2
GPIO3_SDA
GPIO4_SCL
ZGU
CLOCKS/ARBITER
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
GPIO
M12
N12
M11
L10
L9
JTAG
3,4
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTN
C/BE#0
C/BE#1
C/BE#2
C/BE#3
TXN
TXP
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
GNT5#
cc0402
M6
N6
M7
L7
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
B5
B6
A7
B7
A9
A10
B11
D11
A4
A6
A8
C8
C9
A12
PCI_PCLK0
PCI_PCLK1
PCI_PCLK2
A5
C6
B8
B9
A11
B10
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_VIO
DNA
PXVDDA_3.3V
BLM21B
ECJ-2VB1C104K
cc0805
C16
0.1uF
C17
1000pF
cc0402
C18
0.1uF
C19
0.1uF
PCI_M66EN
PCI_REQ#3
PCI_PRST#
PCI_ACK64#
746_SERIES
4
4
4
4
PCI_PCLK[2..0]
R73
0
RR0805
4
J11
Head 2x1
DNA
R1
COM2
R2
R8
R3
R7
R4
R6
COM1
R5
10
9
8
7
6
PCI_REQ#1
PCI_INTD#
PCI_REQ#2
746_SERIES
R8
XDVcc_3.3V
1
2
3
4
5
PCI_IRDY#
PCI_DEVSEL#
C21
C22
C23
C24
C25
C26
C27
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C29
0.1uF
C30
0.1uF
C31
0.1uF
PCI_PERR#
R1
COM2
R2
R8
R3
R7
R4
R6
COM1
R5
10
9
8
7
6
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_SERR#
746_SERIES
DVcc_1.5V
R81
0
RR0805
4
J13
Head 2x1
Vaux
DNA
XVDD15_PLL
220Ohm 200mA
PCI_FBCLK
CLKREQ#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_REQ#5
PCI_REQ#[2..0]
4
1000pF
C40
C41
0.1uF
cc0805
cc0402
ECJ-0EB1A104K
C28
0.1uF
cc0402
C45
0.1uF
R11
10.0K
DNA
C46
0.1uF
PCI_VIO
PCI_GNT#[2..0]
R12
10.0K
R25
10K
RR0805
PCI_PME#
CLKREQ#
VREG_PD33
4
4
DVcc_1.5V
R75
1K
RR0805
R62
10.0K
R80
1K
RR0805
R63
10.0K
DNA
XPCI_VIO_2
XPCI_VIO_1
DNA
C32
0.1uF
1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSSA_1
VSSA_2
VSSA_3
VSSA_4
VSSA_5
VSSA_6
VSSA_7
J12
Head 2x1
C33
0.1uF
ECJ-0EB1H102K
XDVcc_1.5V
DVcc_3.3V
D4
F4
H4
K4
K5
K6
K8
L11
J10
D10
D8
D6
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
G5
G6
G7
G8
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
J9
F12
K10
C11
H12
G11
E11
E10
F11
cc0402
C35
0.1uF
C36
0.1uF
C37
0.1uF
C38
1000pF
cc0402
Vaux
R13
10.0K
2
C34
0.1uF
J14
Head 2x1
R21
10K
RR0805
R22
10K
RR0805
R23
10.0K
R24
10.0K
DNA
DNA
DNA
1
CLKRUN_EN
EXTARB_EN
PCI_REQ#4
PCI_REQ#5
PCLK66_SEL
XVaux
C20
0.1uF
R79
10.0K
JTAG
R10
10.0K
RR0603
DNA
SERIRQ
REFCLK_SEL
U2
1
2
3
4
A0
A1
A2
VSS
VCC
WP
SCL
SDA
8
7
6
5
WP
24LC08B
R20
10K
RR0805
RR0402
R28
GPIO4
0 GPIO3
R29 0 RR0402
R42
R39
R41
R43
10K
10K
10K
10K
RR0805 RR0805 RR0805 RR0805
DNA
PM3705 CONNECTOR
DNA
JP1
1
3
5
7
9
JTAG_TRSTN
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK
C39
0.1uF
R40
0
RR0805
10
1
2
3
4
5
10
9
8
7
6
R78
10.0K
J1
Head 2x6
PCI_REQ#0
PCI_INTC#
PCI_INTA#
PCI_INTB#
R1
COM2
R2
R8
R3
R7
R4
R6
COM1
R5
R7
PCI_3.3V
GPIO1
GPIO3
CLKREQ#
PCI_PME#
PCLK66_SEL
1
2
3
4
5
DVCC_3.3V
DVCC_3.3V
2
4
6
8
10
12
P1_REQ64#
P2_REQ64#
PCI_LOCK#
P3_REQ64#
DVcc_3.3V
NOTE: Place decoupling
caps as close as
possible to associated
power terminals on U1.
1
3
5
7
9
11
4
R6
ECJ-0EB1H102K
XVDDA_3.3V
R76
0
RR0805
GPIO0
GPIO2
GPIO4
PERST#
GRST#
GPIO4
PCLK66_SEL
2
J10
Head 2x1
L2
R74
0
RR0805
EEPROM
10
9
8
7
6
L3
GND
MISC
R1
COM2
R2
R8
R3
R7
R4
R6
COM1
R5
746_SERIES
R72
0
RR0805
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
RR0402
R26
PCI_FBCLK
49.9
PCI_FRAME#
4
PCI_IRDY#
4
PCI_TRDY#
4
PCI_DEVSEL# 4
PCI_STOP#
4
PCI_PAR
4
PCI_PERR#
4
PCI_SERR#
4
PCI_PRST#
4
PCI_M66EN
4
PCI_LOCK#
4
F3
J2
J1
H1
H2
G1
F1
G2
G3
N7
L6
M8
R1
1
2
3
4
5
GPIO0
GPIO1
GPIO2
GPIO3
DVCC_3.3V
PCI_C/BE#[3..0]
B1
F2
J3
N1
C9
C8
0.1uF 0.1uF
C7
0.1uF
1
ECJ-0EB1H102K
C15
1000pF
cc0402
C14
10nF
PCI
cc0402
ECJ-0EB1A104K
C6
0.1uF
cc0402
1000pF
C5
C4
0.1uF
2
ECJ0EB1C103K
DVcc_3.3V
BLM21B
ECJ-2VB1C104K
cc0805
1
POWER
cc0402
C13
GRM155R61A105JE15D
1uF
ECJ-0EB1H102K
XVDDA_1.5V
PXVDDA_1.5V
4
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
2
J11
D12
VREG_PD33
Misc
C5
A3
B4
B3
A2
C4
B2
C3
D3
C2
C1
D2
D1
E3
E2
E1
K1
K2
L1
L2
M1
L3
M2
L4
M3
N2
M4
N3
M5
L5
N4
N5
1
3.3V
L1
PCI_AD[31..0]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
2
Analog
1.5V 3.3V
VDD_33_AUX
D13
A1
K3
PCIR
PCIR
F13
H13
F10
G4
K7
D7
H10
G10
E4
H3
J4
L8
K9
D9
C7
D5
J12
1.5V
VDDA_33
VDDA_15_1
VDDA_15_2
ECJ-0EB1H102K
VDDPLL_15
1uF
cc0402
C12
1000pF
VDD_15_1
VDD_15_2
VDD_15_3
VDD_15_4
VDD_15_PCIE
GRM155R61A105JE15D
ECJ0EB1C103K cc0402
C11
10nF
VDD_15_COMB
VDD_33_COMBIO
VDD_33_COMB
C10
VDD_33_1
VDD_33_2
VDD_33_3
VDD_33_4
VDD_33_5
VDD_33_6
VDD_33_7
VDD_33_8
VDD_33_9
L13
K11
J13
VREG_PD33
U6
cc0402
XIO2001 Evaluation Module (EVM)
R61
10K
RR0805
R19
10K
RR0805
2
4
6
8
10
Conn 2x5 shroud
2510-6002UB
R77
0
RR0805
SCPU031B – February 2009 – Revised June 2014
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Schematics
www.ti.com
Vaux
PCI_12V
PCI_3.3V
C106
P1
Edge PCI Express
C105
lms_folly
U5
PERST#
F5
PolySwitch Fuses
SMD250
2
R67
10.0
C104
0.1UF
cc0603
RXp
RXn
PRESENT#
RSVD#B12
GND#B13
RXP0
RXN0
GND#B16
PRSNT2Z
GND#B18
GND#A12
REFCLKP
REFCLKN
GND#A15
TXP0
TXN0
RSVD#A18
Side B
Component Side
POWER LEDs
Side A
Solder
Side
Clk+
ClkCTXp
CTXn
C102
0.1uF cc0402
C103 TXn
0.1uF cc0402
R69
VIN VREF
EN
FB
PS_GND
OUT
IN
SW
GNDCOMP
2
2
TXp
2
TXn
10
9
8
6
1
TPS63700
R70
100K
10pF
1.2M
2
1
SL03
-12V_in
4
D2
C100
4x4.7uF
L4
10 uH
C101
4.7nF
11
2
2
A12
A13
A14
A15
A16
A17
A18
3
4
7
5
2
PWR_PAD
Key
B12
B13
B14
B15
B16
B17
B18
R68
121K
0.22uF
PRESENT#
1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
1
PRSNT1Z
12V#A2
12V#A3
GND#A4
J_TCK
J_TDI
J_TDO
J_TMS
3_3V#A9
3_3V#A10
PWRGD
2
WAKE#
12V#B1
12V#B2
RSVD#B3
GND#B4
SMCLK
SMDAT
GND#B7
3_3V#B8
J_TRSTZ
3_3VAUX
WAKEZ
2
2
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
DVcc_5.0V
C99
10uF
2
Power
DVCC_3.3V
LED2 Red
1
2
R36
RR0402
332
eprt-leds-00003-0000
SML-LXT0805IW -TR
LED0805
DVCC_5.0V
EVM_12V
DVCC_3.3V
PCI_3.3V
F2
R34
RR0402
332
1
eprt-leds-00003-0000
SML-LXT0805IW -TR
LED0805
2
R38
10.0K
PolySwitch Fuses
1
2
3
4
1
2
3
4
C44
10uF
U3
C42
10uF
J8
F1
PolySwitch Fuses
EVM_12V
1
2
3
4
5
ENABLE
IN
GND GND
OUT
RESET
6
TPS72615DCQ
Power Connector 4pin
2
R37
RR0402
1.00K
1
LED4 Red
1
F3
PolySwitch Fuses
2
2
2
1
DVCC_3.3V
1
DVCC_1.5V
LED1 Red
1
DVCC_5.0V
C43
C50
10uF
C107
10uF
+
100uF
2
eprt-leds-00003-0000
SML-LXT0805IW -TR
LED0805
-12V_in
LED5
2
1
R44
RR0402
1.00K
Red
eprt-leds-00003-0000
SML-LXT0805IW -TR
LED0805
SCPU031B – February 2009 – Revised June 2014
Submit Documentation Feedback
XIO2001 Evaluation Module (EVM)
Copyright © 2009–2014, Texas Instruments Incorporated
11
Schematics
EVM_12V
www.ti.com
DVCC_5.0V
DVCC_3.3V
EVM_12V
DVCC_5.0V
DVCC_3.3V
EVM_12V
DVCC_5.0V
DVCC_3.3V
P2
C51
P3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
0.1uF cc0402
Vaux
PCI_INTA#
PCI_INTC#
R50
0
RR0805
PCI_VIO
PCI_PRST#
PCI_GNT#0
PCI_AD30
R55
0
RR0805
PCI_PME#
PCI_AD28
PCI_AD26
PCI_AD24
IDSEL0
PCI_AD22
PCI_AD20
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
PCI_C/BE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
2
P1_REQ64#
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED_5
+V I/O_4
RESERVED_4
GND
GND
RESERVED_3
RST#
+V I/O_3
GNT#
GND
RESERVED_2
AD[30]
+3.3V
AD[28]
AD[26]
GND
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
GND
AD[18]
AD[16]
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD[15]
+3.3V
AD[13]
AD[11]
GND
AD[09]
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RESERVED_0
PRSNT2#
GND
GND
RESERVED_1
GND
CLK
GND
REQ#
+V I/O_0
AD[31]
AD[29]
GND
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
GND
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE[1]#
AD[14]
GND
AD[12]
AD[10]
M66EN
C/BE[0]#
+3.3V
AD[06]
AD[04]
GND
AD[02]
AD[00]
+V I/O_2
REQ64#
+5V
+5V
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
GND
AD[01]
+V I/O_1
ACK64#
+5V
+5V
Solder Side
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
-12V_in
-12V_in
C52
3
0.1uF cc0402
Vaux
PCI_INTB#
PCI_INTD#
PCI_INTB#
PCI_INTD#
R51
0 PCI_VIO
RR0805
PCI_PCLK0
PCI_PRST#
PCI_REQ#0
PCI_VIO
PCI_AD31
PCI_AD29
R53
0
PCI_GNT#1
PCI_PME#
RR0805
PCI_AD30
PCI_AD27
PCI_AD25
PCI_AD28
PCI_AD26
PCI_C/BE#3
PCI_AD23
PCI_AD24
IDSEL1
PCI_AD21
PCI_AD19
PCI_AD22
PCI_AD20
PCI_AD17
PCI_C/BE#2
PCI_AD18
PCI_AD16
PCI_IRDY#
PCI_FRAME#
PCI_DEVSEL#
PCI_TRDY#
PCI_LOCK#
PCI_PERR#
PCI_STOP#
PCI_SERR#
PCI_C/BE#1
PCI_AD14
PCI_PAR
PCI_AD15
PCI_AD12
PCI_AD10
PCI_M66EN
PCI_AD13
PCI_AD11
PCI_AD9
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PCI_AD8
PCI_AD7
PCI_C/BE#0
PCI_AD5
PCI_AD3
PCI_AD6
PCI_AD4
PCI_AD1
PCI_AD2
PCI_AD0
PCI_ACK64#
2
2
Component Side
P4
P2_REQ64#
C53
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED_5
+V I/O_4
RESERVED_4
GND
GND
RESERVED_3
RST#
+V I/O_3
GNT#
GND
RESERVED_2
AD[30]
+3.3V
AD[28]
AD[26]
GND
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
GND
AD[18]
AD[16]
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD[15]
+3.3V
AD[13]
AD[11]
GND
AD[09]
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RESERVED_0
PRSNT2#
GND
GND
RESERVED_1
GND
CLK
GND
REQ#
+V I/O_0
AD[31]
AD[29]
GND
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
GND
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE[1]#
AD[14]
GND
AD[12]
AD[10]
M66EN
C/BE[0]#
+3.3V
AD[06]
AD[04]
GND
AD[02]
AD[00]
+V I/O_2
REQ64#
+5V
+5V
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
GND
AD[01]
+V I/O_1
ACK64#
+5V
+5V
Solder Side
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
-12V_in
0.1uF cc0402
Vaux
PCI_INTC#
PCI_INTA#
PCI_INTC#
PCI_INTA#
R52
0
RR0805
PCI_VIO
PCI_PRST#
PCI_PCLK1
PCI_REQ#1
PCI_VIO
PCI_AD31
PCI_AD29
R54
0
PCI_GNT#2
RR0805
PCI_AD30
PCI_PME#
PCI_AD28
PCI_AD26
PCI_AD27
PCI_AD25
PCI_AD24
IDSEL2
PCI_C/BE#3
PCI_AD23
PCI_AD22
PCI_AD20
PCI_AD21
PCI_AD19
PCI_AD18
PCI_AD16
PCI_AD17
PCI_C/BE#2
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_LOCK#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_AD15
PCI_C/BE#1
PCI_AD14
PCI_AD13
PCI_AD11
PCI_AD12
PCI_AD10
PCI_M66EN
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PCI_AD9
PCI_AD8
PCI_AD7
PCI_C/BE#0
PCI_AD6
PCI_AD4
PCI_AD5
PCI_AD3
PCI_AD2
PCI_AD0
PCI_AD1
PCI_ACK64#
Component Side
2
P3_REQ64#
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED_5
+V I/O_4
RESERVED_4
GND
GND
RESERVED_3
RST#
+V I/O_3
GNT#
GND
RESERVED_2
AD[30]
+3.3V
AD[28]
AD[26]
GND
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
GND
AD[18]
AD[16]
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD[15]
+3.3V
AD[13]
AD[11]
GND
AD[09]
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RESERVED_0
PRSNT2#
GND
GND
RESERVED_1
GND
CLK
GND
REQ#
+V I/O_0
AD[31]
AD[29]
GND
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
GND
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE[1]#
AD[14]
GND
AD[12]
AD[10]
M66EN
C/BE[0]#
+3.3V
AD[06]
AD[04]
GND
AD[02]
AD[00]
+V I/O_2
REQ64#
+5V
+5V
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
GND
AD[01]
+V I/O_1
ACK64#
+5V
+5V
Solder Side
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
-12V_in
PCI_INTD#
PCI_INTB#
PCI_PCLK2
PCI_REQ#2
PCI_VIO
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_C/BE#3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_C/BE#2
PCI_IRDY#
PCI_DEVSEL#
PCI_LOCK#
PCI_PERR#
PCI_SERR#
PCI_C/BE#1
PCI_AD14
PCI_AD12
PCI_AD10
PCI_M66EN
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
PCI_ACK64#
2
Component Side
PCI 5V Conn
PCI 5V Conn
12
PCI_AD[31..0]
PCI_C/BE#[3..0]
PCI_REQ#[2..0]
PCI_GNT#[2..0]
PCI_PCLK[2..0]
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_PRST#
PCI_M66EN
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PCI_LOCK#
PCI_PME#
2
2,3
C54
0.1uF
cc0402
C55
0.1uF
cc0402
C56
0.1uF
cc0402
C63
0.1uF
cc0402
C64
0.1uF
cc0402
C65
0.1uF
cc0402
C66
0.1uF
cc0402
C81
0.1uF
cc0402
C82
0.1uF
cc0402
C83
0.1uF
cc0402
C84
0.1uF
cc0402
C67
0.1uF
cc0402
C85
0.1uF
cc0402
C68
0.1uF
cc0402
C86
0.1uF
cc0402
PCI 5V Conn
C57
0.1uF
cc0402
C58
0.1uF
cc0402
C59
0.1uF
cc0402
C74
0.1uF
cc0402
C69
0.1uF
cc0402
C70
0.1uF
cc0402
C71
0.1uF
cc0402
C92
0.1uF
cc0402
C87
0.1uF
cc0402
C88
0.1uF
cc0402
C89
0.1uF
cc0402
C72
0.1uF
cc0402
C90
0.1uF
cc0402
C60
0.1uF
cc0402
C61
0.1uF
cc0402
C62
0.1uF
cc0402
C73
0.1uF
cc0402
C80
0.1uF
cc0402
C75
0.1uF
cc0402
C76
0.1uF
cc0402
C77
0.1uF
cc0402
C91
0.1uF
cc0402
C98
0.1uF
cc0402
C93
0.1uF
cc0402
C94
0.1uF
cc0402
C95
0.1uF
cc0402
C78
0.1uF
cc0402
C96
0.1uF
cc0402
C79
0.1uF
cc0402
C97
0.1uF
cc0402
2
2
2
2
2
DVCC_5.0V
DVCC_3.3V
DNA
R56
0
RR0603
R57
0
RR0603
PCI_VIO
PCI_AD16
PCI_AD17
PCI_AD18
R58
100
RR0805
R59
100
RR0805
R60
100
RR0805
2
IDSEL0
IDSEL1
IDSEL2
XIO2001 Evaluation Module (EVM)
SCPU031B – February 2009 – Revised June 2014
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Copyright © 2009–2014, Texas Instruments Incorporated
Bill of Materials
www.ti.com
5
Bill of Materials
Evaluation board bill of materials as assembled. Unused options (e.g., 3.3-V VIO) are not populated and not listed.
SCPU031B – February 2009 – Revised June 2014
Submit Documentation Feedback
XIO2001 Evaluation Module (EVM)
Copyright © 2009–2014, Texas Instruments Incorporated
13
Bill of Materials
www.ti.com
Bill of Materials
ITEM
QTY
1
3
C1, C10, C13
1 μF
Murata
GRM155R61A105JE15D
cc0402
2
3
C2, C11, C14
10 nF
Panasonic
ECJ0EB1C103K
cc0402
3
4
C3, C12, C15, C38
1000 pF
Panasonic
ECJ-0EB1H102K
cc0402
4
2
C4, C16
0.1 μF
Panasonic
ECJ-2VB1C104K
cc0805
5
2
C5, C17
0.001 μF
Panasonic
ECH-U1H102JB5
cc0805
6
72
C6, C7, C8, C9, C18, C19,
C20, C21, C22, C23, C24,
C25, C26, C27, C29, C3,
C31, C32, C33, C34, C35,
C36, C37, C39, C51, C52,
C53, C54, C55, C56, C57,
C58, C59, C60, C61, C62,
C63, C64, C65, C66, C67,
C68, C69, C70, C71 C72,
C73, C74 C75, C76, C77,
C78, C79, C80 C81, C82,
C83, C84, C85, C86, C87,
C88, C89, C90 C91, C92,
C93, C94 C95, C96, C97,
C98
0.1 μF
Panasonic
ECJ-0EB1A104K
cc0402
7
6
C42, C44, C50, C99, C100,
C101
10 μF
Panasonic
ECJ-2FB1A106K
cc0805
8
1
C43
100 μF
Panasonic
ECA1EHG101
THCap_2P5MM
9
3
C45, C48, C49
22 μF
AVX
TAJC226K016R
cc6032
10
2
C46, C47
0.047 μF
Panasonic
ECJ1VB1C473K
cc0603
11
3
C102, C103, C104
0.1 μF
Kemet
C0603C104M4RACTU
cc0603
12
1
C105
10 pF
TDK
C1608C0G1H100DB
cc0603
13
1
C106
0.22 μF
Panasonic
ECJ1VB1A224K
cc0603
14
1
D1
MBRD835L
Diodes, Inc.
MBRD835L
DPAK_4
15
1
D2
SL03
Vishay
SL03D0-219AB-GS08
sl03_schottky_diode
16
4
F1, F2, F3, F5
Polyswitch fuses
Tyco Electronics
SMD250
SMD250
17
1
J1
Head 2 × 6
Berg
54102-T32-05
HDR_6X2
18
1
JP1
Conn 2 × 5 shroud
3M
2510-6002UB
eprt-conn-00002-0001
19
2
L1, L2
BLM21B
MuRata
BLM21BB221SN1
cc0805
20
1
L3
10 μH
Coiltronics
UP4B-100-R
IND_UP4B_100_R
21
1
L4
10 μH
Sumida
CDRH5D18NP-100NC
CDRH5D18
22
4
LED1, LED2, LED3, LED4
Red Lumex
Lumex
SML-LXT0805IW-TR
LED0805
23
1
LED5
Green
Lumex
SML-LXT0805GW-TR
LED0805
24
2
LED6, LED7
Yellow
Lumex
SML-LXT0805YW-TR
LED0805
25
1
P1
Edge PCI Express
DNA
eprt-conn- 00023-0000
26
3
P2, P3, P4
PCI 5 V conn
Tyco Electronics
145154-8
Conn_PCI_60_Dual
27
4
R1, R6, R7, R8
746_SERIES
CTS
746X101103JCT-ND?
10Pin_8Res
10K
Panasonic
ERJ6ENF1002V
RR0805
28
14
R2, R3, R4, R5, R19, R20,
R21, R22, R25, R39, R41,
R42, R43, R61
29
9
R10, R11, R12, R13, R23,
R24, R38, R62, R63
10.0K
Panasonic
ERJ3EKF1002V
RR0603
30
2
R26, R35
49.9
Panasonic
ERJ2RKF49R9X
RR0402
31
2
R28, R29
0
Panasonic
ERJ2GE0R00X
RR0402
32
1
R32
14.3K
Panasonic
ERJ6ENF1432V
RR0805
33
1
R33
232
Panasonic
ERJ6ENF2320V
RR0805
34
2
R34,R36
332
Panasonic
ERJ2GEJ3320X
RR0402
35
1
R37
Conn 2 × 5 shroud
Panasonic
ERJ2RKF1001V
RR0402
36
7
R40, R50, R51, R52, R53,
R54, R55
0
Panasonic
ERJ6ENF0000V
RR0805
37
1
R45
18.7K
Panasonic
ERJ6ENF1872V
RR0805
38
1
R47
6.19K
Panasonic
ERJ6ENF6191V
RR0805
39
1
R49
2K
Panasonic
ERJ6ENF2001V
RR0805
14
REFERENCE
XIO2001 Evaluation Module (EVM)
VALUE
MFR
PART NO.
PACKAGE
SCPU031B – February 2009 – Revised June 2014
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Copyright © 2009–2014, Texas Instruments Incorporated
Revision History
www.ti.com
Bill of Materials (continued)
ITEM
QTY
40
2
R56, R57
REFERENCE
0
VALUE
Panasonic
MFR
ERJ3GEY0R00V
PART NO.
RR0603
PACKAGE
41
3
R58, R59, R60
100
Panasonic
ERJ6ENF1000V
RR0805
42
3
R64, R65, R66
332
Panasonic
ERAV39J3320V
RR0603
43
1
R67
10.0
Panasonic
ERJ2RKF10R0V
RR0402
44
1
R68
121K
Panasonic
ERJ2RKF1213X
RR0402
45
1
R69
1.2M
Vishay
CRCW0603
RR0603
46
1
R70
100K
Panasonic
ERJ2RKF1003V
RR0402
47
1
U2
24LC08B
Microchip
24LC08BIST
TSSOP_8_122X177_ 26
48
1
U3
TPS72615DCQ
Texas Instruments
TPS72615DCQ
TO_263_6_DCQ
49
1
U4
LT1370
Linear Technology
LT1370CR
DDPAK_R_7
50
1
U5
TPS63700
Texas Instruments
TPS63700DRCT
DRC_S_PVSON_N10
51
1
U6
XIO2001_ZAJ
Texas Instruments
XIO2001ZAJ
bga144ZAJ_0p5mm_
socket
Revision History
Changes from A Revision (February 2009) to B Revision ............................................................................................. Page
•
•
•
Changed schematics to rev. D. ........................................................................................................ 10
Changed schematics to rev. D. ........................................................................................................ 11
Changed schematics to rev. D. ........................................................................................................ 12
SCPU031B – February 2009 – Revised June 2014
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Copyright © 2009–2014, Texas Instruments Incorporated
Revision History
15
ADDITIONAL TERMS AND CONDITIONS, WARNINGS, RESTRICTIONS, AND DISCLAIMERS FOR
EVALUATION MODULES
Texas Instruments Incorporated (TI) markets, sells, and loans all evaluation boards, kits, and/or modules (EVMs) pursuant to, and user
expressly acknowledges, represents, and agrees, and takes sole responsibility and risk with respect to, the following:
1.
User agrees and acknowledges that EVMs are intended to be handled and used for feasibility evaluation only in laboratory and/or
development environments. Notwithstanding the foregoing, in certain instances, TI makes certain EVMs available to users that do not
handle and use EVMs solely for feasibility evaluation only in laboratory and/or development environments, but may use EVMs in a
hobbyist environment. All EVMs made available to hobbyist users are FCC certified, as applicable. Hobbyist users acknowledge, agree,
and shall comply with all applicable terms, conditions, warnings, and restrictions in this document and are subject to the disclaimer and
indemnity provisions included in this document.
2. Unless otherwise indicated, EVMs are not finished products and not intended for consumer use. EVMs are intended solely for use by
technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical
mechanical components, systems, and subsystems.
3. User agrees that EVMs shall not be used as, or incorporated into, all or any part of a finished product.
4. User agrees and acknowledges that certain EVMs may not be designed or manufactured by TI.
5. User must read the user's guide and all other documentation accompanying EVMs, including without limitation any warning or
restriction notices, prior to handling and/or using EVMs. Such notices contain important safety information related to, for example,
temperatures and voltages. For additional information on TI's environmental and/or safety programs, please visit www.ti.com/esh or
contact TI.
6. User assumes all responsibility, obligation, and any corresponding liability for proper and safe handling and use of EVMs.
7. Should any EVM not meet the specifications indicated in the user’s guide or other documentation accompanying such EVM, the EVM
may be returned to TI within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE
EXCLUSIVE WARRANTY MADE BY TI TO USER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR
STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. TI SHALL
NOT BE LIABLE TO USER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES RELATED TO THE
HANDLING OR USE OF ANY EVM.
8. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which EVMs might be or are used. TI currently deals with a variety of customers, and therefore TI’s arrangement with
the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services with respect to the handling or use of EVMs.
9. User assumes sole responsibility to determine whether EVMs may be subject to any applicable federal, state, or local laws and
regulatory requirements (including but not limited to U.S. Food and Drug Administration regulations, if applicable) related to its handling
and use of EVMs and, if applicable, compliance in all respects with such laws and regulations.
10. User has sole responsibility to ensure the safety of any activities to be conducted by it and its employees, affiliates, contractors or
designees, with respect to handling and using EVMs. Further, user is responsible to ensure that any interfaces (electronic and/or
mechanical) between EVMs and any human body are designed with suitable isolation and means to safely limit accessible leakage
currents to minimize the risk of electrical shock hazard.
11. User shall employ reasonable safeguards to ensure that user’s use of EVMs will not result in any property damage, injury or death,
even if EVMs should fail to perform as described or expected.
12. User shall be solely responsible for proper disposal and recycling of EVMs consistent with all applicable federal, state, and local
requirements.
Certain Instructions. User shall operate EVMs within TI’s recommended specifications and environmental considerations per the user’s
guide, accompanying documentation, and any other applicable requirements. Exceeding the specified ratings (including but not limited to
input and output voltage, current, power, and environmental ranges) for EVMs may cause property damage, personal injury or death. If
there are questions concerning these ratings, user should contact a TI field representative prior to connecting interface electronics including
input power and intended loads. Any loads applied outside of the specified output range may result in unintended and/or inaccurate
operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the applicable EVM user's guide prior
to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During
normal operation, some circuit components may have case temperatures greater than 60°C as long as the input and output are maintained
at a normal ambient operating temperature. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors which can be identified using EVMs’ schematics located in the applicable EVM user's guide. When
placing measurement probes near EVMs during normal operation, please be aware that EVMs may become very warm. As with all
electronic evaluation tools, only qualified personnel knowledgeable in electronic measurement and diagnostics normally found in
development environments should use EVMs.
Agreement to Defend, Indemnify and Hold Harmless. User agrees to defend, indemnify, and hold TI, its directors, officers, employees,
agents, representatives, affiliates, licensors and their representatives harmless from and against any and all claims, damages, losses,
expenses, costs and liabilities (collectively, "Claims") arising out of, or in connection with, any handling and/or use of EVMs. User’s
indemnity shall apply whether Claims arise under law of tort or contract or any other legal theory, and even if EVMs fail to perform as
described or expected.
Safety-Critical or Life-Critical Applications. If user intends to use EVMs in evaluations of safety critical applications (such as life support),
and a failure of a TI product considered for purchase by user for use in user’s product would reasonably be expected to cause severe
personal injury or death such as devices which are classified as FDA Class III or similar classification, then user must specifically notify TI
of such intent and enter into a separate Assurance and Indemnity Agreement.
RADIO FREQUENCY REGULATORY COMPLIANCE INFORMATION FOR EVALUATION MODULES
Texas Instruments Incorporated (TI) evaluation boards, kits, and/or modules (EVMs) and/or accompanying hardware that is marketed, sold,
or loaned to users may or may not be subject to radio frequency regulations in specific countries.
General Statement for EVMs Not Including a Radio
For EVMs not including a radio and not subject to the U.S. Federal Communications Commission (FCC) or Industry Canada (IC)
regulations, TI intends EVMs to be used only for engineering development, demonstration, or evaluation purposes. EVMs are not finished
products typically fit for general consumer use. EVMs may nonetheless generate, use, or radiate radio frequency energy, but have not been
tested for compliance with the limits of computing devices pursuant to part 15 of FCC or the ICES-003 rules. Operation of such EVMs may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: For EVMs including a radio, the radio included in such EVMs is intended for development and/or
professional use only in legally allocated frequency and power limits. Any use of radio frequencies and/or power availability in such EVMs
and their development application(s) must comply with local laws governing radio spectrum allocation and power limits for such EVMs. It is
the user’s sole responsibility to only operate this radio in legally acceptable frequency space and within legally mandated power limitations.
Any exceptions to this are strictly prohibited and unauthorized by TI unless user has obtained appropriate experimental and/or development
licenses from local regulatory authorities, which is the sole responsibility of the user, including its acceptable authorization.
U.S. Federal Communications Commission Compliance
For EVMs Annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications could void the user's authority to operate the equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at its own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
Industry Canada Compliance (English)
For EVMs Annotated as IC – INDUSTRY CANADA Compliant:
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs Including Radio Transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs Including Detachable Antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Canada Industry Canada Compliance (French)
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
spacer
Important Notice for Users of EVMs Considered “Radio Frequency Products” in Japan
EVMs entering Japan are NOT certified by TI as conforming to Technical Regulations of Radio Law of Japan.
If user uses EVMs in Japan, user is required by Radio Law of Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use EVMs only after user obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or
Use of EVMs only after user obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect
to EVMs. Also, do not transfer EVMs, unless user gives the same notice above to the transferee. Please note that if user does not
follow the instructions above, user will be subject to penalties of Radio Law of Japan.
http://www.tij.co.jp
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 本開発キットは技術基準適合証明を受けておりません。 本製品の
ご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
http://www.tij.co.jp
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