XTR101APG4

XTR101 SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 Precision, Low Drift 4-20mA TWO-WIRE TRANSMITTER FEATURES D INSTRUMENTATION AMPLIFIER INPUT: − Low Offset Voltage, 30µV max − Low Voltage Drift, 0.75µV/°C max − Low Nonlinearity, 0.01% max D TRUE TWO-WIRE OPERATION: − Power and Signal on One Wire Pair − Current Mode Signal Transmission − High Noise Immunity D D D D DUAL MATCHED CURRENT SOURCES WIDE SUPPLY RANGE: 11.6V to 40V SPECIFICATION RANGE: −40°C to +85°C SMALL DIP-14 PACKAGE, CERAMIC AND PLASTIC APPLICATIONS D INDUSTRIAL PROCESS CONTROL: DESCRIPTION The XTR101 is a microcircuit, 4-20mA, two-wire transmitter containing a high accuracy instrumentation amplifier (IA), a voltage-controlled output current source, and dual-matched precision current reference. This combination is ideally suited for remote signal conditioning of a wide variety of transducers such as thermocouples, RTDs, thermistors, and strain gauge bridges. State-of-theart design and laser-trimming, wide temperature range operation, and small size make it very suitable for industrial process control applications. In addition, the optional external transistor allows even higher precision. The two-wire transmitter allows signal and power to be supplied on a single wire pair by modulating the power-supply current with the input signal source. The transmitter is immune to voltage drops from long runs and noise from motors, relays, actuators, switches, transformers, and industrial equipment. It can be used by OEMs producing transmitter modules or by data acquisition system manufacturers. − Pressure Transmitters − Temperature Transmitters − Millivolt Transmitters D D D D D D D IREF1 IREF2 10 e1 3 11 − 8 RESISTANCE BRIDGE INPUTS THERMOCOUPLE INPUTS +VCC Optional External Transistor 5 RTD INPUTS XTR101 Span CURRENT SHUNT (mV) INPUTS 12(1) B 6 PRECISION DUAL CURRENT SOURCES AUTOMATED MANUFACTURING e2 POWER/PLANT ENERGY SYSTEM MONITORING 4 + 1 9 13(1) E 2 14 7 IOUT Optional Offset Null NOTE: (1) Pins 12 and 13 are used for optional BW control. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright  1986-2004, Texas Instruments Incorporated
          
             
 !     !    www.ti.com "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 ABSOLUTE MAXIMUM RATINGS(1) Power Supply, +VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Input Voltage, e1 or e2 . . . . . . . . . . . . . . . . . . . . ≥ VOUT, ≤ +VCC Storage Temperature Range, Ceramic . . . . . . . . . −55°C to +165°C Plastic . . . . . . . . . . −55°C to +125°C Lead Temperature (soldering, 10s) G, P . . . . . . . . . . . . . . . +300°C (wave soldering, 3s) U . . . . . . . . . . . . . . +260°C Output Short-Circuit Duration . . . . . . . Continuous +VCC to IOUT Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +165°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PRODUCT XTR101 (1) PACKAGELEAD PACKAGE DESIGNATOR(1) Ceramic DIP-14 JD SPECIFIED TEMPERATURE RANGE PACKAGE MARKING XTR101AG Plastic DIP-14 N SO-16 DW XTR101BG −40°C to +85°C XTR101AP XTR101AU For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. PIN CONFIGURATION Top View DIP Zero Adjust Zero Adjust 1 2 −In 3 +In 4 Span Span Out 14 5 6 7 13 12 DIP 11 10 9 8 Top View SO Zero Adjust 1 16 Zero Adjust Zero Adjust 2 15 Bandwidth −In 3 14 B Control +In 4 13 IREF2 Span 5 12 IREF1 Span 6 11 E Out 7 10 +VCC NC 8 9 NC Zero Adjust Bandwidth B Control IREF2 IREF1 SOL−16 Surface−Mount E +VCC NC = No Connection 2 "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS At TA = +25°C, +VCC = 24VDC, and RL = 100Ω with external transistor connected, unless otherwise noted. XTR101AG PARAMETER CONDITIONS OUTPUT AND LOAD CHARACTERISTICS Current Linear Operating Region Derated Performance Current Limit Offset Current Error IOS, IO = 4mA vs Temperature ∆IOS/∆T Full-Scale Output Current Full-Scale = 20mA Error Power-Supply Voltage Load Resistance VCC, Pins 7 and 8, Compliance (1) MIN XTR101BG TYP MAX 28 ±3.9 ±10.5 20 22 38 ±10 ±20 ±20 ±40 4 3.8 MIN ∗ ∗ At VCC = +24V, IO = 20mA 600 At VCC = +40V, IO = 20mA 1400 MAX MIN ∗ ∗ ∗ ∗ ∗ ∗ TYP XTR101AU MAX MIN ∗ ∗ ∗ ∗ ∗ ±2.5 ±8 ±6 ±15 31 ±8.5 ±10.5 ±19 ±20 ±15 ±30 ±30 ±60 ∗ ±40 +11.6 XTR101AP TYP ∗ ∗ ∗ ∗ ∗ ∗ ∗ TYP MAX ∗ ∗ ∗ 31 ±8.5 ∗ ±19 ±30 ±60 ∗ UNIT mA mA mA µA ppm, FS/°C ∗ ∗ ∗ µA VDC Ω Ω SPAN Output Current Equation Span Equation vs Temperature Untrimmed Error(2) Nonlinearity Hysteresis Dead Band INPUT CHARACTERISTICS Impedance: Differential Common-Mode Voltage Range, Full-Scale Offset Voltage vs Temperature Power-Supply Rejection Bias Current vs Temperature Offset Current vs Temperature Common-Mode Rejection (4) Common-Mode Range CURRENT SOURCES Magnitude Accuracy vs Temperature vs VCC vs Time Compliance Voltage Ratio Match Accuracy RS in Ω, e1 and e2 in V I ƪ ∆e = (e2 − e1)(3) VOS ∆VOS/∆T ∆VCC/PSRR = VOS Error IB ∆IB/∆T IOSI ∆IOSI/∆T ƪ ǒ S S + 0.016ampsńvolt ) 40ńR −5 0 0 ∗ ∗ ∗ ∗ 0.4 3 10 3 ∗ ∗ ±30 −2.5 0 110 DC 90 e1 and e2 with Respect to Pin 7 4 ±30 ±0.75 125 60 0.30 10 0.1 ±100 0 0.01 1 ±60 ±1.5 ∗ ∗ ∗ 150 1 ±30 0.3 100 6 ∗ ∗ ±0.06 ±50 ±3 ±8 0 10 TEMPERATURE RANGE Specification Operating Storage −40 −55 −55 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ±30 ±0.75 ∗ ∗ ±20 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ±0.02 5 ±0.075 ±80 ±30 ±50 ∗ ∗ ∗ ±0.0 6 ±0.00 9 ±15 ∗ ∗ ∗ ±10 ±1 20 ∗ +85 +125 +165 ∗ ∗ ∗ Ǔƫǒe2 * e1Ǔ S ∗ ∗ ∗ ∗ Ǔƫ ∗ ∗ ∗ ∗ 122 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ±100 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ±0.1 7 VCC − 3.5 ±0.01 4 (1 − IREF1/IREF2) × 100% ±20 ±0.35 ∗ ∗ ∗ ∗ 1 VCC = 24V, VPIN 8 − VPIN 10, 11 = 19V, R2 = 5kΩ, see Figure 5 With Respect to Pin 7 Tracking ǒ + 4mA ) 0.016ampsńvolt ) 40ńR RS in Ω Excluding TCR of RS εSPAN εNONLINEARITY vs Temperature vs VCC vs Time Output Impedance ∗ Same as XTR101AG. O ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ±100 ∗ ±0.37 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 10 ∗ ∗ ∗ ±0.088 ±0.031 ∗ ∗ 15 ∗ ∗ GΩ pF GΩ pF V µV µV/°C dB nA nA/°C nA nA/°C V mA ±0.2 ∗ A/V ppm/°C % % % % dB ∗ ±0.37 ±0.031 ∗ ∗ ∗ ∗ ∗ ∗ ∗ 122 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ±0.2 ±0.04 ∗ ∗ ∗ ∗ ∗ % ppm/°C ppm/V ppm/month ∗ V ±0.088 % ∗ ppm/°C ppm/V ppm/month 15 MΩ ∗ ∗ ∗ ∗ −40 −55 +85 +125 −40 −55 +85 +125 °C °C °C (1) See the Typical Characteristics. (2) Span error shown is untrimmed and may be adjusted to zero. (3) e1 and e2 are signals on the −In and +In terminals with respect to the output, pin 7. While the maximum permissible ∆e is 1V, it is primarily intended for much lower signal levels, for instance, 10mV or 50mV full-scale for the XTR101A and XTR101B grades, respectively. 2mV FS is also possible with the B grade, but accuracy will degrade due to possible errors in the low value span resistance and very high amplification of offset, drift, and noise. (4) Offset voltage is trimmed with the application of a 5V common-mode voltage. Thus, the associated common-mode error is removed. See the Application Information section. 3 "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS At TA = +25°C and VCC = 24VDC, unless otherwise noted. STEP RESPONSE SPAN vs FREQUENCY 25 80 ) Ω RS = ∞ 20 60 Output Current (mA) Transconductance (20 Log m CC = 0 RS = 25Ω RS = 100Ω RS = 400Ω 40 RS = 2kΩ RS = ∞ 20 RS = 25Ω 15 10 5 0 0 100 1k 10k 100k 0 1M 200 400 FULL−SCALE INPUT VOLTAGE vs RS RS (kΩ ) 0 2 4 600 800 1000 Time (µs) Frequency (Hz) 6 COMMON−MODE REJECTION vs FREQUENCY 8 0.08 120 0.8 0 to 800mV and 0 to 8kΩscale 0.04 0.4 0.02 0.2 80 CMR (dB) 0.6 0.06 ∆ eIN Full−Scale (V) ∆ eIN Full−Scale (V) 100 40 20 0 to 80mV (low−level signals) and 0 to 400Ωscale 0 0 0 100 200 60 300 0 0.1 400 1 RS (Ω) 1k 10k 100k BANDWIDTH vs PHASE COMPENSATION 140 100k 120 10k 100 Bandwidth (Hz) Power−Supply Rejection (dB) 100 Frequency (Hz) POWER−SUPPLY REJECTION vs FREQUENCY 80 60 RS = ∞ 1k RS = 400Ω RS = 100Ω 100 RS = 25Ω 10 40 1 20 0.1 0 0.1 10 100 1k 10k Frequency (Hz) 4 10 100k 1M 10M 1 10 100 1k 10k Bandwidth Control, CC (pF) 100k 1M "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY INPUT CURRENT NOISE DENSITY vs FREQUENCY 6 Input Noise Current (pA/ Hz) 50 40 30 20 10 5 4 3 2 1 0 0 1 10 100 1k 10k 100k 1 10 100 Frequency (Hz) 1k 10k 100k Frequency (Hz) OUTPUT CURRENT NOISE DENSITY vs FREQUENCY 6 Output Noise Current (nA/ Hz) Input Noise Voltage (nV/ Hz) 60 5 4 3 2 1 0 1 10 100 1k 10k 100k Frequency (Hz) 5 "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 THEORY OF OPERATION A simplified schematic of the XTR101 is shown in Figure 1. Basically, the amplifiers A1 and A2 act as a single power-supply instrumentation amplifier controlling a current source, A3 and Q1. Operation is determined by an internal feedback loop. e1 applied to pin 3 will also appear at pin 5, and similarly, e2 will appear at pin 6. Therefore, the current in RS (the span setting resistor) will be IS = (e2 − e1)/RS = eIN/RS. This current combines with the current I3 to form I1. The circuit is configured such that I2 is 19 times I1. From this point, the derivation of the transfer function is straightforward but lengthy. The result is shown in Figure 1. eIN − Examination of the transfer function shows that IO has a lower range-limit of 4mA when eIN = e2 − e1 = 0V. This 4mA is composed of 2mA quiescent current exiting pin 7 plus 2mA from the current sources. The upper range limit of IO is set to 20mA by the proper selection of RS based on the upper range limit of eIN. Specifically, RS is chosen for a 16mA output current span for the given full-scale input voltage span. ǒ For example, 0.016 Ǔ amps 40 ǒ ) e IN full−scaleǓ + 16mA. volt RS Note that since IO is unipolar, e2 must be kept larger than e1 (that is, e2 ≥ e1 or eIN ≥ 0). Also note that in order not to exceed the output upper range limit of 20mA, eIN must be kept less than 1V when RS = ∞ and proportionately less as RS is reduced. + RS (e1) (e2) IS 5 6 I3 I4 R3 1.25kΩ R4 1.25kΩ +VCC +VCC IB1 (e1) A2 A1 +VCC 8 D1 −In3 eIN IB2 VPS +In4 (e2) 100µA 7 IO + Q1 +VCC eL +VCC I1 R1 1kΩ 2mA A3 R2 52.6Ω I2 IO Voltage−Controlled Current Source 10 IREF1 11 IREF2 2.5kΩ I O + 4mA ) ǒ 0.016 Ǔ amps 40 ) e e + e2 * e1 volt RS IN, IN Figure 1. Simplified Schematic of the XTR101 6 RL − "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 OPTIONAL EXTERNAL TRANSISTOR INSTALLATION AND OPERATING INSTRUCTIONS The optional external transistor, when used, is connected in parallel with the XTR101 internal transistor. The purpose is to increase accuracy by reducing heat change inside the XTR101 package as the output current spans from 4-20mA. Under normal operating conditions, the internal transistor is never completely turned off, as shown in Figure 2. This maintains frequency stability with varying external transistor characteristics and wiring capacitance. The actual current sharing between internal and external transistors is dependent on two factors: BASIC CONNECTION See Figure 1 for the basic connection of the XTR101. A difference voltage applied between input pins 3 and 4 will cause a current of 4-20mA to circulate in the two-wire output loop (through RL, VPS, and D1). For applications requiring moderate accuracy, the XTR101 operates very cost-effectively with just its internal drive transistor. For more demanding applications (high accuracy in high gain), an external NPN transistor can be added in parallel with the internal one. This keeps the heat out of the XTR101 package and minimizes thermal feedback to the input stage. Also, in such applications where the eIN full-scale is small (< 50mV) and RSPAN is small (< 150Ω), caution should be taken to consider errors from the external span circuit plus high amplification of offset drift and noise. 1. relative geometry of emitter areas, and 2. relative package dissipation (case size and thermal conductivity). For best results, the external device should have a larger base-emitter area and smaller package. It will, upon turn-on, take about [0.95(IO − 3.3mA)]mA. However, it will heat faster and take a greater share after a few seconds. 4mA 20mA 16mA +VCC 8 750Ω (2) 12V, 200mW 3.5mA 0.5mA XTR101 B 12 QEXT 23.6V, 377mW 2N2222 QINT 18mW (1) Other Suitable Types Package Type 3.47V, 60mW 210Ω 9 E 1.5mA Quiescent TO−225 TO−220 TO−220 7 I OUT 11 Short−Circuit Worst−Case 10 1mA VPS 40V 0.95V, 17mW 52.6Ω 1mA 2N4922 TIP29B TIP31B RL 250Ω 18mA 20mA 2mA NOTES: (1) An external transistor is used in the manufacturing test circuit for testing electrical specifications. (2) This resistor is required for the 2N2222 with VPS > 24V to limit power dissipation. Figure 2. Power Calculation of the XTR101 with an External Transistor 7 "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 Although any NPN of suitable power rating will operate with the XTR101, two readily available transistors are recommended: 1. 2N2222 in the TO-18 package. For power-supply voltages above 24V, a 750Ω, 1/2W resistor should be connected in series with the collector. This will limit the power dissipation to 377mW under the worst-case conditions; see Figure 2. Thus, the 2N2222 will safely operate below its 400mW rating at the upper temperature of +85°C. Heat sinking the 2N2222 will result in greatly reduced accuracy improvement and is not recommended. 2. TIP29B in the TO-220 package. This transistor will operate over the specified temperature and output voltage range without a series collector resistor. Heat sinking the TIP29B will result in slightly less accuracy improvement. It can be done, however, when mechanical constraints require it. MAJOR POINTS TO CONSIDER WHEN USING THE XTR101 1. The leads to RS should be kept as short as possible to reduce noise pick-up and parasitic resistance. 2. +VCC should be bypassed with a 0.01µF capacitor as close to the unit as possible (pin 8 to pin 7). 3. Always keep the input voltages within their range of linear operation, +4V to +6V (e1 and e2 measured with respect to pin 7). 4. The maximum input signal level (eINFS) is 1V with RS = ∞ and proportionally less as RS decreases. 5. Always return the current references (pins 10 and 11) to the output (pin 7) through an appropriate resistor. If the references are not used for biasing or excitation, connect them together to pin 7. Each reference must have between 0V and +(VCC − 4V) with respect to pin 7. 6. Always choose RL (including line resistance) so that the voltage between pins 7 and 8 (+VCC) remains within the 11.6V to 40V range as the output changes between the 4-20mA range (as shown in Figure 4). 7. It is recommended that a reverse polarity protection diode (D1 in Figure 1) be used. This will prevent damage to the XTR101 caused by a momentary (such as a transient) or long-term application of the wrong polarity of voltage between pins 7 and 8. 8. Consider PC board layout which minimizes parasitic capacitance, especially in high gain. ACCURACY WITH AND WITHOUT AN EXTERNAL TRANSISTOR The XTR101 has been tested in a circuit using an external transistor. The relative difference in accuracy with and without an external transistor is shown in Figure 3. Notice that a dramatic improvement in offset voltage change with supply voltage is evident for any value of load resistor. 60 50 25 ∆VOS (µV) Without External Transistor 40 20 15 RL = 100Ω 30 RL = 600Ω 10 5 0 10 R L = 1kΩ With External Transistor 10 RL = 1kΩ RL = 600Ω RL = 100Ω 20 0 20 30 40 VCC (V) 1500 Load Resistance, RL (Ω) Span = ∆IO = 16mA Self−Heating ∆ Temperature (_C) 30 1250 RL max = 1000 VPS − 11.6V 20mA 750 Operating Region 500 250 0 0 10 20 30 40 50 Power−Supply Voltage, VPS (V) Figure 3. Thermal Feedback Due to Change in Output Current 8 Figure 4. Power-Supply Operating Range 60 "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 SELECTING THE RS 11 10 e1 3 − RSPAN is chosen so that a given full-scale input span (eINFS) will result in the desired full-scale output span of ∆IOFS: ƪǒ Ǔ ǒ Ǔƫ De amps 0.016 ) 40 volt RS 5 − IN 2mA + DI O + 16mA. eIN RS Adj. + 6 Solving for RS: 4−20mA XTR101 e2 + 4 RS + 40 amps DI OńDe IN * 0.016 volt + (1) +4V ≤ e2 ≤ +6V The offset adjustment is used to remove the offset voltage of the input amplifier. When the input differential voltage (eIN) equals zero, adjust for 4mA output. Figure 6 shows a similar connection for a resistive transducer. The transducer could be excited either by one (as shown) or both current sources. Also, the offset adjustment has higher resolution compared to Figure 5. IO Offset Adjust I O + 4mA ) ǒ 0.016 Ǔ amps 40 ) e IN volt R S e IN + e 2 2mA +5V Figure 5. Basic Connection for Floating Voltage Source 1mA D1 11 e1 3 10 − 1mA 8 5 BIASING THE INPUTS +4V ≤ e1 ≤ +6V + 24V + eL − RL − 7 R2 2.5kΩ RS + Because the XTR operates from a single supply, both e1 and e2 must be biased approximately 5V above the voltage at pin 7 to assure linear response. This is easily done by using one or both current sources and an external resistor, R2. Figure 5 shows the simplest case—a floating voltage source eȀ2. The 2mA from the current sources flows through the 2.5kΩ value of R2 and both e1 and e2 are raised by the required 5V with respect to pin 7. For linear operation the constraint is: 14 0.01µF For example, if ∆eINFS = 100mV for ∆IOFS = 16mA, See the Typical Characteristics for a plot of RS vs ∆eINFS. Note that in order not to exceed the 20mA upper range limit, eIN must be less than 1V when RS = ∞ and proportionately smaller as RS decreases. 2 0.01µF 1MΩ 1 e’2 40 40 + ǒ16mAń100mVǓ * 0.016 0.16 * 0.016 + 40 + 278W 0.144 D1 8 + eIN − RS XTR101 + 24V + eL − RL − 4 2 14 1 100kΩ + RT − Alternate circuitry shown in Figure 8. 7 + e2 e2 0.01µF 6 Offset Adjust 1MΩ R2 2.5kΩ 2mA +5V 0.01µF I O + 4mA ) ǒ 0.016 e IN + eȀ 2 + 1mA Ǔ amps 40 ) e IN volt R S RT Figure 6. Basic Connection for Resistive Source CMV AND CMR The XTR101 is designed to operate with a nominal 5V common-mode voltage at the input and will function properly with either input operating over the range of 4V to 6V with respect to pin 7. The error caused by the 5V CMV is already included in the accuracy specifications. If the inputs are biased at some other CMV, then an input offset error term is (CMV − 5)/CMRR, where CMR is in dB, and CMRR is in V/V. 9 "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 SIGNAL SUPPRESSION AND ELEVATION In some applications, it is desired to have suppressed zero range (input signal elevation) or elevated zero range (input signal suppression). This is easily accomplished with the XTR101 by using the current sources to create the suppression/elevation voltage. The basic concept is shown in Figure 7 and Figure 8(a). In this example, the sensor voltage is derived from RT (a thermistor, RTD, or other variable resistance element) and excited by one of the 1mA current sources. The other current source is used to create the elevated zero range voltage. Figure 8(b), (c), and (d) show some of the possible circuit variations. These circuits have the desirable feature of noninteractive span and suppression/elevation adjustments. Note: It is not recommended to use the optional offset voltage null (pins 1, 2, and 14) for elevation/suppression. This trim capability is used only to null the amplifier’s input offset voltage. In many applications the already low offset voltage (typically 20µV) will not need to be nulled at all. Adjusting the offset voltage to non-zero values will disturb the voltage drift by ±0.3µV/°C per 100µV or induced offset. 1mA eIN − IO (mA) + e’2 − RT e’2 RT + V4 R4 − 2mA 2mA eIN = (e’2 − V4) V4 = 1mA × R4 e’2 = 1mA × RT eIN = (e’2 + V4) V4 = 1mA × R4 e’2 = 1mA × RT (a) Elevated Zero Range (b) Suppressed Zero Range 2mA − eIN + − eIN + 2mA − e’2 + + R4 + + e’2 − V4 R4 − 2mA 2mA eIN = (e’2 − V4) V4 = 2mA × R4 eIN = (e’2 + V4) V4 = 2mA × R4 (c) Elevated Zero Range (d) Suppressed Zero Range Figure 8. Elevation and Suppression Circuits Elevated Zero Range Suppressed Zero Range 0 −0+ eIN (V) Figure 7. Elevation and Suppression Graph 10 − eIN + 1mA + + R4 Span Adjust 10 5 1mA − − 15 − + V4 V4 20 1mA APPLICATION INFORMATION The small size, low offset voltage and drift, excellent linearity, and internal precision current sources make the XTR101 ideal for a variety of two-wire transmitter applications. It can be used by OEMs producing different types of transducer transmitter modules and by data acquisition systems manufacturers who gather transducer data. Current-mode transmission greatly reduces noise interference. The two-wire nature of the device allows economical signal conditioning at the transducer. Thus the XTR101 is, in general, very suitable for individualized and special-purpose applications. "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 EXAMPLE 1 e1 An RTD transducer is shown in Figure 9. 3 Given a process with temperature limits of +25°C and +150°C, configure the XTR101 to measure the temperature with a platinum RTD which produces 100Ω at 0°C and 200Ω at +266°C (obtained from standard RTD tables). Transmit 4mA for +25°C and 20mA for +150°C. COMPUTING RS: The sensitivity of the RTD is ∆R/∆T = 100Ω/266°C. When excited with a 1mA current source for a 25°C to 150°C range (a 125°C span), the span of eIN is 1mA × (100Ω/266°C) × 125°C = 47mV = ∆eIN. 40 From Equation 1, R S + amps DI OńDe IN * 0.016 volt 40 RS + + 40 + 123.3W 0.3244 16mAń47mV * 0.016AńV Span adjustment (calibration) is accomplished by trimming RS. At ) 25 oC, eȀ 2 + 1mA(RT ) DRT) ƪ ƫ + 1mA 100W ) 100W 25 oC 266 oC + 1mA(109.4W) + 109.4mV In order to make the lower range limit of 25°C correspond to the output lower range limit of 4mA, the input circuitry shown in Figure 9 is used. eIN, the XTR101 differential input, is made 0 at 25°C or: 25 oC * V4 thus, V 4 + eȀ 2 R4 + 10 8 5 − eIN + RS + V4 − XTR101 4 R4 e2 + e’2 − 0.01µF 6 + 24V + eL − RL − 7 + RT R2 0.01µF Figure 9. Circuit for Example 1 EXAMPLE 2 A thermocouple transducer is shown in Figure 10. COMPUTING R4: eȀ 2 D1 11 − 25 oC + 109.4mV Given a process with temperature (T1) limits of 0°C and +1000°C, configure the XTR101 to measure the temperature with a type J thermocouple that produces a 58mV change for 1000°C change. Use a semiconductor diode for cold junction compensation to make the measurement relative to 0°C. This is accomplished by supplying a compensating voltage (VR6) equal to that normally produced by the thermocouple with its cold junction (T2) at ambient. At a typical ambient of +25°C, this is 1.28mV (obtained from standard thermocouple tables with reference junction of 0°C). Transmit 4mA for T1 = 0°C and 20mA for T1 = +1000°C. Note: eIN = e2 − e1 indicates that T1 is relative to T2. V4 + 109.4mV + 109.4W 1mA 1mA 1mA 1mA R5 2kΩ COMPUTING R2 AND CHECKING CMV: At ) 25 C, eȀ 2 + 109.4mV At ) 150 oC, eȀ 2 + 1mA(RT ) DRT) o ƪ + 1mA 100W ) 100W 266 oC + 156.4mV R 2 + 5V + 2.5kW 2mA e 2 min + 5V ) 0.1094V e 2 max + 5V ) 0.1564V e 1 + 5V ) 0.1094V D ƫ + e1 − 150 oC Since both eȀ2 and V4 are small relative to the desired 5V common-mode voltage, they may be ignored in computing R2 as long as the CMV is met. The 4V to 6V CMV requirement is met. 11 − 10 8 R6 51Ω eIN XTR101 Thermocouple TTC 4 VTC Temperature T1 ǁ 3 + V4 − R4 + e2 − 7 + 0.01µF 2.5kΩ Temperature T2 = TD Figure 10. Thermocouple Input Circuit with Two Temperature Regions and Diode (D) Cold Junction Compensation 11 "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 ESTABLISHING RS: R5 is chosen as 2kΩ to be much larger than the resistance of the diode. Solving for R6 yields 51Ω. The input full-scale span is 58mV (∆eINFS = 58mV). RS is found from Equation 1. 40 amps DI OńDe IN * 0.016 volt 40 + + 40 + 153.9W 0.2599 16mAń58mV * 0.016AńV RS + SELECTING R4: R4 is chosen to make the output 4mA at TTC = 0°C (VTC = −1.28mV) and TD = +25°C (VD = 0.6V); see Figure 10. 1mA + VD − R5 + V5 − R6 + V6 − D VTC will be −1.28mV when TTC = 0°C and the reference junction is at +25°C. e1 must be computed for the condition of TD = +25°C to make eIN = 0V. V D 25oC + 600mV ǒ Figure 11. Cold Junction Compensation Circuit Ǔ e 1 25oC + 600mV 51 + 14.9mV 2051 e IN + e2 * e1 + V TC ) V4 * e1 THERMOCOUPLE BURN-OUT INDICATION With eIN = 0 and VTC = −1.28mV, V 4 + e1 ) eIN * VTC + 14.9mV ) 0V * (* 1.28mV) 1mA(R 4) + 16.18mV R 4 + 16.18W COLD JUNCTION COMPENSATION: A temperature reference circuit is shown in Figure 11. The diode voltage has the form: V D + KT q ln I DIODE I SAT OPTIONAL INPUT OFFSET VOLTAGE TRIM Typically at T2 = +25°C, VD = 0.6V and ∆VD/∆T = −2mV/°C. R5 and R6 form a voltage divider for the diode voltage VD. The divider values are selected so that the gradient ∆VD/∆T equals the gradient of the thermocouple at the reference temperature. At +25°C this is approximately 52µV/°C (obtained from a standard thermocouple table); therefore, ǒ DT C DVD R6 + DT DT R 5 ) R 6 ǒ Ǔ 52mV 2000mV R6 + °C °C R5 ) R6 12 In process control applications it is desirable to detect when a thermocouple has burned out. This is typically done by forcing the two-wire transmitter current to either limit when the thermocouple impedance goes very high. The circuits of Figure 16 and Figure 17 inherently have downscale indication. When the impedance of the thermocouple gets very large (open) the bias current flowing into the + input (large impedance) will cause IO to go to its lower range limit value (about 3.8mA). If upscale indication is desired, the circuit of Figure 18 should be used. When TC opens, the output will go to its upper range limit value (about 25mA or higher). Ǔ (2) The XTR101 has provisions for nulling the input offset voltage associated with the input amplifiers. In many applications the already low offset voltages (30µV max for the B grade and 60µV max for the A grade) will not need to be nulled at all. The null adjustment can be done with a potentiometer at pins 1, 2, and 14; see Figure 5 and Figure 6. Either of these two circuits may be used. NOTE: It is not recommended to use this input offset voltage nulling capability for elevation or suppression. See the Signal Suppression and Elevation section for the proper techniques. "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 OPTIONAL BANDWIDTH CONTROL f CO + 0.0047µF 1mA Low-pass filtering is recommended where possible and can be done by either one of two techniques; see Figure 12. C2 connected to pins 3 and 4 will reduce the bandwidth with a cutoff frequency given by: R3(1) 3 11 − 1mA 15.9 (R1 ) R2 ) R3 ) R 4)(C2 ) 3pF) C2 XTR101 R1 This method has the disadvantage of having fCO vary with R1, R2, R3, R4, and it may require large values of R3 and R4. The other method, using C1, will use smaller values of capacitance and is not a function of the input resistors. It is, however, more subject to nonlinear distortion caused by slew rate limiting. This is normally not a problem with the slow signals associated with most process control transducers. The relationship between C1 and fCO is shown in the Typical Characteristics. R4(1) 4 12 R2 13 + C1 NOTE: (1) R3 and R 4 should be equal if used. Internally eNOISE RTI = e2INPUT STAGE + e2OUTPUT STAGE 2 Gain Figure 12. Optional Filtering APPLICATION CIRCUITS Voltage Reference + MC1403A VR = 2.5V − 100pF XTR101 V+ IO (4−20 mA) OPA27 V− R1 125Ω R2 500Ω IOȀ (0−20mA) ǒ R1 NOTE: I OȀ + 1 ) R 2 Ǔ V I O * R + 1.25 I O * 5mA R2 Other conversions are readily achievable by changing the reference and ratio of R1 to R2. Figure 13. 0-20mA Output Converter 13 "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 0.9852mA 2mA 1.0147mA 1.8kΩ R R LM129 6.9V Voltage Ref − 300Ω R RS XTR101 R + 4.7kΩ 0.01µF Figure 14. Bridge Input, Voltage Excitation 1mA 2mA R R − 300Ω − Type J − + R R 51Ω RS RS 20Ω XTR101 This circuit has downscale burn−out indication. 1mA 2kΩ XTR101 J 2.2kΩ 2.5kΩ Figure 15. Bridge Input, Current Excitiation 1mA 15Ω RTD 100Ω This circuit has upscale burn−out indication. 1mA + − − + 20Ω RS 20Ω XTR101 15Ω Zero Adjust + 2.5kΩ Figure 16. Thermocouple Input with RTD Cold Junction Compensation 14 1mA − Type J − Figure 17. Thermocouple Input with Diode Cold Junction Compensation This circuit has downscale burn−out indication. 1mA + Zero Adjust + RTD 100Ω RS XTR101 Zero Adjust + 2.5kΩ Figure 18. Thermocouple Input with RTD Cold Junction Compensation "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 11 I1 I2 10 +VCC 8 +VCC − 3 OPA21 15V 0.01µF R1 XTR101 7 + VREF Out R2 4 2.5kΩ VREF = ImA R2 Figure 19. Dual Precision Current Sources Operated from One Supply Isolation Barrier 8 −V2 ∆eIN 1kΩ E 7 1µF V− + 30V − XTR101 1µF V+ 722 C1 +V1 −V1 4−20 mA +15V P+ +V2 C2 − +15V 1MΩ + 10 + 12 15 7 250Ω −15V 1MΩ 2 4 3 ISO100 9 VOUT(1) +1V to +5V 8 IREF2 17 − 16 18 IREF1 NOTE: (1) Can be shifted and amplified using ISO100 current sources. Figure 20. Isolated Two-Wire Current Loop 15 "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 DETAILED ERROR ANALYSIS EXAMPLE 3 The ideal output current is: See the circuit in Figure 9 with the XTR101BG specifications and the following conditions: RT = 109.4Ω at 25°C, RT = 156.4Ω at 150°C, IO = 4mA at 25°C, IO = 20mA at 150°C, RS = 123.3Ω, R4 = 109Ω, RL = 250Ω, RLINE = 100Ω, VDI = 0.6V, and VPS = 24V ± 0.5%. Determine the % error at the upper and lower range values. I O IDEAL + 4mA ) K e IN ǒ (3) where K is the span (gain) term, 0.016 ǒ ǓǓ amps ) 40 volt RS In the XTR101 there are three major components of error: A. AT THE LOWER RANGE VALUE (T = +255C) 1. σO = errors associated with the output stage. s O + I OS RTO +" 6mA 2. σS = errors associated with span adjustment. 3. σI = errors associated with the input stage. DVCC s I + V OSI ) ǒI BI DR ) I OSI R4Ǔ ) ) PSRR The transfer function including these errors is: I O ACTUAL + ǒ4mA ) s OǓ ) Kǒ1 ) sSǓ(e IN ) s I) (4) When this expression is expanded, second-order terms (σS, σI) dropped, and terms collected, the result is: IO ACTUAL + ǒ4mA ) s OǓ ) K e IN ) Ks I ) Ks S e IN (6) This is a general error expression. The composition of each component of error depends on the circuitry inside the XTR101 and the particular circuit in which it is applied. The circuit of Figure 9 will be used to illustrate the principles. s O + I OS RTO (7) s S + eNONLINEARITY ) eSPAN sI + VOSI ) ǒIB1 ) R4 * IB2 R TǓ ) DVCC ) PSRR (8) ǒe1)e2Ǔ 2 * 5V CMRR (9) The term in parentheses may be written in terms of offset current and resistor mismatches as IB1 ∆R + IOSȀ R4. VOSI(1) = input offset voltage. IB1(1), IB2(1) = input bias current. IOSI(1) = input offset current. IOS RTO (1) = output offset current error. ∆R = RT − R4 = mismatch in resistor. ∆VCC = change supply voltage between pins 7 and 8 away from 24V nominal. PSRR (1) = power-supply rejection ratio. CMRR (1) = common-mode rejection ratio. εNONLIN (1) = span nonlinearity. εSPAN(1) = span equation error. Untrimmed error = 5% max. May be trimmed to zero. (1) 16 e 1 + ǒ2mA 2.5kWǓ ) ǒ1mA + 5.109V e 2 + ǒ2mA 2.5kWǓ ) ǒ1mA + 5.1094V ǒe 1 ) e 2Ǔ 2 I O ERROR + sO ) KsI ) KsS e IN These items can be found in the Electrical Characteristics. e )e ƫ 1 2 2 ȳ ȧ ȴ * 5V CMRR DR + RT 25oC * R4 + 109.4 * 109 [ 0 DVCC + (24 0.005) ) 4mA(250W ) 100W) ) 0.6V + 120mV ) 1400mV ) 600mV + 2120mV (5) The error in the output current is IO ACTUAL − IO IDEAL and can be found by subtracting Equation 3 from Equation 5. ȱƪ ȧ Ȳ 109WǓ 109.4WǓ * 5V + 0.1092V PSRR + 3.16 CMRR + 31.6 105 for 110dB 10 3 for 90dB s 1 + 30mV ) (150nA 0 ) 20nA 109W) ) 2120mV ) 0.1092V (10) 3.16 10 5 3.16 10 3 + 30mV ) 2.18mV ) 6.7mV ) 3.46mV + 42.34mV s S + eNONLIN ) eSPAN + 0.0001 ) 0 ǒassumes trim of R SǓ I O ERROR + sO ) K sI ) K sS e IN K + 0.016 ) 40 + 0.016 ) 40 123.3W RS amps + 0.340 volts e IN + e2 * V4 + I REF1 R T 25oC * I REF2 R4 Since RT 25°C = R4: e IN + ǒI REF1 * IREF2Ǔ R 4 + 0.4mA + 43.6mV 109W Since the maximum mismatch of the current references is 0.04% of 1mA = 0.4µA: I O error + 6mA ) ǒ0.34AńV 42.34mVǓ ) ǒ0.34AńV 0.0001 43.6mVǓ + 6mA ) 14.40mA ) 0.0015mA + 20.40mA 20.40mA 100% % error + 16mA 0.13% of span at lower range value. "#$# www.ti.com SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004 B. AT THE UPPER RANGE VALUE (T = +150°C) DR + R T 150oC * R 4 + 156.4 * 109.4 + 47W DV CC + ǒ24 0.005Ǔ ) 20mAǒ250W ) 100WǓ ) 0.6V + 7720mV e 1 + 5.109V e 2 + ǒ2mA 2.5kWǓ ) ǒ1mA + 5.156V ǒe 1 * e 2Ǔ 2 156.4WǓ * 5V + 0.1325V s O + 6mA s 1 + 30mV ) ǒ150nA 47W ) 20nA 190WǓ ) 7720mV ) 0.1325V 3.16 105 3.16 10 3 + 30mV ) 9.23mV ) 24mV ) 4.19mV + 67.42mV s S + 0.0001 e IN + eȀ 2 * V 4 + IREF1 R T 150oC * IREF2 R 4 + ǒ1mA + 47mV 156.4WǓ * ǒ1mA 109WǓ I O error + sO ) K s I ) K s S eIN + 6mA ) ǒ0.34AńV 67.42mVǓ ) ǒ0.34AńV 0.0001 47000mVǓ CONCLUSIONS Lower Range: From Equation 10, it is observed that the predominant error term is the input offset voltage (30µV for the B grade). This is of little consequence in many applications. VOS RTI can, however, be nulled using the plots shown in Figure 5 and Figure 6. The result is an error of 0.06% of span instead of 0.13% of span. Upper Range: From Equation 11, the predominant errors are IOS RTO (6µA), VOS RTI (30µV), and IB (150nA), max, B grade. Both IOS and VOS can be trimmed to zero; however, the result is an error of 0.09% of span instead of 0.19% of span. RECOMMENDED HANDLING PROCEDURES FOR INTEGRATED CIRCUITS All semiconductor devices are vulnerable, in varying degrees, to damage from the discharge of electrostatic energy. Such damage can cause performance degradation or failure, either immediate or latent. As a general practice, we recommend the following handling procedures to reduce the risk of electrostatic damage: 1. Remove the static-generating materials (such as untreated plastic) from all areas that handle microcircuits. 2. Ground all operators, equipment, and work stations. (11) 3. + 6mA ) 22.92mA ) 1.60mA + 30.52mA 30.52mA % error + 100% 16mA Transport and ship microcircuits, or products incorporating microcircuits, in static-free, shielded containers. 4. Connect together all leads of each device by means of a conductive material when the device is not connected into a circuit. 0.19% of span at upper range value. 5. Control relative humidity to as high a value as practical (50% recommended). 17 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) XTR101AG NRND CDIP SB JD 14 1 RoHS & Green Call TI N / A for Pkg Type XTR101AP ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 XTR101AG XTR101AP XTR101AU ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 XTR101AU XTR101AU/1K ACTIVE SOIC DW 16 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 XTR101AU XTR101BG NRND CDIP SB JD 14 1 RoHS & Green Call TI N / A for Pkg Type -40 to 85 XTR101BG (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of