SPT7851

www.cadeka.com SPT7851 10-Bit, 20 MSPS, 79mW Analog-to-DIgital Converter Features • 10-Bit, 20 MSPS Analog-to-Digital converter • Monolithic CMOS • Internal track-and-hold • Low input capacitance: 1.4 pF • Low power dissipation: 79mW • 2.8 to 3.6V power supply range • TTL-compatible outputs • -40°C to +85°C operation Description The SPT7851 10-bit, 20 MSPS analog-to-digital converter has a pipelined converter architecture built in a CMOS process. It delivers high performance with a typical power dissipation of only 79mW. With low distortion and high dynamic range, this device offers the performance needed for imaging, multimedia, telecommunications and instrumentation applications. The SPT7851 is available in a 44-lead Thin Quad Flat Pack (TQFP) package in the industrial temperature range (-40°C to +85°C). Applications • CCD imaging cameras and sensors • Medical imaging • RF communications • Document and film scanners • Electro-optics • Transient signal analysis • Handheld equipment Functional Block Diagram ADC DAC + – G=2 D Pipeline Stage VIN+ VIN– VREF+ VREF– CLK Clock Driver Stage 1 Stage 2 Stage 9 Stage 10 Digital Delays, Error Correction and Output 10 Digital Output (D0 – D9) REV. 1B October 2003 DATA SHEET SPT7851 Electrical Specifications (TA = TMIN–TMAX, VDD1 = VDD2 = VDD3 = 3.3V, VREF– = 1.0V, VREF+ = 2.0V, Common Mode Voltage = 1.65V, ƒCLK = 20 MSPS, Bias1 = 90µA, Bias2 = 9.5µA, Differential Input, Duty Cycle = 50%; unless otherwise noted) Parameter DC Accuracy Resolution Differential Linearity Integral Linearity No Missing Codes Analog Input Input Voltage Range (differential) Common Mode Input Voltage Input Capacitance Input Bandwidth (large signal) Offset (mid-scale) Gain Error Reference Voltages Reference Input Voltage Range Negative Reference Voltage (VREF–) Positive Reference Voltage (VREF+) Common Mode Output Voltage (VCM) VREF+ Current VREF– Current Switching Performance Maximum Conversion Rate Pipeline Delay (see Figure 1) Aperture Delay Time (TAP) Aperture Jitter Time Dynamic Performance Signal-To-Noise Ratio Effective Number of Bits Total Harmonic Distortion Signal-To-Noise and Distortion Spurious Free Dynamic Range Differential Phase Differential Gain ƒIN = 5MHz ƒIN = 10MHz ƒIN = 5MHz ƒIN = 10MHz ƒIN = 5MHz ƒIN = 10MHz ƒIN = 5MHz ƒIN = 10MHz ƒIN = 5MHz ƒIN = 10MHz VI V VI V VI V VI V VI V V V 62 56 9.0 57 58 58 9.3 9.0 -68 -60 58 56 70 61 0.2 0.5 -61 dB dB Bits Bits dB dB dB dB dB dB deg % VI IV V V 20 7.5 5 10 MHz CLK ns ps-rms IO = -1µA VREF+ – VREF– IV IV IV VI V V 0.6 0.9 1.9 1.3 1.0 1.0 2.0 1.65 35 -25 1.7 1.3 2.9 1.8 V V V V µA µA VIN+ = VIN- = VCM IV IV V V V V ±0.6 1.2 ±1.0 1.65 1.4 120 ±1.0 0.3 ±1.7 1.9 V V pF MHz %FSR %FSR V V VI 10 ±0.6 ±0.75 Guaranteed Bits LSB LSB Conditions Test Level Min Typ Max Units 2 REV. 1B October 2003 SPT7851 DATA SHEET Electrical Specifications (TA = TMIN–TMAX, VDD1 = VDD2 = VDD3 = 3.3V, VREF– = 1.0V, VREF+ = 2.0V, Common Mode Voltage = 1.65V, ƒCLK = 20 MSPS, Bias1 = 90µA, Bias2 = 9.5µA, Differential Input, Duty Cycle = 50%; unless otherwise noted) Parameter Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage CLK to Output Delay Time (tD) Power Supply Requirements Supply Voltage (VDD1, VDD2, VDD3) Supply Current (IDD) Power Dissipation Power Supply Rejection Ratio TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. LEVEL IV V VI TEST PROCEDURE Parameter is guaranteed (but not tested) by design or characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25°C. Parameter is guaranteed over specified temperature range. IV VI VI V 2.8 3.3 24 79 67 3.6 30 100 V mA mW dB IO = -2mA IO = +2mA VI VI IV 4 85% VDD 90% VDD 0.1 8 0.4 12 V V ns VIN = GND VIN = VDD VI VI VI VI V 1.8 80% VDD 20% VDD ±1 ±1 µA µA pF Conditions Test Level Min Typ Max Units Absolute Maximum Ratings (beyond which the device may be damaged) Parameter Supply Voltages VDD1, VDD2,VDD3 Input Voltages Analog and Digital Input VREF+, VREF–, CLK Operating Temperature Range Storage Temperature Range -0.5 -0.5 -40 -65 VDD +0.5 VDD +0.5 +85 +125 V V °C °C -0.5 +6 V Min Max Units Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. REV. 1B October 2003 3 DATA SHEET SPT7851 Typical Performance Characteristics (TA = TMIN–TMAX, VDD1 = VDD2 = VDD3 = 3.3V, VREF– = 1.0V, VREF+ = 2.0V, Common Mode Voltage = 1.65, ƒCLK = 20 MSPS, Bias1 = 90µA, Bias2 = 9.5µA, Differential Input, Duty Cycle = 50%; unless otherwise noted) THD, SNR, SINAD vs. Input Frequency 80 80 THD, SNR, SINAD vs. Sample Rate THD, SNR, SINAD (dB) THD, SNR, SINAD (dB) 70 SNR THD 70 60 THD SNR SINAD 60 50 40 30 20 100 101 102 SINAD 50 40 30 20 100 101 102 NOTE: Bias1 and Bias2 currents optimized for each sample rate Input Frequency (MHz) Sample Rate (MSPS) THD, SNR, SINAD vs. Temperature 70 150 Power Dissipation vs. Sample Rate THD, SNR, SINAD (dB) Power Dissipation (mW) 68 THD 125 100 75 50 25 0 66 64 62 60 SNR 58 SINAD NOTE: Bias1 and Bias2 currents optimized for each sample rate 56 -40 -25 0 25 50 70 85 100 101 102 Temperature ( °C) Sample Rate (MSPS) Bias2 Voltage vs. Bias2 Current 0.90 IBias2 3 6 9 12 15 VBias2 0.6975 0.7535 0.796 0.8295 0.8595 Bias1 Voltage vs. Bias1 Current 3.4 3.2 3.0 IBias1 30 60 90 120 150 VBias1 2.19 2.53 2.79 3 3.22 0.85 VBias1 (V) 2.8 2.6 2.4 2.2 2.0 0 30 60 90 120 150 180 VBias2 (V) 0.80 0.75 0.70 0.65 0.60 0 3 6 9 12 15 18 IBIAS1 (µA) IBIAS2 (µA) 4 REV. 1B October 2003 SPT7851 DATA SHEET Sampling Points N-1 N N+1 tAP AIN CLK N+2 N+6 N+7 N+8 tD DOUT N-2 N-1 N Figure 1: Timing Diagram General Description The SPT7851 is an ultra-low power, 10-bit, 20 MSPS ADC. It has a pipelined architecture and incorporates digital error correction of all 10 bits. This error correction ensures good linearity performance for input frequencies up to Nyquist. The inputs are fully differential, making the device insensitive to system-level noise. This device can also be used in a single-ended mode. (See analog input section.) With the power dissipation roughly proportional to the sampling rate, this device is ideal for very low power applications in the range of 1 to 20 MSPS. Typical Interface Circuit The SPT7851 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7851 in normal circuit operation. The following sections provide a description of the functions and outline critical performance criteria to consider for achieving the optimal device performance. +3.3V Ref- In (+1.15 V) 4.7 µF + .01 µF 10 µF + CLKIN (3V Logic) +3.3V +3.3V Digital Ref+ In (+2.15 V) + 4.7 µF .01 µF 11 12 N/C N/C N/C .01 µF 0.1 µF 1 GND CLK N/C Decoupling Cap VDD2 VDD1 VDD3 VRef- VRef+ VDD1 VDD1 VDD2 VDD3 44 DNC DNC D0 (LSB) 90 µA 9.5 µA .01 µF (+1.65 V) GND Bias1 Bias2 VCM GND U1 SPT7851 D1 D2 D3 D4 D5 D6 D7 D9 Interfacing 3V Logic RFIN 51Ω 68 pF VIN+ VIN- 22 Minicircuit T1-6T GND GND 34 D8 (MSB) 23 33 AGND Note: 1. All VDD1, VDD2 and VDD3 should be tied together. 2. FB = Ferrite Bead; must be placed as close to U1 as possible. FB DGND Figure 2: Typical Interface Circuit REV. 1B October 2003 5 DATA SHEET SPT7851 Analog Input The input of the SPT7851 can be configured in various ways depending on if a single-ended or differential, AC- or DCcoupled input is desired. The AC coupled input is most conveniently implemented using a transformer with a center tapped secondary winding. The center tap is connected to the VCM pin as shown in Figure 2. To obtain low distortion, it is important that the selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the inputs attenuates kickback noise from the internal sample and hold. Figure 3 illustrates a solution (based on operational amplifiers) that can be used if a a DC-coupled single-ended input is desired. The selection criteria of the buffer op-amps is as follows: • Open loop gain > 75dB • Gain bandwidth product > 50MHz • Total Harmonic Distortion ≤ –75dB • Signal-to-Noise Ratio > 75dB R3 R3 VCM (R3)/2 Input Voltage (±0.5V) R2 R2 – + R – + 15pF 51Ω VIN+ ADC VINR References The SPT7851 has a differential analog input. The voltages applied to the VREF+ and VREF– pins determine the input voltage range and are equal to ±(VREF+ – VREF–). This voltage range will be symmetrical about the common mode voltage. Externally generated reference voltages must be connected to these pins. (See figure 2, Typical Interface Circuit.) For best performance, these voltages should be symmetrical about the midpoint of the supply voltage. Common Mode Voltage Reference Circuit The SPT7851 has an on-board common mode voltage reference circuit (VCM). It is typically one-half of the supply voltage and can drive loads of up to 20 µA. This circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. Bias Current Circuits The bias currents suggested (Bias 1 and Bias 2 in figure 2) optimize device performance for the stated sample rate of 20 MSPS. To achieve the best dynamic performance when operating the device at sample rates other than 20 MSPS, the bias current levels should be adjusted. Table I shows the settings for Bias 1 and Bias 2 for selected sample rates. The “Bias Voltage vs Bias Current” graphs on page 4 show the relationship between the bias current and the bias voltage. Please refer to the application note for more information. Table I – Sample Rate Settings 51Ω + – 51Ω R R R Sample Rate (MHz) Bias1 (µA) 30 50 70 90 Bias2 (µA) 3.0 6.0 7.5 9.5 Figure 3: DC-coupled single-ended to differential conversion (power supplies/bypassing not shown) 1 5 Power Supplies and Grounding The SPT7851 is operated from a single power supply in the range of 2.8 to 3.6 volts. Nominal operation is suggested to be 3.3 volts. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible. 10 20 6 REV. 1B October 2003 SPT7851 DATA SHEET Clock The SPT7851 accepts a low voltage CMOS logic level at the CLK input. The duty cycle of the clock should be kept as close to 50% as possible. Because consecutive stages in the ADC are clocked in opposite phase to each other, a non-50% duty cycle reduces the settling time available for every other stage and thus could potentially cause a degradation of dynamic performance. For optimal performance at high input frequencies, the clock should have low jitter and fast edges. The rise/fall times should be kept shorter than 2ns. Overshoot and undershoot should be avoided. Clock jitter causes the noise floor to rise proportional to the input frequency. Because jitter can be caused by crosstalk on the PC board, it is recommended that the clock trace be kept as short as possible and standard transmission line practices be followed. in an all zeros output code (000…0). A positive full scale input results in an all 1’s code (111…1). The output data is available 7.5 clock cycles after the data is sampled. The input signal is sampled on the high to low transition of the input clock. Output data should be latched on the low to high clock transition as shown in figure 1, the Timing Diagram. The output data is invalid for the first 20 clock cycles after the device is powered up. Evaluation Board The EB7851 Evaluation Board is available to aid designers in demonstrating the full performance capability of the SPT7851. The board includes an on-board clock driver, adjustable voltage references, adjustable bias current circuits, single-to-differential input buffers with adjustable levels, a single-to-differential transformer (1:1), digital output buffers and 3.3/5 V adjustable logic outputs. An application note (AN7851) is also available which describes the operation of the evaluation board and provides an example of the recommended power and ground layout and signal routing. Contact the factory for price and availability. Digital Outputs The digital output data appears in an offset binary code at 3.3V CMOS logic levels. A negative full scale input results Pin Configuration D0 (LSB) VDD3 44 Pin Assignments Pin Name VIN+, VIN– Analog Inputs External Reference Inputs Input Clock Common Mode Output Voltage (1.65V typ) Bias Current (90µA typ) Bias Current (9.5µA typ) Digital Outputs (D0 = LSB) Analog Ground Analog Power Supply Digital Power Supply Digital Output Power Supply No connect Do not connect pins; leave floating Description DNC 43 DNC 42 D3 D4 D7 D2 D5 D6 D1 40 VREF+, VREF– 33 32 31 30 29 28 27 26 25 24 23 D8 D9 (MSB) GND GND GND GND GND GND GND GND GND 41 38 37 36 39 35 34 GND CLK N/C VDD3 VDD2 VDD2 VDD1 VDD1 VDD1 VREF– VREF+ 1 2 3 4 5 6 7 8 9 10 11 12 N/C 13 N/C 14 N/C 15 N/C 16 Bias 1 17 Bias 2 18 VCM 19 GND 20 VIN+ 21 VIN– 22 GND CLK VCM Bias1 Bias2 D0 – D9 GND VDD1 VDD2 VDD3 N/C DNC REV. 1B October 2003 7 DATA SHEET SPT7851 Package Dimensions TQFP-44 A B Pin 1 Index C D E F G I H J K Inches Symbol Min A B C D E F G H I J K 0.472 Typ 0.394 Typ 0.394 Typ 0.472 Typ 0.031 Typ 0.012 0.053 0.002 0.018 0.039 Typ 0-7° 0.018 0.057 0.006 0.030 Max Min Millimeters Max 12.00 Typ 10.00 Typ 10.00 Typ 12.00 Typ 0.80 Typ 0.300 1.35 0.05 0.450 1.00 Typ 0-7° 0.45 1.45 0.15 0.750 8 REV. 1B October 2003 SPT7851 DATA SHEET Ordering Information Model SPT7851 Part Number SPT7851SIT Package 44-pin TQFP Container Tray Pack Qty - Temperature range for all par ts: -40°C to +85°C.