TMC1175A

www.cadeka.com TMC1175A Video A/D Converter 8 bit, 40 Msps Features • • • • • • • • • • 8-Bit resolution 40 Msps conversion rate Low power: 100mW at 20 Msps Integral track/hold Integral and differential linearity error 0.5 LSB Single or dual +5 Volt supplies Differential phase 0.5 degree Differential gain 1.5% Three-state TTL/CMOS-compatible outputs Low cost Description The TMC1175A analog-to-digital (A/D) converter employs a two-step flash architecture to convert analog signals into 8-bit digital words at sample rates of up to 40 Msps (Megasamples per second). An integral Track/Hold circuit delivers excellent performance on signals with full-scale frequency components up to 12 MHz. Innovative architecture and submicron CMOS technology limit typical power dissipation to 100 mW. Power may be derived from either single or dual +5V supplies. Internal voltage reference resistors allow self-bias operation. Input capacitance is very low, simplifying or eliminating input driving amplifiers. All digital three-state outputs are TTL- and CMOS-compatible. The TMC1175A is available in 24-lead plastic SOIC, and 28-lead J-lead PLCC packages. Performance specifications are guaranteed from -20°C to 75°C. Applications • • • • • • • Video digitizing VGA and CCD digitizing LCD projection panels Image scanners Personal computer video boards Multimedia systems Low cost, high speed data conversion Block Diagram Coarse Quantizer VIN Track/ Hold VR+ RT RB VR– Reference Matrix Digital ErrorCorrector D7-0 Fine Quantizer CONV OE 24453A REV. 1.3.3 2/28/02 TMC1175A PRODUCT SPECIFICATION Functional Description The TMC1175A 8-bit A/D converter uses a two-step architecture to perform analog-to-digital conversion at rates up to 40 Msps. The input signal is held in an integral track/hold stage during the conversion process. Operation is pipelined, with one input sample taken and one output word provided for each CONVert cycle. The first step in the conversion process is a coarse 4-bit quantization. This determines the range of the subsequent fine 4-bit quantization step. To eliminate spurious codes, the fine 4-bit A/D quantizer output is gray-coded and converted to binary before it is combined with the coarse result to form a complete 8-bit result. V DDA VR+ +2.6V RT R+ 324Ω RREF 270Ω RB +0.6V Analog Input and Voltage References The TMC1175A converts analog signals in the range RB to RT into digital data. Input signals outside that range produce “saturated” 00h or FFh output codes. The device will not be damaged by signals within the range AGND to VDDA. Input voltage range is very flexible and extends from the +5 Volt power supply to ground. Performance is specified over the optimom 2 volt input range: 0.6V to 2.6V. However, the part will function with a full-scale range from 1.0V to 5.0V. A reduced input range may simplify analog signal conditioning circuitry, at the expense of additional noise sensitivity and reduced differential linearity. Increasing the range can improve differential linearity, but imposes a greater burden on the input signal conditioning circuitry. In many applications, external voltage reference sources are connected to the RT and RB pins. RB can be grounded. Gain and offset errors are directly related to the accuracy and stability of the applied reference voltages. Two reference pull-up and pull-down resistors connected to VR+ and VR– are provided internally for operation without external voltage reference circuitry (Figure 1). The reference voltages applied to RT and RB may be generated by connecting VR+ to RT and VR- to RB. The power supply voltage is divided by the on-chip resistors to bias the RT and RB points. This sets-up the converter for operation in its nominal range from 0.6V to 2.6V. VR– R– 81Ω 27010A Figure 1. Reference Resistors With VDDA at 5.0V, connecting VR+ to RT and grounding RB will provide an input range from 0.0V to 2.27V, while connecting RT to VDDA and RB to VR- produces a full scale range of 3.85V referenced to VDDA. External resistors may also be employed to provide arbitrary reference voltages, but they will not match the temperature coefficient of the onchip resistors as well as R+ and R-, and will cause the converter transfer function to vary with temperature. With this implementation, errors in the power supply voltage end up on the conversion data output. Because a two-step conversion process is employed, it is important that the references remain stable during the ENTIRE conversion process (two clock cycles). The reference voltage can then be changed, but any conversion in progress during a reference change is invalid. 2 REV. 1.3.3 2/28/02 PRODUCT SPECIFICATION TMC1175A Table 1. Output Coding Input Voltage RT + 1 LSB RT RT – 1 LSB ••• RB + 128 LSB RB + 127 LSB ••• RB + 1 LSB RB RB – 1 LSB Note: 1. LSB = (RT – RB) / 255 Output FF FF FE ••• 80 7F ••• 01 00 00 remain valid for tHO (Output Hold Time), satisfying any hold time requirement of the receiving circuit. The new data become valid tDO (Output Delay Time) after this rising edge of CONV. The outputs of the TMC1175A are CMOS- and TTL-compatible, and are capable of driving four low-power Schottky TTL (54/74LS) loads. An Output Enable control, OE, places the outputs in a high-impedance state when HIGH. The outputs are enabled when OE is LOW. Power and Ground To minimize noise injection into the analog section, VDDA may be connected to a separate regulated +5 volt supply. VDDD may be connected to a digital supply. Power up sequence is immaterial. Latch-up will not occur. AGND and DGND pins should be connected to a common ground plane. For optimum performance treat analog and digital PWB traces as transmission lines. Route analog connections cleanly to the TMC1175A. Segregate digital connections and if necessary terminate clocks to eliminate ringing. Prevent digital returm currents from flowing across analog input sections of the TMC1175A. Digital Inputs and Outputs Sampling of the applied input signal takes place on the falling edge of the CONV signal (Figure 2). The output word is delayed by 2 1/2 CONV cycles. It is then available after the rising edge of CONV. The previous data on the output tSTO Sample N Sample N+1 tPWL CONV tDO D7-0 ORP ORN tHO Data N–3 Data N–2 tDIS Hi-Z Data N–1 tENA tPWH 1/fS Sample N+2 Sample N+3 VIN Data N OE 24455A Figure 2. Conversion Timing REV. 1.3.3 2/28/02 3 TMC1175A PRODUCT SPECIFICATION V(1) V(2) V(3) V(4) Analog input External Clock Upper comparators block Upper data S (1) C (1) S (2) C (2) S (3) C (3) S (4) C (4) MD (0) MD (1) MD (2) MD (3) Lower reference voltage RV (0) RV (1) RV (2) RV (3) Lower comparators A block Lower data A S (1) H (1) LD (-1) C (1) S (3) H (3) LD (1) C (3) Lower comparators B block Lower data B H (0) LD(-2) C (0) S (2) H (2) LD(0) C (2) S (4) H (94) LD(2) Digital output Out(-2) Out(-1) Out(0) Out(1) 65-7568 Figure 3. Internal Timing Pin Assignments OE 1 DGND 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 VDDD 11 CONV 12 M7 Package 24 23 22 21 20 19 18 17 16 15 14 13 DGND RB VR– AGND AGND VIN VDDA RT VR+ VDDA VDDA VDDD 25 24 23 22 21 20 19 18 17 16 15 14 13 A GND A GND VIN N/C VDDA RT VR+ VR– 26 RB 27 DGND 28 N/C 1 OE 2 DGND 3 D0 4 D1 5 D2 6 D3 7 N/C 8 D4 9 D5 10 D6 11 VDDA VDDA VDDD N/C CONV VDDD 12 D7 R3 Package 24454A 4 REV. 1.3.3 2/28/02 PRODUCT SPECIFICATION TMC1175A Pin Descriptions Pin Number Pin Name Inputs VIN RT 19 17 23 20 RT – RB Analog Input. The input voltage conversion range lies between the voltages applied to the RT and RB pins. 2.6V Reference Voltage Top Input. RT is the top input to the reference resistor ladder. A DC voltage applied to RT defines the positive end of the VIN conversion range. Reference Voltage Bottom Input. RB is the bottom input to the reference resistor ladder. A DC voltage applied to RB defines the negative end of the VIN conversion range. Reference Voltage Top Source. VR+ is the internal pull-up reference resistor for self-bias operations. Reference Voltage Bottom Source. VR- is the internal pull-down reference resistor for self-bias operations. CMOS CMOS Output Enable. (CMOS-compatible) When LOW, D7-0 are enabled. When HIGH, D7-0 are in a high-impedance state. Convert (Clock) Input. (CMOS-compatible) VIN is sampled on the falling edge of CONV. Data Outputs (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Data is output following the rising edge of CONV. Analog Supply Voltage. Independent +5 volt power connection to analog comparator circuits. Digital Supply Voltage. Independent +5 volt power connection to digital error correction and output drivers. Analog Ground. Connect to the system analog ground plane. Digital Ground. Connect to the system analog ground plane. Not Connected. M7 R3 Pin Type Pin Function Description RB 23 27 0.6V VR+ VR– OE CONV Outputs D7-0 Power VDDA VDDD AGND DGND No Connect N/C 16 22 1 12 19 26 2 14 10–3 12–9, 7–4 17, 18, 21 13, 16 24, 25 3, 28 1, 8, 15, 22 CMOS/ TTL +5V +5V 0.0V 0.0V open 14, 15, 18 11, 13 20, 21 2, 24 Bandwidth Specification Notes The specification for bandwidth of an A/D converter is somewhat different from the normal frequency-response specification used in amplifiers and filters. An understanding of the differences will help in selecting converters properly for particular applications. A/D conversion comprises two distinct processes: sampling and quantizing. Sampling is “grabbing” a snapshot of the input signal and holding it steady for quantizing. The quantizing process is approximating the analog input, which may be any value within the conversion range, with its nearest numerical value. While sampling is a high-frequency process, quantizing operates on a dc signal, held steady by the track/hold circuit. Therefore, the sampling process is what relates to the dynamic characteristics of the converter. REV. 1.3.3 2/28/02 Sampling involves an aperture time, the time during which the track/hold is trying to capture the input signal and settle on a dc value to hold. It is analogous to the shutter speed of a camera: the shorter the aperture (or faster the shutter) the less the signal will be blurred, and the less uncertainty there will be in the quantized value. For example, a 10 MHz sinewave with a 1V peak amplitude (2Vp-p) has a maximum slew rate of 2πfA at zero crossing, or 62.8V/µs. With an 8-bit A/D converter, q (the quantization step size) = 2V/255 = 7.8mV. The input signal will slew one LSB in 124ps. To limit the error (and noise) contribution due to aperture effects to 1/2LSB, the aperture must be shorter than 62ps. 5 TMC1175A PRODUCT SPECIFICATION This is the primary reason that the signal to noise ratio drops off as full scale frequency increases. Note, also, that the slew rate is directly proportional to signal amplitude, A. A/Ds will handle lower-amplitude signals of higher bandwidth. All this is of particular interest in applications such as digitizing analog VGA RGB signals, or the output of a CCD imaging chip. These data are effectively pre-sampled: there is a period of rapid slewing from one pixel value to another, followed by a relatively stable dc level before the signal slews to the next pixel value. The goal is, of course, to sample on these pixel values, not on the slewing between pixels. During the aperture time, the A/D sees essentially a dc signal, and classic bandwidth considerations are not important. As long as the input circuit can slew and settle to the new value in the prescribed period, an accurate conversion will be made. The TMC1175A is capable of slewing a full 2V and settling between samples taken as little as 25ns apart, making it ideal for digitizing analog VGA and CCD outputs. Equivalent Circuits and Threshold Level VDD VDD p Data or Control Input n p Output n GND 27014B GND 27011B Figure 4. Equivalent Digital Input Circuit Figure 5. Equivalent Digital Output Circuit VDDA tENA VIN OE Three-State Outputs tDIS 0.5V 2.0V 0.8V 0.5V 65-1175A-07 AGND 27052A High Impedance Figure 6. Equivalent Analog Input Circuit Figure 7. Threshold Levels for Three-State Measurements 6 REV. 1.3.3 2/28/02 PRODUCT SPECIFICATION TMC1175A Absolute Maximum Ratings Parameter Power Supply Voltages VDDA VDDD VDDA AGND Digital Inputs Applied Voltage2 Forced Current3,4 Analog Inputs Applied Voltage2 Forced Current Outputs Applied Voltage2 Forced Current3,4 Short Circuit Duration Temperature Operating, Ambient Junction Storage Lead Soldering Vapor Phase Soldering 10 seconds 1 minute 3,4 (beyond which the device may be damaged)1 Conditions Measured to AGND Measured to DGND Measured to VDDD Measured to DGND Measured to DGND Min -0.5 -0.5 -0.5 -0.5 -0.5 -10.0 Measured to AGND -0.5 -10.0 Measured to DGND Single output in HIGH state to ground -20 -65 -0.5 -6.0 Typ Max 7.0 7.0 0.5 0.5 VDDD + 0.5 10.0 VDDA + 0.5 10.0 VDDD + 0.5 6.0 1 110 150 150 300 220 V mA V mA V mA sec °C °C °C °C °C V Unit V Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device REV. 1.3.3 2/28/02 7 TMC1175A PRODUCT SPECIFICATION . Operating Conditions Parameter VDDD VDDA AGND fS Digital Power Supply Voltage Analog Power Supply Voltage Analog Ground (Measured to DGND) Conversion Rate TMC1175A-20 TMC1175A-30 TMC1175A-40 tPWH CONV Pulsewidth, HIGH TMC1175A-20 TMC1175A-30 TMC1175A-40 tPWL CONV Pulsewidth, LOW TMC1175A-20 TMC1175A-30 TMC1175A-40 VRT VRB VRT-VRB VIN VIH VIL IOH IOL TA Reference Voltage, Top Reference Voltage, Bottom Reference Voltage Differential Analog Input Range Input Voltage, Logic HIGH Input Voltage, Logic LOW Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air -20 15 13 12 15 12 12 2.0 0 1.0 VRB 0.7 x VDDD GND 2.6 0.6 VDDA 3.0 5.0 VRT VDDD 0.3 x VDDD -4.0 4.0 75 Min 4.75 4.75 -0.1 Nom 5.0 5.0 0 Max 5.25 5.25 0.1 20 30 40 Units V V V Msps Msps Msps ns ns ns ns ns ns V V V V V V mA mA °C Electrical Characteristics Parameter IDD Power Supply Current1 Conditions VDDD = VDDA = Max, CLOAD = 35pF fS = 20Msps fS = 30Msps fS = 40Msps IDDQ Power Supply Current, Quiescent Total Power Dissipation VDDD = VDDA = Max CONV = LOW CONV = HIGH PD VDDD = VDDA = Max, CLOAD = 35pF fS = 20Msps fS = 30Msps fS = 40Msps CAI RIN 8 Input Capacitance, Analog Input Resistance CONV = LOW CONV = HIGH 500 100 125 150 4 12 1000 160 185 210 mW mW mW pF pF kΩ REV. 1.3.3 2/28/02 Min Typ1 20 25 30 7 10 Max 30 35 40 18 20 Units mA mA mA mA mA PRODUCT SPECIFICATION TMC1175A Electrical Characteristics (continued) Parameter ICB RREF IIH IIL IOZH IOZL IOS VOH Input Current, Analog Reference Resistance Input Current, HIGH Input Current, LOW Hi-Z Output Leakage Hi-Z Output Leakage Short-Circuit Current Output Voltage, HIGH IOH = -100µA IOH = -2.5mA IOH = Max VOL CDI CDO Output Voltage, LOW Digital Input Capacitance Digital Output Capacitance IOL = Max 4 10 VDDD-0.3 3.5 2.4 0.4 10 VDDD = Max, VIN = VDDD VDDD = Max, VIN = 0V VDDD = Max, VIN = VDDD VDDD = Max, VIN = 0V 200 270 Conditions Min Typ1 Max ±1 340 ±5 ±5 ±5 ±5 -30 Units µA Ω µA µA µA µA mA V V V V pF pF Note: 1. Typical values with VDDD = VDDA = Nom and TA = Nom, Minimum/Maximum values with VDDD = VDDA = Max and TA = Min. Switching Characteristics Parameter tSTO tHO tDO tENA tDIS Sampling Time Offset Output Hold Time Output Delay Time Output Enable Time Output Disable Time CLOAD = 15pF CLOAD = 15pF Conditions Min 2 5 20 27 42 Typ 5 Max 8 Units ns ns ns ns ns REV. 1.3.3 2/28/02 9 TMC1175A PRODUCT SPECIFICATION System Performance Characteristics Parameter ELI ELD BW Integral Linearity Error, Independent Differential Linearity Error Bandwidth2 VRT = 2.6V VRB = 0.6V VRT = 2.6V VRB = 0.6V TMC1175A-20 TMC1175A-30 TMC1175A-40 30 RT – VIN for most positive code transition RB – VIN for most negative code transition fS = 14.3Msps NTSC 40 IRE Mod Ramp VDDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V fS = 14.3Msps NTSC 40 IRE Mod Ramp VDDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V fS = 20Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz fIN = 2.48MHz fIN = 6.98MHz fIN = 10.0MHz fS = 30Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz fIN = 2.48MHz fIN = 6.98MHz fIN = 10.0MHz fIN = 12.0MHz fS = 40Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz fIN = 2.48MHz fIN = 6.98MHz fIN = 10.0MHz fIN = 12.0MHz 40 38 36 34 32 45 43 41 38 36 dB dB dB dB dB 42 40 38 33 30 47 45 43 39 37 dB dB dB dB dB 44 43 41 37 48 47 45 42 dB dB dB dB -8 30 -25 40 1.5 -42 60 2.7 Conditions Min Typ1 ±0.5 ±0.3 Max ±1 ±1 10 12 12 Units LSB LSB MHz MHz MHz ps mV mV % EAP EOT EOB dg Aperture Error Offset Voltage, Top Offset Voltage, Bottom Differential Gain dp Differential Phase 0.5 1.0 deg SNR3 Signal-to-Noise Ratio 10 REV. 1.3.3 2/28/02 PRODUCT SPECIFICATION TMC1175A System Performance Characteristics (continued) Parameter SFDR4 Spurious-Free Dynamic Range fIN = 1.24MHz fIN = 2.48MHz fIN = 6.98MHz fIN = 10.0MHz fS = 30Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz fIN = 2.48MHz fIN = 6.98MHz fIN = 10.0MHz fIN = 12.0MHz fS = 40Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz fIN = 2.48MHz fIN = 6.98MHz fIN = 10.0MHz fIN = 12.0MHz 40 39 38 36 36 44 43 41 40 39 dB dB dB dB dB 42 40 37 35 34 49 45 41 40 39 dB dB dB dB dB Conditions fS = 20Msps, VRT = 2.6V, VRB = 0.6V 46 44 41 38 52 51 45 43 dB dB dB dB Min Typ1 Max Units Notes: 1. Values shown in Typ column are typical for VDDD = VDDA = +5V and TA = 25°C. 2. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes. 3. SNR values do not include the harmonics of the fundamental frequency. 4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude. REV. 1.3.3 2/28/02 11 TMC1175A PRODUCT SPECIFICATION Typical Performance Characteristics 30 25 20 IDD (mA) SFDR 15 10 5 0 0 10 20 30 40 60 50 40 30 20 10 0 0 2 4 6 fs = 20 Msps fs = 30 Msps fs = 40 Msps 8 10 12 Figure 8. Typical IDD vs fS Figure 9. Typical SFDR vs fIN and fS 50 40 30 SNR 20 10 0 0 2 4 6 SNR fs = 20 Msps fs = 30 Msps fs = 40 Msps 50 40 30 20 10 0 8 10 12 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fs = 20 Msps fs = 33 Msps Figure 10. Typical SNR vs fIN and fS Figure 11. Typical SNR vs Full Scale Input Range Applications Discussion The circuit in Figure 12 employs a band-gap reference to generate a variable RT reference voltages for the TMC1175A as well as a bias voltage to offset the wideband input amplifier to mid-range. An "offset adjust" is also shown for varying the mid-range voltage level. The operational amplifier in the reference circuitry is a standard 741-type. The voltage reference at RT can be adjusted from 0.0 to 2.4 volts while RB is grounded. Diodes are used to restrict the wideband amplifier output to between -0.7V and VDD +0.7V. Diode protection is good practice to limit the analog input voltage at VIN to the safe operating range. The circuit in Figure 13 shows self-bias of RT and RB by connection to VR+ and VR-. This sets up a 0.6 to 2.6 Volt input range for VIN. The input range is susceptible to power supply variation since the voltages on RT and RB are directly derived from VDDA. The video input is AC-coupled and biased at a adjustable midpoint of the A/D input range. This circuit offers the advantage of minimum support circuitry for the most cost-sensitive applications. In Figure 14, an external band-gap reference sets RT to +1.2 Volts while RB is grounded. The internal pull-up resistor, R+, provides the bias current for the band-gap reference. The A/D converter input is biased to the mid-point of the input range. 12 REV. 1.3.3 2/28/02 PRODUCT SPECIFICATION TMC1175A Regulated +5V 0.1µF LM385 0.1µF 1kΩ +5V Gain Adjust 2kΩ 0.1mF + 1kΩ 1kΩ Video Input 75Ω + 455Ω 455Ω +5V Wideband Op-amp 0.1µF RB VRV IN A GND 20Ω 2V V DDA VR+ RT TMC1175A D 7-0 OE CONV D GND V DDD +5V 0.1µF 27056A Figure 12. Typical Interface Circuit-High Performance Grounding The TMC1175A has separate analog and digital circuits. To keep digital system noise from the A/D converter, it is recommended that power supply voltages (VDDD and VDDA) originate from separate sources with VDDA regulated, and that ground connections (DGND and AGND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. The digital circuitry that gets its input from the TMC1175A should be referred to the system digital ground plane. 0.1µF +5V 0.1µF Offset Adjust V DDA +5V 2.2kΩ 2kΩ 0.1µF VR+ RT V DDD TMC1175A RB VRD 7-0 OE V IN A GND CONV D GND 0.1µF Video Input 560Ω 0.1µF Printed Circuit Board Layout Designing with high performance mixed-signal circuits demands printed circuits with ground planes. Wire-wrap is not an option, even for breadboarding. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor A/D conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VIN, RT, RB, VR+, VR-) as short as possible and as far as possible from all digital signals. The TMC1175A should be located near the board edge, close to the analog input connectors. The power plane for the TMC1175A should be separate from that which supplies the rest of the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the TMC1175A is the same as that of the system's digital circuitry, power to the TMC1175A should be decoupled with ferrite beads and 0.1µF capacitors to reduce noise. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. 10µF 75Ω 24458A Figure 13. Typical Interface Circuit – Low Cost 0.1µF +5V 0.1µF V DDA VR+ RT LM385 1kΩ RF Input 10µF 0.1µF V DDD TMC1175A RB VRV IN D 7-0 OE CONV D GND 24457A 2. 56Ω 1kΩ A GND 3. Figure 14. Typical Interface Circuit – Stabilized Reference REV. 1.3.3 2/28/02 13 TMC1175A PRODUCT SPECIFICATION 4. Decoupling capacitors should be applied liberally to VDD pins. Remember that not all power supply pins are created equal. They supply different circuits on the integrated circuit, each of which generate varying amounts and types of noise. For best results, use 0.1µF ceramic capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC1175A, the voltage reference, or the analog inputs. Capacitive coupling of digital power supply noise from this layer to the TMC1175A and its related analog circuitry can have an adverse effect on performance. 6. CONV should be handled carefully. Jitter and noise on this clock may degrade performance. Terminate the clock line at the CONV input, if required, to eliminate overshoot and ringing. Evaluation Board An evaluation board is available that implements good interface practices and provide a convenient testbed for developing system applications and circuit variations. An on-board D/A converter is provided to reconstruct the digitized signal and to evaluate converter performance. Contact your sales representative for information. 5. 14 REV. 1.3.3 2/28/02 PRODUCT SPECIFICATION TMC1175A Mechanical Dimensions 24 Lead SOIC (5.4 mm) Package Inches Min. .067 .004 .014 .006 .587 .205 .295 Symbol A A1 B C D E E1 e h L N α° ccc Millimeters Min. 1.70 0.10 0.36 0.15 14.90 5.20 7.50 Max. .075 .012 .020 .012 .610 .220 .319 Max. 1.90 0.31 0.51 0.30 15.50 5.60 8.10 Notes .050 BSC .010 .020 .016 24 0 8 .004 .050 1.27 BSC 0.25 0.50 0.41 1.27 24 0 8 0.10 24 13 E1 E 1 D A e B 12 h x 45° A1 SEATING PLANE α -CLEAD COPLANARITY ccc C C L REV. 1.3.3 2/28/02 15 TMC1175A PRODUCT SPECIFICATION Mechanical Dimensions (continued) 28 Lead PLCC Package Inches Min. Max. .165 .180 .090 .120 .020 — .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 — .004 Millimeters Min. Max. 4.19 4.57 2.29 3.05 .51 — .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 — 0.10 Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45° 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm) Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc 3 2 E E1 J D D1 D3/E3 B1 e J A A1 A2 B –C– LEAD COPLANARITY ccc C 16 REV. 1.3.3 2/28/02 TMC1175A PRODUCT SPECIFICATION Ordering Information Product Number TMC1175AM7C20 TMC1175AM7C30 TMC1175AM7C40 TMC1175AR3C20 TMC1175AR3C30 TMC1175AR3C40 Conversion Rate Temperature Range 20 Msps 30 Msps 40 Msps 20 Msps 30 Msps 40 Msps TA = -20°C to 75°C TA = -20°C to 75°C TA = -20°C to 75°C TA = -20°C to 75°C TA = -20°C to 75°C TA = -20°C to 75°C Screening Commercial Commercial Commercial Commercial Commercial Commercial Package 24-Lead SOIC 24-Lead SOIC 24-Lead SOIC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC Package Marking 1175AM7C20 1175AM7C30 1175AM7C40 1175AR3C20 1175AR3C30 1175AR3C40 2/28/02 0.0m 002 Stock#DS7001175A Addendum 03/03/09 CADEKA Adds New Package Option TMC1175AW7C20 20 Msps TA = -20°C to 75°C Commercial 24-Lead SOIC (0.300 wide body SOIC) 1175AW7C20 24 Lead SOIC, 0.300 Wide Body Package 24 13 Symbol A A1 B C D E e H h L N α ccc Notes: Inches Min. Max. .093 .104 .004 .012 .013 .020 .009 .013 .599 .614 .290 .299 .050 BSC .394 .419 .010 .016 0° .020 .050 8° Millimeters Min. Max. 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.36 7.60 1.27 BSC 10.00 10.65 0.25 0.40 0° 0.51 1.27 8° Notes E H 1 12 5 2 2 D A e B A1 SEATING PLANE –C– 24 24 3 6 — .004 — 0.10 LEAD COPLANARITY ccc C 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 4. Terminal numbers are shown for reference only. h x 45° C α L 3. "L" is the length of terminal for soldering to a substrate. 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. 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