CAT310_07

CAT310 10 Channel Automotive LED Display Driver FEATURES • • • • • • • • • Automotive “load dump” protection (40V) 10 independent LED channels Up to 50mA output per channel Overvoltage detection at 19V Serial interface for channel programming Daisy chain output for multi-driver cascading LED blanking control Operating temperature from -40ºC to +125ºC 20-pin SOIC package PRODUCT DESCRIPTION The CAT310 is a 10-channel LED driver for automotive and other lighting applications. All LED output channels are driven from a low onresistance open-drain High Voltage CMOS Nch-FETs and are fully compliant with “Load Dump” transients of up to 40 volts. The LED bias current of each channel can be set independently using an external series ballast resistor, making the device ideal for multi-color instrumentation displays. A high-speed serial interface (suitable with both 3.3 volt and 5 volt systems) feeding a 10 bit shift register is used to program the desired state (on/off) of each channel. The device offers a blanking control pin (BLANK) which can be used to disable all channels on demand. A serial output data pin (SOUT) is provided to daisy-chain devices in large cluster LED applications During initial power up all channels are reset and cleared via an under-voltage lock out (UVLO) detector and for added protection all channels are disabled in the event of a battery over-voltage condition (19 volts or more). APPLICATIONS • • • • Automotive lighting White and other color high brightness LEDs Multi-color high-brightness LED cluster displays General LED lighting ORDERING INFORMATION Part Number CAT310W Package SOIC-20 Lead free Quantity per Reel 1000 Package Marking CAT310W For Ordering Information details, see page 10. TYPICAL APPLICATION CIRCUIT PIN DIAGRAM SOIC 20-pin package © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc No. 25087, Rev. 1 CAT310 ABSOLUTE MAXIMUM RATINGS Parameter VCC voltage Input voltage range (SIN, SCLK, BLANK, XLAT) SOUT voltage range Peak OUT0 to OUT9 voltage VBATT input voltage DC output current on OUT0 to OUT9 Storage Temperature Range Operating Junction Temperature Range Lead Soldering Temperature (10sec.) ESD Rating: Low Voltage Pins Human Body Model Machine Model ESD Rating: VBATT, OUT[0:9] pins Human Body Model Machine Model Rating 7 -0.3V to VCC+0.3V -0.3V to VCC+0.3V 40 40 70 -55 to +160 -40 to +150 300 3000 300 1000 100 Unit V V V V V mA °C °C °C V V RECOMMENDED OPERATING CONDITIONS Parameter VCC Voltage applied to OUT0 to OUT9 Output current on OUT0 to OUT9 Ambient Temperature Range Range 3.0 to 5.5 9 to 17 0 to 50 -40 to +125 Unit V V mA °C ELECTRICAL OPERATING CHARACTERISTICS DC Characteristics VCC = 5.0V, -40ºC ≤ TA ≤ 125 ºC, over recommended operating conditions unless specified otherwise. Symbol ISTBY VOVP VUVLO RSW IO(n)LKG IXLAT IBLANK VIH VIL IIL VOH VOL Name Standby Quiescent Current VBATT Over Voltage Protection Trigger threshold VCC Under Voltage Lockout Trigger threshold Switch on resistance for OUT0 to OUT9 OUT0 to OUT9 Output Switch Leakage XLAT Internal Pull-down current BLANK Internal Pull-up current Logic high input voltage Logic low input voltage Logic Input leakage current (SCLK, SIN) SOUT logic high output voltage SOUT logic low output voltage Conditions Static input signal. All outputs turned off. Min 17 Typ 1 19 1.7 IO(n) = 30mA V(OUT(n)) = 15V XLAT = VCC XLAT = 0.3V BLANK = 0V BLANK = VCC - 0.3V VI = VCC or GND IOH = -1mA IOL = 1mA 4 1 4 1 0.3 VCC -5 VCC -0.3V 2 5 0.1 10 3 10 3 0 Max 10 21 2.5 12 10 30 6 30 6 0.7VCC 5 0.3 Units µA V V Ω µA µA µA V µA V © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 2 Doc No. 25087, Rev. 1 CAT310 ELECTRICAL OPERATING CHARACTERISTICS Switching Characteristics VCC = 5.0V, -40ºC ≤ TA ≤ 125 ºC, over recommended operating conditions unless specified otherwise. Symbol SCLK fSCLK twh/wl SIN tsu th XLAT tw th tr tf tpd tpd tpd Name SCLK Clock Frequency SCLK Pulse width Setup time SIN to SCLK Hold time SIN to SCLK XLAT Pulse width Hold time SCLK to XLAT SOUT rise time (10% to 90%) SOUT fall time (90% to 10%) Propagation delay time Propagation delay time Propagation delay time SIN to SCLK CL = 15pF CL = 15pF Blank ↑ to OUT(n) Blank ↓ to OUT(n) SCLK to SOUT Conditions High or Low Min 30 10 10 20 20 20 15 25 25 25 Typ Max 10 Units MHz ns ns ns ns ns ns ns ns ns ns All logic inputs contain Schmitt trigger inputs. BLOCK DIAGRAM © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 25087, Rev. 1 CAT310 PIN DESCRIPTIONS VCC is the supply input for the internal logic and is compatible with both 3.3V and 5V systems. The logic is held in a reset state until VCC exceeds 2.5V. It is recommended that a small bypass ceramic capacitor (1uF) be placed between VCC and GND pins on the device. SIN is the CMOS logic pin for delivering the serial input data stream into the internal 10-bit shift register. The most recent or last data value in the serial stream is used to configure the state of output channel “zero” (OUT0). During the initial power up sequence all contents of the shift register are reset and cleared to zero. BLANK is the CMOS logic input (active high) used to temporarily disable all outputs. An internal pull-up current of 10 microampere is present on this pin. The BLANK pin must be driven to a logic low in order for channel outputs to resume normal operation. An external pulldown resistance of 10kΩ or less is adequate for logic low. SCLK is the CMOS logic pin used to clock the internal shift register. On each rising edge of clock, the serial data will advance through one stage of the shift register. SOUT is the CMOS logic output used for daisy chain applications. The serial output data stream is fed from the last stage of the internal 10-bit shift register. On each rising edge of the clock, the SOUT value will be updated. The data value present on this pin is identical to the data value being used for configuring the state of output channel nine (OUT9). At initial power up, the SOUT data stream will contain all zeroes until the shift register has been fully loaded. VBATT input monitors the battery voltage. If an over-voltage, above 19V typical, is detected, all outputs are disabled. Upon conclusion of the over-voltage condition, all outputs resume normal operation. The current drawn by the VBATT pin is less than 1 microampere during normal operation. XLAT is the CMOS logic input used to transfer data from the 10-bit shift register into the output channel latches. An internal pulldown current of 10 microampere is present on this pin. When XLAT is low, the state of each output channel remains unchanged. When XLAT is driven high, the contents of the shift register appear at their respective output channels. An external pull-up resistance of 10kΩ or less is adequate for logic high. OUT0-OUT9 PGND, GND pins should be connected to the ground on the PCB. are the ten LED outputs connected internally to the switch N-channel FETs. They sink currents up to 50mA per channel and can withstand transients up to 40V compatible with automotive “load dump”. The output on-resistance is 5Ω, and the offresistance is 5MΩ. PIN TABLE Pin Number 1 2 3 4 5 6-10 11-15 16 17 18 19 20 Pin Name SCLK XLAT SIN SOUT GND OUT4 - OUT0 OUT9 - OUT5 PGND VBATT VCC BLANK N.C. Description/Function Clock input for the data shift register. Control input for the data latch. Serial data input. Serial data output. Ground. Open drain outputs. Open drain outputs. Ground for LED driver outputs. Battery sense input. Power supply voltage for the logic Blank input. When BLANK is high, all the output drivers are turned off. No connect. 4 Doc No. 25087, Rev. 1 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT310 TYPICAL CHARACTERISTICS VCC = 5V, VBATT = 14V, TAMB = 25ºC, unless otherwise specified. VBATT Overvoltage Detection Amplitude between 16V and 26V BLANK and Output waveform 18V XLAT pull-down Current vs. Input Voltage 14 12 XLAT CURRENT [uA] 10 8 6 4 2 0 0 1 2 3 4 XLAT VOLTAGE [V] 5 125ºC 85ºC -40ºC 25ºC BLANK pull-up Current vs. Input Voltage 14 BLANK CURRENT [uA] 12 10 8 6 4 2 0 0 1 2 3 4 BLANK VOLTAGE [V] 5 VCC = 5V 85ºC 125ºC 25ºC -40ºC VBATT Load Dump 40V Switch On-resistance vs. VCC 12 SWITCH ON RESISTANCE [ Ω ] 10 125ºC 8 6 4 2 0 2 3 4 5 VCC VOLTAGE [V] 6 -40ºC 25ºC 85ºC © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 25087, Rev. 1 CAT310 TYPICAL CHARACTERISTICS VCC = 5V, VBATT = 14V, TAMB = 25ºC, unless otherwise specified. Output Channel Leakage vs. Bias Voltage 14 OUTPUT PIN LEAKAGE [uA] 12 10 8 6 4 2 0 10 11 12 13 14 15 16 OUTPUT PIN BIAS VOLTAGE [V] 85ºC 125ºC -40ºC 25ºC QUIESCENT CURRENT[uA] Quiescent Current vs. Temperature 20 15 10 5 0 -50 -25 0 25 50 75 100 125 TEMPERATURE [ºC] VBATT Overvoltage Detection vs. Temperature OVERVOLTAGE DETECTION [V] 24 22 20 18 16 14 -50 -25 0 25 50 75 100 125 TEMPERATURE [ºC] VCC Undervoltage Lockout vs. Temperature UNDERVOLTAGE LOCKOUT [V] 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -50 -25 0 25 50 75 100 125 TEMPERATURE [ºC] © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 6 Doc No. 25087, Rev. 1 CAT310 FUNCTIONAL DESCRIPTION The CAT310 implements a 10-bit serial-in shift register for storing the setting of the ten outputs. Serial input data SIN are clocked into the shift register on the rising edge of the clock. At the 10th clock pulse, the first data bit entered is outputted from the shift register to SOUT. The following clock pulses will output the following data bits onto SOUT. The output data pattern replicates the input data stream with a delay of ten clock pulses. The 10-bit data pattern present in the shift register is stored in the 10-bit data latch when Serial to Parallel Shift Register CLK → SIN → the latch signal XLAT is logic high. When XLAT transitions to logic low, data are latched and stay unchanged for as long as XLAT remains low. The last serial input data corresponds to OUT0. The serial input data that was received 10 clock pulse ago is stored in OUT9. When the BLANK input is logic high, all the output switches are in the off state. If the BLANK input is low, the 10-bit data latches control the 10 output switches. A data bit value of zero keeps the switch off. A data bit value of one keeps the switch on. Data Latch XLAT → Bit 0 ↓ LED OUT0 Bit 1 ↓ LED OUT1 Bit 2 ↓ LED OUT2 Bit 3 ↓ LED OUT3 Bit 4 ↓ LED OUT4 Bit 5 ↓ LED OUT5 Bit 6 ↓ LED OUT6 Bit 7 ↓ LED OUT7 Bit 8 ↓ LED OUT8 Bit 9 ↓ LED OUT9 → SOUT TIMING DIAGRAM © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 25087, Rev. 1 CAT310 APPLICATION INFORMATION For applications with a large number of LEDs, several CAT310 drivers can be daisy chained. The serial data output pin (SOUT) of the first driver is connected to the second driver data input pin (SIN). This sequence is repeated until the last driver is linked. All drivers are controlled by the same clock signal. Figure 1 shows an example with three CAT310 devices driving a total of 30 LEDs in parallel. The controller transmits the serial data sequentially through the CAT310 devices. For N drivers connected in cascade, after 10 x N clock pulses, the data are latched with one single XLAT transition. Figure 1. Daisy Chain Application Diagram © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8 Doc No. 25087, Rev. 1 CAT310 PACKAGE OUTLINE DRAWING SOIC 20-Lead 300mils (W) SYMBOL MIN NOM MAX A A1 A2 b E1 E 2.36 0.10 2.05 0.31 0.20 12.60 10.01 7.40 0.25 0.40 0° 5° 2.49 2.64 0.30 2.55 0.41 0.27 12.80 10.30 7.50 1.27 BSC 0.51 0.33 13.00 10.64 7.60 0.75 c D E E1 e h L 0.81 1.27 8° 15° b PIN#1 IDENTIFICATION e θ θ1 TOP VIEW D h h θ1 A A2 θ θ1 END VIEW A1 SIDE VIEW L c For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) (2) All dimensions are in millimeters. Angles in degrees. Complies with JEDEC MS-013. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc No. 25087, Rev. 1 CAT310 EXAMPLE OF ORDERING INFORMATION Prefix CAT Device # 310 Suffix W – T1 Product Number Optional Company ID Package W: SOIC Tape & Reel T: Tape & Reel 1: 1000/Reel Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is Matte-Tin. (3) The device used in the above example is a CAT310W–T1 (SOIC, Tape & Reel). © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 10 Doc No. 25087, Rev. 1 CAT310 REVISION HISTORY Date 05/05/2005 08/22/2007 Revision 00 1 Reason Initial issue Update Ordering Information Update Package Outline Drawing Add Example of Ordering Information Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™ and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com © Catalyst Semiconductor, Inc. Characteristics subject to change without notice Document No: 25087 Revision: Rev. 1 Issue date: 08/22/07 11 Doc No. 25087, Rev. 1