CAT514JTE13

CAT514 8-Bit Quad Digital POT FEATURES s Output settings retained without power s Output range includes both supply rails s 4 independently addressable outputs s 1 LSB Accuracy s Serial µP interface s Single supply operation: 2.7V-5.5V s Setting read-back without effecting outputs APPLICATIONS s Automated product calibration. s Remote control adjustment of equipment s Offset, gain and zero adjustments in Self- Calibrating and Adaptive Control systems. s Tamper-proof calibrations. DESCRIPTION The CAT514 is a quad 8-Bit Memory DAC designed as an electronic replacement for mechanical potentiometers and trim pots. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for systems capable of self calibration, and applications where equipment which is either difficult to access or in a hazardous environment, requires periodic adjustment. The 4 independently programmable DAC's have an output range which includes both supply rails. Output settings, stored in non-volatile EEPROM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each output can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DAC’s output. FUNCTIONAL DIAGRAM RDY/BSY VDD 1 V REF H 14 Control of the CAT514 is accomplished with a simple 3 wire serial interface. A Chip Select pin allows several CAT514's to share a common serial interface and communication back to the host controller is via a single serial data line thanks to the CAT514’s Tri-Stated Data Output pin. A Rdy/Bsy output working in concert with an internal low voltage detector signals proper operation of EEPROM Erase/Write cycle. The CAT514 is available in the 0 to 70° C Commercial and –40° C to + 85° C Industrial operating temperature ranges and offered in 14-pin plastic DIP and SOIC packages. PIN CONFIGURATION DIP Package (P) VDD DAC 1 13 V OUT 1 SOIC Package (J) 1 2 3 14 13 VREFH VOUT1 VOUT2 VOUT3 VOUT4 VREFL GND 3 PROG 7 PROGRAM CONTROL 1 2 3 4 14 13 CLK RDY/BSY CS DI DO PROG DI 5 DAC 2 2 DATA REGISTER & EEPROM DAC 3 12 V OUT 2 12 CAT 11 514 5 10 6 9 7 8 VDD VREFH CLK VOUT1 VOUT2 RDY/BSY VOUT3 VOUT4 VREFL GND CS DI DO PROG 12 4 CAT 11 514 5 10 6 9 7 8 CLK SERIAL CONTROL 11 CS 4 V OUT 3 DAC 4 10 V OUT 4 SERIAL DATA OUTPUT REGISTER 6 DO CAT514 8 GND 9 V L REF © 2000 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25075-00 2/98 M-1 CAT514 ABSOLUTE MAXIMUM RATINGS* Supply Voltage VDD to GND ...................................... –0.5V to +7V Inputs CLK to GND ............................ –0.5V to VDD +0.5V CS to GND .............................. –0.5V to VDD +0.5V DI to GND ............................... –0.5V to VDD +0.5V PROG to GND ........................ –0.5V to VDD +0.5V VREFH to GND ........................ –0.5V to VDD +0.5V VREFL to GND ......................... –0.5V to VDD +0.5V Outputs D0 to GND ............................... –0.5V to VDD +0.5V VOUT 1– 4 to GND ................... –0.5V to VDD +0.5V Operating Ambient Temperature Commercial (‘C’ suffix) .................... 0°C to +70°C Industrial (‘I’ suffix) ...................... – 40°C to +85°C RELIABILITY CHARACTERISTICS Symbol VZAP(1) ILTH(1)(2) Notes: Junction Temperature ..................................... +150°C Storage Temperature ....................... –65°C to +150°C Lead Soldering (10 sec max) .......................... +300°C * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. Parameter ESD Susceptibility Latch-Up Min 2000 100 Max Units Volts mA Test Method MIL-STD-883, Test Method 3015 JEDEC Standard 17 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. DC ELECTRICAL CHARACTERISTICS: VDD = +2.7 to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Accuracy INL Integral Linearity Error ILOAD = 250 nA, TR = C TR = I ILOAD = 1 µA, TR = C TR = I ILOAD = 250 nA, TR = C TR = I ILOAD = 1 µA, TR = C TR = I — — — — — — — — — — — — — — — — ±1 ±1 ±2 ±2 ± 0.5 ± 0.5 ± 1.5 ± 1.5 LSB LSB LSB LSB LSB LSB LSB LSB Parameter Resolution Conditions Min 8 Typ — Max — Units Bits DNL Differential Linearity Error Logic Inputs IIH IIL VIH VIL Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage VREFH Input Voltage Range VREFL Input Voltage Range VREFH–VREFL Resistance High Level Output Voltage Low Level Output Voltage IOH = – 40 µA IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V VIN = VDD VIN = 0V — — 2 0 2.7 GND — VDD –0.3 — — — — — — — — 7k — — — 10 –10 VDD 0.8 VDD VDD -2.7 — — 0.4 0.4 µA µA V V V V Ω V V V References VRH VRL ZIN VOH VOL Logic Outputs Doc. No. 25075-00 2/98 M-1 2 CAT514 DC ELECTRICAL CHARACTERISTICS (Cont.): VDD = +2.7V to +5.5V , VREFH = +VDD, VREFL = 0V, unless otherwise specified Symbol FSO ZSO IL ROUT PSSR TCO TCREF Parameter Full-Scale Output Voltage Zero-Scale Output Voltage DAC Output Load Current DAC Output Impedance Power Supply Rejection VOUT Temperature Coefficient Temperature Coefficient of VREF Resistance Supply Current (Read) Supply Current (Write) Operating Voltage Range Conditions VR = VREFH–VREFL VR = VREFH–VREFL VDD = +5V VDD = +3V ILOAD = 250 nA VREFH = +5V, VREFL = 0V VDD = +5V, ILOAD = 250nA VREFH to VREFL Min 0.99 VR — — — — — — — Typ 0.995 VR 0.005 VR — — — — — 700 Max — 0.01 VR 1 100k 150k 1 200 — Units V V µA Ω Ω LSB / V µV/ °C ppm / °C Analog Output Temperature Power Supply IDD1 IDD2 VDD Normal Operating VDD=5V VDD=3V — — — 2.7 40 1200 600 — 50 2000 1200 5.5 µA µA µA V AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified Symbol Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tBUSY tLZ tPROG tPS tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Erase/Write Cycle Time Output Delay to Low-Z Erase/Write Pulse Width PROG Setup Time Minimum CLK High Time Minimum CLK Low Time Clock Frequency DAC Settling Time to 1/2 LSB 150 100 0 50 50 — — — — — 700 150 500 300 DC — — — — — — — — — — — 400 4 400 — — — — — 3 6 8 6 — — — — — 150 150 — 5 — — — — — 1 10 10 — — ns ns ns ns ns ns ns ns ms ns ns ns ns ns MHz µs µs pF pF Parameter Conditions Min Typ Max Units CL = 100 pF see note 1 Analog tDS CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V VIN = 0V, f = 1 MHz(2) VOUT = 0V, f = 1 MHz(2) Pin Capacitance CIN COUT Notes: Input Capacitance Output Capacitance 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 25075-00 2/98 M-1 Doc. No. 25075-00 2/98 M-1 A. C. TIMING DIAGRAM CAT514 to 1 2 3 4 5 PARAM NAME TIMING MIN/MAX FROM TO t CLK H CLK t CLK H Rising CLK edge to falling CLK edge Min t CLK L Falling CLK edge to CLK rising edge t CSH t CSS CS t CSMIN t CSMIN Falling CS edge to rising CS edge t DIS t DIS DI t DIH t DIH t DO0 t LZ t LZ DO t HZ t DO1 t DO1 t HZ Rising CLK edge to D0 = high Falling CS edge to D0 becoming high impedance (Tri-State) t DO0 Rising CLK edge to end of data valid Data valid to first rising CLK edge after CS = high t CLK L t CSH Falling CLK edge for last data bit (DI) to falling CS edge Rising CS edge to next rising CLK edge Min Min t CSS Min Min Min Min 4 PROG RDY/BSY to 1 Rising CLK edge to D0 = low Rising CS edge to D0 becoming high low impedance (active output) Max (Max) Max (Max) t PS t PS t PROG Rising PROG edge to next rising CLK edge Min Min t PROG Rising PROG edge to falling PROG edge t BUSY Falling CLK edge after PROG=H to rising RDY/BSY edge Max t BUSY 2 3 4 5 CAT514 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DAC addressing is as follows: Function Power supply positive. Clock input pin.Clock input pin. Ready/Busy Output Chip Select Serial data input pin. Serial data output pin. EEPROM Programming Enable Input Power supply ground. Minimum DAC output voltage. DAC output channel 4. DAC output channel 3. DAC output channel 2. DAC output channel 1. Maximum DAC output voltage. Name VDD CLK RDY/BSY CS DI DO PROG GND VREFL VOUT4 VOUT3 VOUT2 VOUT1 VREFH DAC OUTPUT VOUT1 VOUT2 VOUT3 VOUT4 A0 0 1 0 1 A1 0 0 1 1 DEVICE OPERATION The CAT514 is a quad 8-bit Digital to Analog Converter (DAC) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile EEPROM memory and will not be lost when power is removed from the chip. Upon power up the DACs return to the settings stored in EEPROM memory. Each DAC can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT514 employs a standard 3 wire serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DAC address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT514’s read and write operations. When CS is high data may be 5 read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DAC control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DAC outputs to the settings stored in EEPROM memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT514’s clock controls both data flow in and out of the IC and EEPROM memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to EEPROM memory, even though the data being saved may already be resident in the DAC control register. No clock is necessary upon system power-up. The CAT514’s internal power-on reset circuitry loads data from EEPROM to the DACs without using the external clock. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. Doc. No. 25075-00 2/98 M-1 CAT514 VREF VREF, the voltage applied between pins VREFH andVREFL, sets the DAC’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH andVREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. READY/BUSY When saving data to non-volatile EEPROM memory, the Ready/Busy ouput (RDY/BSY) signals the start and duration of the EEPROM erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/ BSY goes low and remains low until the programming cycle is complete. During this time the CAT514 will ignore any data appearing at DI and no data will be output on DO. RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for EEPROM programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT Data is output serially by the CAT514, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 514s to share a single serial data line and simplifies interfacing multiple 514s to a microprocessor. WRITING TO MEMORY Programming the CAT514’s EEPROM memory is acFigure 1. Writing to Memory to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 complished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DAC address and eight data bits are clocked into the DAC control register via the DI pin. Data enters on the clock’s rising edge. The DAC output changes to its new setting on the clock cycle following D7, the last data bit. Programming is achieved by bringing PROG high for a minimum of 3 ms. PROG must be brought high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DAC control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the EEPROM cells. The CAT514’s EEPROM memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. READING DATA Each time data is transferred into a DAC control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DAC’s output. This feature allows µPs to poll DACs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in EEPROM so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the EEPROM’s setting is reloaded into the DAC control register. Since Figure 2. Reading from Memory to 1 2 3 4 5 6 7 8 9 10 11 12 CS NEW DAC DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 CS CURRENT DAC DATA DO D0 D1 D2 D3 D4 D5 D6 D7 DI 1 A0 A1 CURRENT DAC DATA DO PROG D0 D1 D2 D3 D4 D5 D6 D7 PROG RDY/BSY DAC OUTPUT CURRENT DAC VALUE NON-VOLATILE NEW DAC VALUE VOLATILE NEW DAC VALUE NON-VOLATILE DAC OUTPUT CURRENT DAC VALUE NON-VOLATILE Doc. No. 25075-00 2/98 M-1 6 CAT514 this value is the same as that which had been there previously no change in the DAC’s output is noticed. Had the value held in the control register been different from that stored in EEPROM then a change would occur at the read cycle’s conclusion. TEMPORARILY CHANGE OUTPUT The CAT514 allows temporary changes in DAC’s output to be made without disturbing the settings retained in EEPROM memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. Figure 3 shows the control and data signals needed to effect a temporary output change. DAC settings may be changed as many times as required and can be made to any of the four DACs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DACs will return to the output values stored in EEPROM memory. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DAC control register prior to programming. This is because the CAT514’s internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no PROG signal is received. Figure 3. Temporary Change in Output to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DAC DATA 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI CURRENT DAC DATA DO D0 D1 D2 D3 D4 D5 D6 D7 PROG CURRENT DAC VALUE NON-VOLATILE DAC OUTPUT NEW DAC VALUE VOLATILE CURRENT DAC VALUE NON-VOLATILE APPLICATION CIRCUITS +5V +5V Ri +15V RF +15V VDD CONTROL & DATA VREF H – + -15V VOUT VDD CONTROL & DATA VREF H – + -15V VOUT CAT514 OPT 504 GND VREF L OP 07 CAT514 OPT 504 GND VREF L OP 07 VOUT = VDAC RF VOUT = (1 + –––) V DAC RI Buffered DAC Output Amplified DAC Output DAC INPUT +5V Vi Ri +15V VDD CONTROL & DATA VREF H RF DAC OUTPUT CODE VDAC = ——— (VFS - VZERO ) + VZERO 255 VFS = 0.99 VREF VZERO = 0.01 VREF 255 —— (.98 VREF ) + .01 VREF = .990 V REF 255 128 —— (.98 V ) + .01 V = .502 V REF REF REF 255 127 (.98 V —— ) + .01 V = .498 V 255 REF REF REF 1 —— (.98 V ) + .01 V = .014 V 255 REF REF REF —0 (.98 V — ) + .01 V = .010 V REF REF REF 255 ANALOG OUTPUT MSB LSB 1111 VREF = 5V R I = RF V OUT = +4.90V V = +0.02V OUT V = -0.02V OUT V = -4.86V OUT V = -4.90V OUT – + -15V VOUT OP 07 1111 CAT514 OPT 504 GND VREF L 1000 0111 0000 0000 1111 0001 VOUT = VDAC ( R i+ RF) -Vi R F Ri For R i = RF VOUT = 2VDAC -Vi 0000 0000 Bipolar DAC Output 7 Doc. No. 25075-00 2/98 M-1 CAT514 APPLICATION CIRCUITS (Cont.) VREF RC = ————— 256 * 1 µA +5V VREF VREFH Fine adjust gives ± 1 LSB change in V OFFSET VREF when VOFFSET = ——— 2 +5V +VREF VREFH VDD VDD FINE ADJUST DAC 127RC + (+VREF ) - (VOFFSET ) RC = ——————————— 1 µA (-VREF ) + (VOFFSET+ ) Ro = ——————————— 1 µA FINE ADJUST DAC 127RC +V COARSE ADJUST DAC RC V OFFSET COARSE ADJUST DAC RC + – GND VREF L Ro -VREF VOFFSET +V + – -V GND VREF L Coarse-Fine Offset Control by Averaging DAC Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DAC Outputs for Dual Power Supply Systems 28 - 32V V+ I > 2 mA 15K 10 µF VDD CONTROL & DATA VREF H VREF = 5.000V VDD 1N5231B VREF H 5.1V 10K CAT514 OPT 504 GND VREF L LT 1029 CONTROL & DATA CAT514 OPT 504 GND VREF L + – LM 324 MPT3055EL OUTPUT 4.02 K 1.00K 10 µF 35V 0 - 25V @ 1A Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference Doc. No. 25075-00 2/98 M-1 8 CAT514 APPLICATION CIRCUITS (Cont.) +5V VREF VIN 1.0 µF + – VDD VREF H LM 339 10K +5V WINDOW 1 VREF WINDOW 1 OPT 504 CAT514 VPP + – + – +5V + 10K WINDOW 2 DAC 1 VOUT 1 WINDOW 2 VOUT 2 CS – DI DAC 2 + – +5V + 10K WINDOW 3 WINDOW 3 DO – PROG DAC 3 + – +5V + 10K WINDOW 4 VOUT 3 WINDOW 4 VOUT 4 WINDOW 5 GND WINDOW 5 CLK – DAC 4 + – +5V + 10K GND VREF L WINDOW STRUCTURE – Staircase Window Comparator +5V VREF VIN 1.0 µF + – VDD VREF H LM 339 10K +5V WINDOW 1 VREF WINDOW 1 CAT514 OPT 514 + – + – +5V + 10K WINDOW 2 DAC 1 VOUT 1 WINDOW 2 VOUT 2 CS – DI DAC 2 + – +5V + 10K WINDOW 3 WINDOW 3 DO – PROG DAC 3 + – +5V + 10K WINDOW 4 VOUT 3 WINDOW 4 VOUT 4 WINDOW 5 GND WINDOW 5 CLK – DAC 4 + – +5V + 10K GND VREF L WINDOW STRUCTURE – Overlapping Window Comparator 9 Doc. No. 25075-00 2/98 M-1 CAT514 APPLICATION CIRCUITS (Cont.) +5V 2.2K VDD VREF 4.7 µA LM385-2.5 +15V ISINK = 2 - 255 mA DAC +5V 10K + – 10K 2N7000 39Ω1W 39Ω 1W 1 mA steps CONTROL & DATA OPT 504 CAT514 DAC + 2N7000 – 5 µA steps GND VREF L 5 meg 5 meg 3.9K 10K 10K – + TIP 30 -15V Current Sink with 4 Decades of Resolution +15V 51K + TIP 29 – 10K +5V 10K VDD VREF H 5 meg 5 meg DAC 39Ω 1W 39Ω 1W CONTROL & DATA – OPT 504 CAT514 5 meg + 5 meg BS170P 1 mA steps DAC 3.9K GND VREF L – BS170P + LM385-2.5 5 µA steps -15V ISOURCE = 2 - 255 mA Current Source with 4 Decades of Resolution Doc. No. 25075-00 2/98 M-1 10 CAT514 ORDERING INFORMATION Prefix CAT Device # 514 Suffix J I -TE13 Optional Company ID Product Number Package P: PDIP J: SOIC Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) Tape & Reel TE13: 2000/Reel Notes: (1) The device used in the above example is a CAT514JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) 11 Doc. No. 25075-00 2/98 M-1