CAT525

CAT525 Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications H GEN FR ALO EE LE A D F R E ETM FEATURES s Four 8-bit DPPs configured as programmable s Single supply operation: 2.7V - 5.5V s Setting read-back without effecting outputs voltage sources in DAC-like applications s Independent reference inputs s Buffered wiper outputs s Non-volatile NVRAM memory wiper storage s Output voltage range includes both supply rails s 4 independently addressable buffered APPLICATIONS s Automated product calibration s Remote control adjustment of equipment s Offset, gain and zero adjustments in output wipers s 1 LSB accuracy, high resolution s Serial Microwire-like interface self-calibrating and adaptive control systems s Tamper-proof calibrations s DAC (with memory) substitute DESCRIPTION The CAT525 is a quad 8-bit digitally programmable potentiometer (DPP™) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines and systems capable of self calibration, it is also well suited for applications were equipment requiring periodic adjustment is either difficult to access or located in a hazardous environment. The CAT525 offers four independently programmable DPPs each having its own reference inputs and each capable of rail to rail output swing. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to FUNCTIONAL DIAGRAM V REF H1 V REF H3 V REF H4 19 test new output values without effecting the stored settings and stored settings can be read back without disturbing the DPP’s output. Control of the CAT525 is accomplished with a simple 3wire, Microwire-like serial interface. A Chip Select pin allows several CAT525's to share a common serial interface and communications back to the host controller is via a single serial data line thanks to the CAT525’s TriStated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of non-volatile NVRAM Memory Erase/ Write cycle. The CAT525 is available in the 0°C to 70°C commercial and -40°C to 85°C industrial operating temperature ranges and offered in 20-pin plastic DIP and surface mount packages. PIN CONFIGURATION DIP Package (P, L) SOIC Package (J, W) VREFH2 VREF H1 VDD CLK RDY/BSY CS DI DO PROG GND 1 2 3 4 5 20 19 18 17 16 VREF H3 VREF H4 VOUT1 VOUT2 VOUT3 VOUT4 VREFL4 VREFL3 VREFL2 VREF L1 V REF H2 2 1 20 RDY/BSY 5 + PROG 9 PROGRAM CONTROL – 18 V OUT1 VREFH2 VREF H1 1 2 3 4 5 6 20 19 18 17 16 VREF H3 VREF H4 VOUT1 VOUT2 VOUT3 VOUT4 VREFL4 VREFL3 VREFL2 VREF L1 CLK 4 DATA CONTROLLER WIPER CONTROL REGISTERS AND NVRAM + – 17 V OUT2 VDD CLK + – 16 CS 6 V OUT3 RDY/BSY CS DI 7 + – 15 V OUT4 DI DO 15 CAT525 7 14 8 9 10 13 12 11 15 6 CAT525 7 14 8 9 10 13 12 11 24kΩ (ea) H.V. CHARGE PUMP SERIAL DATA OUTPUT REGISTER 8 DO PROG GND CAT525 11 12 13 14 VREFL4 VREFL2 V REFL1 VREFL3 © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 2001, Rev. E CAT525 ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND ...................................... -0.5V to +7V Inputs CLK to GND ............................ -0.5V to VDD +0.5V CS to GND .............................. -0.5V to VDD +0.5V DI to GND ............................... -0.5V to VDD +0.5V RDY/BSY to GND ................... -0.5V to VDD +0.5V PROG to GND ........................ -0.5V to VDD +0.5V VREFH to GND ........................ -0.5V to VDD +0.5V VREFL to GND ......................... -0.5V to VDD +0.5V Outputs D0 to GND ............................... -0.5V to VDD +0.5V VOUT 1– 4 to GND ................... -0.5V to VDD +0.5V RELIABILITY CHARACTERISTICS Symbol VZAP(1) ILTH(1)(2) Operating Ambient Temperature Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C Industrial (‘I’ suffix) ........................ -40°C to +85°C Junction Temperature ..................................... +150°C Storage Temperature ........................ -65°C to +150°C Lead Soldering (10 sec max) .......................... +300°C * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. Parameter ESD Susceptibility Latch-Up Min 2000 100 Max Units Volts mA Test Method MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. POWER SUPPLY Symbol Parameter IDD1 IDD2 Supply Current (Read) Supply Current (Write) Conditions Normal Operating Programming, VDD = 5V VDD = 3V VDD Operating Voltage Range Min — — — 2.7 Typ 400 1600 1000 — Max 600 2500 1600 5.5 Units µA µA µA V LOGIC INPUTS Symbol IIH IIL VIH VIL Parameter Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage Conditions VIN = VDD VIN = 0V Min — — 2 0 Typ — — — — Max 10 -10 VDD 0.8 Units µA µA V V LOGIC OUTPUTS Symbol Parameter VOH VIL High Level Output Voltage Low Level Output Voltage Conditions IOH = -40µA IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V Min VDD -0.3 — — Typ — — — Max — 0.4 0.4 Units V V V Doc. No. 2001, Rev. E 2 CAT525 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Potentiometer Resistance RPOT to RPOT Match Pot Resistance Tolerance Voltage on VREFH pin Voltage on VREFL pin Resolution INL DNL ROUT IOUT TCRPOT CH/CL Integral Linearity Error Differential Linearity Error Buffer Output Resistance Buffer Output Current TC of Pot Resistance Potentiometer Capacitances 300 8/8 2.7 0V 0.4 0.5 0.25 1 0.5 10 3 — Conditions Min Typ 24 +0.5 +1 +20 VDD VDD - 2.7 Max Units kΩ % % V V % LSB LSB Ω mA ppm/˚C pF AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency DPP Settling Time to 1 LSB 150 100 0 50 50 — — — — — 150 700 500 300 DC — — — — — — — — — 400 400 4 — — — — — 3 6 — — — — — 150 150 — — 5 — — — — 1 10 10 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz µs µs Parameter Conditions Min Typ Max Units CL=100pF, see note 1 Analog tDS CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2001, Rev. E CAT525 TIMING MIN/MAX FROM TO A. C. TIMING DIAGRAM Doc. No. 2001, Rev. E to 1 2 3 4 5 PARAM NAME t CLK H t CLK H Rising CLK edge to falling CLK edge Min CLK t CLK L Falling CLK edge to CLK rising edge t CSH t CLK L t CSS t CSH Falling CLK edge for last data bit (DI) to falling CS edge Rising CS edge to next rising CLK edge Min Min t CSS Min CS t CSMIN t CSMIN Falling CS edge to rising CS edge t DIS Data valid to first rising CLK edge after CS = high Min Min t DIS DI t DIH t DIH t DO0 t LZ t DO0 Rising CLK edge to end of data valid Min 4 Rising CLK edge to D0 = low Rising CS edge to D0 becoming high low impedance (active output) Max (Max) t HZ t DO1 t DO1 t HZ Rising CLK edge to D0 = high Falling CS edge to D0 becoming high impedance (Tri-State) t PS t PS t PROG Max (Max) Rising PROG edge to next rising CLK edge t PROG Rising PROG edge to falling PROG edge t BUSY Falling CLK edge after PROG=H to rising RDY/BSY edge t BUSY Min Min Max 1 2 3 4 5 t LZ DO PROG RDY/BSY to CAT525 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CDPP/DPP addressing is as follows: Function Maximum DPP 2 output voltage Maximum DPP 1 output voltage Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin Non-volatile Memory Programming Enable Input Power supply ground Minimum DPP 1 output voltage Minimum DPP 2 output voltage Minimum DPP 3 output voltage Minimum DPP 4 output voltage DPP 4 output DPP 3 output DPP 2 output DPP 1 output Maximum DPP 4 output voltage Maximum DPP 3 output voltage Name VREFH2 VREFH1 VDD CLK RDY/BSY CS DI DO PROG GND VREFL1 VREFL2 VREFL3 VREFL4 VOUT4 VOUT3 VOUT2 VOUT1 VREFH4 VREFH3 DPP OUTPUT VOUT1 VOUT2 VOUT3 VOUT4 A0 0 1 0 1 A1 0 0 1 1 DEVICE OPERATION The CAT525 is a quad 8-bit configured digitally programmable potentiometer (DPP/CDPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each confitured DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT525 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high 5 impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT525’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP wiper control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT525’s clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. No clock is necessary upon system power-up. The CAT525’s internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. Doc. No. 2001, Rev. E CAT525 As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. VREF VREF, the voltage applied between pins VREFH &VREFL, sets the configured DPP’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH &VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the References section of DC Electrical Characteristics. READY/BUSY When saving data to non-volatile memory, the Ready/ Busy ouput (RDY/BSY) signals the start and duration of the erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT525 will ignore any data appearing at DI and no data will be output on DO. RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for EEPROM programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT Data is output serially by the CAT525, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 525s to share a Figure 1. Writing to Memory to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 single serial data line and simplifies interfacing multiple 525s to a microprocessor. WRITING TO MEMORY Programming the CAT525’s non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP wiper control register via the DI pin. Data enters on the clock’s rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. The CAT525’s non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. READING DATA Each time data is transferred into a DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP’s output. This feature allows µPs to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. Since this value is the Figure 2. Reading from Memory to 1 2 3 4 5 6 7 8 9 10 11 12 CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 CS DI 1 A0 A1 CURRENT DPP DATA CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 D7 DO D0 D1 D2 D3 D4 D5 D6 D7 PROG PROG RDY/BSY RDY/BSY DPP OUTPUT CURRENT DPP VALUE NON-VOLATILE NEW DPP VALUE VOLATILE NEW DPP VALUE NON-VOLATILE DPP OUTPUT CURRENT DPP VALUE NON-VOLATILE Doc. No. 2001, Rev. E 6 CAT525 same as that which had been there previously no change in the DPP’s output is noticed. Had the value held in the control register been different from that stored in nonvolatile memory then a change would occur at the read cycle’s conclusion. TEMPORARILY CHANGE OUTPUT The CAT525 allows temporary changes in DPP’s output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. Figure 3 shows the control and data signals needed to effect a temporary output change. DPP settings may be changed as many times as required and can be made to any of the four DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DPPs will return to the output values stored in non-volatile memory. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP control register prior to programming. This is because the CAT525’s internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. APPLICATION CIRCUITS +5V Vi RI +15V VDD CONTROL & DATA VREFH VDPP RF Figure 3. Temporary Change in Output to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 D7 PROG RDY/BSY DPP OUTPUT CURRENT DPP VALUE NON-VOLATILE NEW DPP VALUE VOLATILE CURRENT DPP VALUE NON-VOLATILE DPP INPUT DPP OUTPUT CODE VDPP = ——— (VFS - VZERO ) + VZERO 255 VFS = 0.99 VREF ANALOG OUTPUT – + -15V V OUT MSB 1111 LSB 1111 VZERO = 0.01 VREF 255 —— (.98 VREF ) + .01 V = .990 V REF REF 255 128 —— (.98 V ) + .01 V = .502 V REF REF REF 255 127 (.98 V —— ) + .01 V = .498 V 255 REF REF REF 1 —— (.98 V ) + .01 V = .014 V 255 REF REF REF —0 (.98 V — ) + .01 VREF = .010 V REF REF 255 VREF = 5V R I = RF V OUT = +4.90V V = +0.02V OUT V = -0.02V OUT V = -4.86V OUT V = -4.90V OUT CAT525 GND VREFL OP 07 1000 0111 0000 0000 1111 0001 VOUT = VDPP ( RI+ RF) -VI R F RI For R I = RF VOUT = 2VDPP -VI 0000 0000 Bipolar DPP Output +5V RI +15V VDD CONTROL & DATA VREFH RF – + OP 07 VOUT CAT525 GND VREFL -15V RF VOUT = (1 + –––) V DPP RI A lifi d DAC O Amplified DPP Output 7 Doc. No. 2001, Rev. E CAT525 APPLICATION CIRCUITS (Cont.) +5V +VREF VREFH VREF RC = ————— 256 * 1 µA +5V VREF VREFH Fine adjust gives ± 1 LSB change in V OFFSET VREF when VOFFSET = ——— 2 127RC VDD FINE ADJUST DPP 127RC (+VREF ) - (VOFFSET+ ) RC = ——————————— 1 µA (-VREF ) + (VOFFSET+ ) Ro = ——————————— 1 µA VDD FINE ADJUST DPP COARSE ADJUST DPP RC +V COARSE ADJUST DPP RC VOFFSET GND VREFL Ro -VREF VOFFSET +V + – + – -V GND VREFL Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems 28 - 32V V+ I > 2 mA 15K 10 µF VDD CONTROL & DATA VREFH VREF = 5.000V VDD 1N5231B VREFH 5.1V 10K CAT525 GND VREFL LT 1029 CONTROL & DATA CAT525 CAT525 GND VREFL + – LM 324 MPT3055EL OUTPUT 4.02 K 1.00K 10 µF 35V 0 - 25V @ 1A Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference Doc. No. 2001, Rev. E 8 CAT525 APPLICATION CIRCUITS (Cont.) +5V VREF VIN 1.0 µF + – VDD VREFH LM 339 10K +5V WINDOW 1 VREF WINDOW 1 CAT525 VPP + – + – +5V + 10K WINDOW 2 DPP 1 VOUT 1 WINDOW 2 VOUT 2 CS – DI DPP 2 + – +5V + 10K WINDOW 3 WINDOW 3 DO – PROG DPP 3 + – +5V + 10K WINDOW 4 VOUT 3 WINDOW 4 VOUT 4 WINDOW 5 GND WINDOW 5 CLK – DPP 4 + – +5V + 10K GND VREFL WINDOW STRUCTURE – Staircase Window Comparator +5V VREF VIN 1.0 µF VDD VREFH + – +5V + – LM 339 10K WINDOW 1 CAT525 VPP DPP 1 VREF H CS WINDOW 1 DI DPP 2 + – +5V + 10K WINDOW 2 VOUT 1 V 2 OUT WINDOW 2 V 4 OUT DO – PROG DPP 3 VOUT 3 WINDOW 3 CLK GND DPP 4 + – +5V + 10K WINDOW 3 WINDOW STRUCTURE GND VREFL – Overlapping Window Comparator 9 Doc. No. 2001, Rev. E CAT525 APPLICATION CIRCUITS (Cont.) +5V 2.2K VDD VREF 4.7 µA LM385-2.5 +15V ISINK = 2 - 255 mA DPP1 +5V 10K + – 10K 2N7000 39 Ω 1W 39 Ω 1W 1 mA steps CONTROL & DATA CAT525 DPP2 + 2N7000 – 5 µA steps GND VREFL 5M 5M 3.9K 10K 10K – + TIP 30 -15V Current Sink with 4 Decades of Resolution +15V 51K + TIP 29 – 10K +5V 10K VDD VREFH 5M 5M 39 Ω 1W 39 Ω 1W DPP1 CONTROL & DATA CAT525 CAT525 5M – + 5M BS170P 1 mA steps DPP2 3.9K GND VREFL – BS170P + LM385-2.5 5 µA steps -15V ISOURCE = 2 - 255 mA Current Source with 4 Decades of Resolution Doc. No. 2001, Rev. E 10 CAT525 ORDERING INFORMATION Prefix CAT Device # 525 Suffix J I -TE13 Optional Company ID Product Number Package P: PDIP J: SOIC L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Tape & Reel TE13: 2000/Reel Temperature Range Blank = Commercial (0°C to 70°C) I = Industrial (-40°C to 85°C) Notes: (1) The device used in the above example is a CAT525JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) 11 Doc. No. 2001, Rev. E REVISION HISTORY Date 3/16/2004 7/12/2004 Rev. D E Reason Updated Potentiometer Characteristics Updated Functional Diagram Updated Potentiometer Characteristics Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue Date: Type: 2001 E 7/12/04 Final