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CEM8311

CEM8311

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CEM8311 - Dual P-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CEM8311 数据手册
CEM8311 Dual P-Channel Enhancement Mode Field Effect Transistor FEATURES -30V, -7.9A, RDS(ON) = 20mΩ @VGS = -10V. RDS(ON) = 33mΩ @VGS = -4.5V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. Surface mount Package. D1 8 D1 7 D2 6 D2 5 5 SO-8 1 1 S1 2 G1 3 S2 4 G2 ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a TA = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg -30 Units V V A A W C ±20 -7.9 -31.6 2.0 -55 to 150 Maximum Power Dissipation Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Ambient b Symbol RθJA Limit 62.5 Units C/W Specification and data are subject to change without notice . 5 - 147 Rev 1. 2006.January http://www.cetsemi.com CEM8311 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics c Gate Threshold Voltage Static Drain-Source On-Resistance Dynamic Characteristics d Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics d Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current b Drain-Source Diode Forward Voltage c td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = -2.1A VDS = -15V, ID = -7A, VGS = -4.5V VDD = -10V, ID = -1A, VGS = -10V, RGEN = 6Ω 16 7 105 40 16.4 5.8 6.5 -2.1 -1.2 30 15 200 80 22 ns ns ns ns nC nC nC A V gFS Ciss Coss Crss VDS = -10V, ID = -7A VDS = -15V, VGS = 0V, f = 1.0 MHz 15 2020 395 202 S pF pF pF VGS(th) RDS(on) VGS = VDS, ID = -250µA VGS = -10V, ID = -7A VGS = -4.5V, ID = -5.8A -1 16 25 -3 20 33 V mΩ mΩ BVDSS IDSS IGSSF IGSSR VGS = 0V, ID = -250µA VDS = -24V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V -30 -1 100 -100 V µA TA = 25 C unless otherwise noted Symbol Test Condition Min Typ Max Units nA nA Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing. 5 - 148 CEM8311 25 -VGS=10,8,7,6,5V 20 50 -ID, Drain Current (A) -ID, Drain Current (A) 40 15 -VGS=4V 10 30 20 25 C 10 TJ=125 C -55 C 3 4 5 6 5 -VGS=3V 0 0.0 0 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 -VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 3600 3000 Ciss 2400 1800 1200 Coss 600 Crss 0 0 5 10 15 20 25 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 -VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=-7A VGS=-10V C, Capacitance (pF) -50 0 50 100 150 200 -VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature -IS, Source-drain current (A) VGS=0V 1 VTH, Normalized Gate-Source Threshold Voltage VDS=VGS ID=-250µA 10 10 0 10 -25 0 25 50 75 100 125 150 -1 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature -VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 5 - 149 CEM8311 -VGS, Gate to Source Voltage (V) 5 VDS=-15V ID=-7A 10 2 RDS(ON)Limit 4 -ID, Drain Current (A) 1ms 10 1 10ms 100ms 1s DC 3 10 0 5 2 1 10 -1 0 0 3 6 9 12 15 18 10 -2 TA=25 C TJ=150 C Single Pulse 10 -2 10 -1 10 0 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge -VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area VDD t on V IN D VGS RGEN G 90% toff tr 90% RL VOUT td(on) VOUT td(off) 90% 10% tf 10% INVERTED S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 PDM t1 t2 1. RθJA (t)=r (t) * RθJA 2. RθJA=See Datasheet 3. TJM-TA = P* RθJA (t) 4. Duty Cycle, D=t1/t2 10 -2 Single Pulse -4 10 10 -3 10 -2 10 -1 10 0 10 1 10 2 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 5 - 150
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