CS212

CS212 CS212 Security Detector Serial-Addressable Receiver/Transmitter Description The S-ART is a 16 pin circuit designed for data transmission on a two-lead cable. The circuit is specially developed for alarm systems where it is desired to identify each detector individually. There can be up to 30 S-ART circuits/detectors on the same 2-lead cable. This cable transmits both DC supply to the S-ART and information to/from the S-ART. The S-ART works on the principle by which an address is sent on the line cable and the S-ART which recognizes the address then carries out the order which can, in principle, be two things: 1. Transmit data from the line cable to the S-ART's two outputs OUT0 and OUT1. 2. Answer the S-ART controller with the condition of the 2 inputs IN0 and IN1 or IN2-3. The line signal is divided into 3 levels in order to give a time signal for synchronizing and a data signal containing addresses, orders etc. Typical signal levels for the three levels would be 15V, 7.5V and 0V. Features s Receives/Transmits Data on Only Two Leads s Low Current Consumption s High Noise Immunity s Sabotage Surveilled Loop Input Block Diagram Package Options 16L PDIP & 16L SO Wide A method by which, in principle, the system can be extended to an infinite number of S-ART is shown on the block diagram. The controller scans the in/outputs of a number of lines, each with a maximum of 30 S-ARTs. Line 1 S-ART OUT0 1 Controller Line N 16 15 14 13 12 11 10 9 OUT1 DSR IN2 IN3 VDD DATAOUT Gnd LINE A4 2 A3 3 A2 4 A1 5 A0 6 IN1 7 IN0 8 V CK "1" DATA "1" DATA "0" Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com Rev. 4/21/99 1 A ¨ Company CS212 Absolute Maximum Ratings Lead Temperature Soldering: Wave Solder (through hole styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Sec. max 260ûC Peak Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Sec max. above 183ûC, 230ûC Peak Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to 150ûC Maximum Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125¡C Electrical Characteristics: TA = 25¡C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Operating Temperature Range, TA Device Current IDD Not Addressed Device Current IDD Power-Up-Mode (5 corr. addr. bits)CP4-CP5 Device Current IDD Addressed, Line Output Transistor Active Device Current IDD Addressed (4 corr.addr.bits) Line Output Transistor Not Active Output Voltage Low Level Out0, Out1, DSR Output sink Current Out0, Out1, DSR Output Voltage High Level Out0, Out1, DSR Leakage Current Out0, Out1, DSR Input Voltage Level Low A0-A4, IN0, IN1 High Input Current IN0, IN1=Gnd Power-Up Mode (4 corr.addr.bits) Input Current A0-A4, IN0, IN1 Not Addressed Positive Trigger Threshold VP, C Voltage Vdd=15V VP, D Negative Trigger VNC Threshold Voltage VNC Hysteresis Voltage Clock/Data Comp. Saturation Voltage For Line Output Driver Saturation Voltage For Line Output Driver Leakage Current For the Line Output Line Signal Freq. Rise/Fall-Time Line Signal -40 Outputs unloaded Line Voltage=0-15V, VDD=15V IN0, IN1 are Open IN2, IN3 are Active VDD=15V IN2, IN3 not Active IN0, IN1 are Open VDD=15V IN2, IN3 not Active IN0, IN1 are Open VDD=15V VDD=10-15V ISINK=1mA 1.0 0.47 3.55 85 0.80 5.50 ¡C mA mA 6.24 9.64 mA 1.84 2.86 mA 1.2 V mA 14 VOUT=14V 30 V µA VDD=10-15V VDD=10-15V VDD=18V 30%VDD 70%VDD 150 850 V V µA VDD=18V 20 µA Clock Comparator Data Comparator VDD=15V Clock Comparator VDD=15V, Data Comparator VDD=15V VDD=15V, IC=50mA VDD=15V, IC=10mA VLINE=0-18V, VDD=18V VDD=15V±1V 11.0 4.6 10.2 3.4 0.7 11.7 5.7 10.9 4.3 0.8 12.4 6.6 11.6 5.2 V V V V V V V µA kHz µs 1 0.4 ±16 0 0.25 20 250.00 2 CS212 Electrical Characteristics: TA = 25¡C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Turn-On Time For Line Output Driver Turn-Off Time For Line Output Driver Line Voltage VL (Note 1) Loop Current IN2, IN3 Alarm Condition IN2-IN3 Loop Open Alarm Condition IN2-IN3 Loop Shorted 1.0 1.0 0 0.1 1 5 28 0.5 5 30 µs µs V mA k½ k½ Note 1: The circuit shall function in the correct way only between 0 and 18VDC. Data driver must not turn on when line voltage is above 18V. Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION 1 2 3 4 5 6 7 8 9 10 11 OUT0 A4 A3 A2 A1 A0 IN1 IN0 LINE Gnd DATAOUT Output (open collector) from S-ART. Address input. Must be connected to VDD or Gnd according to the relevant address code. Address input. Must be connected to VDD or Gnd according to the relevant address code. Address input. Must be connected to VDD or Gnd according to the relevant address code. Address input. Must be connected to VDD or Gnd according to the relevant address code. Address input. Must be connected to VDD or Gnd according to the relevant address code. Input to S-ART. Input to S-ART. Signal lead in the line cable. Zero lead in the line cable. Output from the S-ART, which is active in the READ-mode. Transmits data from S-ART to line. Supply voltage to the S-ART. The voltage is derived from the line signal. Sabotage surveilled loop (shorting and breaking). Sabotage surveilled loop (shorting and breaking). Data Set Ready. Output (open collector) from the S-ART which is active during WRITE-mode, when OUT0 and OUT1 change. Output (open collector) from S-ART. 12 13 14 15 16 VDD IN3 IN2 DSR OUT1 3 CS212 Serial-Addressable Receiver Transmitter S-ART ADDRESS CODING The circuit is coded on address inputs A0-A4. In order to reduce the power consumption to the circuits they are in power down mode for most of the time. Only when a circuit is addressed is the amount to that particular circuit increased. READ When a S-ART has recognized an address with the correct parity and then received a READ-order the controller becomes passive. The S-ART in question will then send data bits to the controller. These bits are the condition on the IN0 and IN1 or IN2-3 and a parity bit derived from them. The current in inputs IN0 and IN1 only flows when the S-ART is addressed. If the sabotage surveilled loop IN2-3 is used IN1 should be open. IN2-3 is then read instead of IN1. The loop IN2-3 is checked for both shorting and breaking. WRITE When a S-ART has recognized an address with correct parity and a write order, the S-ART in question transmits data to the outputs OUT0 and OUT1. This data transmission takes place after a check of the parity bit. If the parity bit is wrong, data transmission to OUT0 and OUT1 is blocked and new data transmission can only take place after a read order which resets the parity fault. The DSR signal can be used to strobe OUT0 and OUT1 further on in the following logic. DATA FORMAT The signals are sent out on the line in words organized as shown in the figure. The S-ART information consists of two parity bits: an address parity bit and a data parity bit. Both the address and data are checked for even parity. The address parity bit must always be generated by the controller. The data parity bit during the READ-mode is generated by the S-ART. During the WRITE-mode the data parity bit is generated by the controller. Typical S-ART Applications Addresses ADD. Parity Command Data Data Parity 1) Alarm Detector Transmission Line Line from Controller Address Coding IN0 Gnd Gnd S-ART IN0 Tamper Contact Detector Alarm Contact IN1 R1 Line Data Out VDD + IN1 2) Window Foil Line from Controller Foil IN2 S-ART Terminal Lead IN3 R2 C + IN2 End of Loop Circuit Address Coding Address Code IN3 Gnd A0 A4 Short Cables OUT0 OUT1 DSR + The foil is checked both for shorts and breakage. 3) Alarm Indicator/Data Transmission Line from Controller S-ART Bells Lamps etc. Logic Circuit + Indicates IN1 and Loop IN2, IN3 cannot be used at the same time. Address Coding Functional Description GENERAL The CS212 is a peripheral addressable circuit which is used as a communication link between Detectors/Sensors and a Central Control Unit. The communication between the CS212 and a control unit takes place via a simple 2-wire cable which also provides power to the IC. On each 2-wire cable, a maximum of 30 CS212's can be controlled or interrogated with the address binary 0-29. This permits surveillance of up to 30 window protections, door contacts, movement detectors, etc. within the same 2-wire group. Each CS212 can monitor the status of two external surveillance devices and communicate the status back to the control unit. Two outputs are also available for controlling bells, lights, LED's, door locks, etc. These outputs are controlled from the control unit via the 2-wire cable. WIRE TRANSMISSION CABLE (The Line) The 2-wire bidirectional transmission cable called "The Line" provides power and data to the CS212 and also provides data back to the control circuit. The line signal is rectified and filtered at each CS212 and is used for the power supply to the chip. The CS212 also decodes the line signal into clock and data signals used inside the IC. 4 CS212 CS Functional Description READ WORD Control Circuit 2121 2122 2123 21229 2 Wire Transmission Line Tranmission Line VCC(