CS51221ED16

CS51221 CS51221 Enhanced Voltage Mode PWM Controller Description The CS51221 fixed frequency feed forward voltage mode PWM controller contains all of the features necessary for basic voltage mode operation. This PWM controller has been optimized for high frequency primary side control operation. In addition, this device includes such features as: Soft Start, accurate duty cycle limit control, less than 50µA startup current, over and under voltage protection, and bidirectional synchronization. The CS51221 is available in 16 lead PDIP and SO narrow surface mount packages. s s Features 1MHz Frequency Capability Fixed Frequency Voltage Mode Operation, with Feed Forward Thermal Shutdown Under Voltage Lock-out Accurate Programmable Max Duty Cycle Limit 1A Sink/Source Gate Drive Programmable Pulse by Pulse Over Current Protection Leading Edge Current Sense Blanking 75ns Shutdown Propagation Delay Programmable Soft Start Under Voltage Protection Over Voltage Protection with Programmable Hysteresis Bidirectional Synchronization 25ns GATE Rise and Fall Time (1nF load) 3.3V 3% Reference Voltage Output s s s s s s s Application Diagram 36V-72V to 5V/5A converter s s s s s BAS21 VIN (36V to 72V) 51k FZT688 11V 10 100 1µF 22µF 18V 160k T3 100:1 0.1µF 24.3k VC VREF VCC UV OV ISET FF GATE ISENSE U1 s T2 2:5 VOUT (5V/5A) 100µF SGnd 510k 10k T1 4:1 MBRB2545CT 10 CS51221/2 0.22µF 10k 1µF SYNC 330pF 0.01µF 200 2200pF 4.3k D11 BAS21 100pF COMP VFB RT/CT SYNC SS LGnd 680pF D13 V33MLA1206A23 20.25k 13k 10 IRF634 Package Options 16 Lead SO Narrow & PDIP GATE ISENSE 1 PGnd 470pF 62 10 VC PGnd VCC VREF LGnd SS COMP VFB 0.1µF 5.1k SYNC 2k 5.6k 180 1k TL431 2k 150 4700pF MOC81025 FF UV OV RTCT ISET 1k Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com Rev. 3/26/99 1 A ® Company CS51221 Absolute Maximum Ratings Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited Lead Temperature Soldering: Wave Solder (through hole styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Sec. max 260˚C Peak Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Sec max. above 183˚C, 230˚C Peak Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150˚C ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV PIN SYMBOL PIN NAME VMAX 15V 6V 6V 6V 6V 6V 6V 6V 6V 6V 6V 15V 15V 6V N/A VMIN -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V N/A ISOURCE 1.0A Peak 200mA DC 1mA 1mA 1mA 10mA 1mA 10mA 1mA 1mA 1mA 1mA 10mA 10mA Internally Limited 1.0A Peak 200mA DC N/A ISINK 1.0A Peak 200mA DC 1mA 10mA 25mA 20mA 1mA 10mA 1mA 1mA 1mA 10mA 50mA 1.0A Peak 200mA DC 10mA N/A GATE ISENSE RTCT FF COMP VFB SYNC UV OV ISET SS VCC VC VREF PGnd Gate Drive Output Current Sense Input Timing Resistor/Capacitor Feed Forward Error Amp Output Feedback Voltage Sync Input Under Voltage Over Voltage Current Set Soft Start Logic Section Supply Power Section Supply Reference Voltage Power Ground LGnd Logic Ground N/A N/A N/A 2 Electrical Characteristics: -40˚C < TA < 85˚C; -40˚C < TJ < 125˚C; 3V < VC < 15V; 4.7V < VCC < 15V; Rt=12K, Ct=390pF Unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS51221 s Start/Stop Voltages Start Threshold Stop Threshold Hysteresis ICC @ Startup s Supply Current ICC Operating IC Operating IC Operating s Reference Voltage Total Accuracy Line Regulation Load Regulation Noise Voltage Op Life Shift Fault Voltage VREF(OK) Voltage VREF(OK) Hysteresis Current Limit s Error Amp Reference Voltage VFB Input Current Open Loop Gain Unity Gain Bandwidth COMP Sink Current COMP Source Current COMP High Voltage COMP Low Voltage PSRR SS Clamp, VCOMP COMP Max Clamp VFB = COMP VFB = 1.2V (Note 1) (Note 1) COMP = 1.4V, VFB = 1.45V COMP = 1.4V, VFB = 1.15V VFB = 1.15V VFB = 1.45V Freq = 120Hz (Note 1) SS = 1.4V, VFB = 0V, ISET = 2V Note 1 60 1.5 3 1 2.8 75 60 1.3 1.7 12 1.6 3.1 125 85 1.4 1.8 1.5 1.9 32 2.0 3.4 300 1.234 1.263 1.3 1.285 2 V µA dB MHz mA mA V mV dB V V 0mA < IREF < 2mA 10Hz < F < 10kHz (Note 1) T = 1000Hrs. (Note 1) 2.8 2.9 30 2 0mA < IREF < 2mA 3.2 3.3 6 6 50 4 2.95 3.05 100 40 20 3.1 3.2 150 100 3.4 20 15 V mV mV µV mV V V mV mA 1nF Load on GATE No switching 9.5 12 2 14 18 4 mA mA mA 4.4 3.2 400 4.6 3.8 850 38 4.7 4.1 1400 75 V V mV µA Start - Stop VCC < UVL Start Threshold 3 CS51221 Electrical Characteristics: -40˚C < TA < 85˚C; -40˚C < TJ < 125˚C; 3V < VC < 15V; 4.7V < VCC < 15V; Rt=12K, Ct=390pF Unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT s Oscillator Frequency Accuracy Voltage Stability Temperature Stability Max Frequency Duty Cycle Peak Voltage Valley Clamp Voltage Valley Voltage Discharge Current s Synchronization Input Threshold Output Pulse Width Output High Voltage Input Resistance SYNC to Drive Delay Output Drive Current s GATE Driver High Saturation Voltage Low Saturation Voltage High Voltage Clamp Output Current Output UVL Leakage Rise Time Fall Time Max Gate Voltage during UVL/Sleep s FeedForward (FF) Discharge Voltage Discharge Current FF to GATE Delay IFF = 2mA FF = 1V 2 50 0.3 16 75 0.7 30 125 V mA ns 1 nF load (Note 1) GATE = 0V 1nF load, VC = 20V, 1V < GATE < 9V 1nF load, VC = 20V, 9V < GATE < 1V IGATE = 500µA .4 VC-GATE, VC = 10V, ISOURCE = 200mA GATE-PGnd, ISINK = 200mA 11.0 1.5 1.2 13.5 1 1 60 25 .7 2.0 1.5 16.0 1.25 50 100 50 1.0 V V V A µA ns ns V Time from SYNC to GATE Shutdown RSYNC = 1Ω 100µA Load 0.9 200 2.1 35 100 1.00 1.4 320 2.5 70 140 1.50 1.8 450 2.8 140 180 2.25 V ns V kΩ ns mA (Note 1) (Note 1) (Note 1) -40˚C < TJ < 125˚C (Note 1) 1 80 1.94 0.90 0.85 0.85 85 2.00 0.95 1.00 1.00 90 2.06 1.00 1.15 1.15 260 273 1 8 320 2 kHz % % MHz % V V V mA 4 CS51221 Electrical Characteristics: -40˚C < TA < 85˚C; -40˚C < TJ < 125˚C; 3V < VC < 15V; 4.7V < VCC < 15V; Rt=12K, Ct=390pF Unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT s Overcurrent Protection Overcurrent Threshold ISENSE to GATE Delay s External Voltage Monitors Overvoltage Threshold Overvoltage Hysteresis Current Undervoltage Threshold Undervoltage Hysteresis s Soft Start (SS) Charge Current Discharge Current Charge Voltage Discharge Voltage Soft Start Clamp Offset Soft Start Fault Voltage s Blanking Blanking Time SS Blanking Disable Threshold COMP Blanking Disable Threshold s Thermal Shutdown Thermal Shutdown Thermal Hysteresis (Note 1) (Note 1) 125 5 150 10 180 15 ˚C ˚C VFB < 1 VFB < 1, SS > 3V 50 2.8 2.8 150 3.0 3.0 250 3.3 3.3 ns V V FF = 1.25V OV = 2.15V or LV = 0.85V SS = 2V SS = 2V 40 4 2.8 0.25 1.15 50 5 3.0 0.3 1.25 0.1 70 7 3.4 0.35 1.35 0.2 µA µA V V V V OV increasing OV = 2.15V UV increasing 1.9 10.0 0.95 25 2.0 12.5 1.00 75 2.1 15.0 1.05 125 V µA V mV ISET = 0.5V, Ramp ISENSE 0.475 50 0.500 90 0.525 125 V ns Note 1: Guaranteed by design, not 100% tested in production. 5 CS51221 Package Pin Description Typical Performance Characteristics PACKAGE PIN # PIN SYMBOL FUNCTION 16L PDIP & 16L SO Narrow 1 GATE External power switch driver with 1.0A peak capability. Rail to rail output occurs when the capacitive load is between 470pF and 10nF. Current sense comparator input. Bidirectional synchronization. Locks to highest frequency. PWM ramp. Undervoltage protection monitor. Overvoltage protection monitor. Timing resistor RT and capacitor CT determine oscillator frequency and maximum duty cycle, DMAX. Voltage at this pin sets pulse-by-pulse overcurrent threshold. Feedback voltage input. Connected to the error amplifier inverting input. Error amplifier output. Charging external capacitor restricts error amplifier output voltage during the power up or fault conditions. Logic Ground. 3.3V reference voltage output. Decoupling capacitor can be selected from 0.01µF to 10µF. Logic supply voltage. Output power stage ground. Output power stage supply voltage. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ISENSE SYNC FF UV OV RT/CT ISET VFB COMP SS LGnd VREF VCC PGnd VC Block Diagram VCC 3.3V UVL ENABLE 2mA(maximum load current) VREF VREF = 3.3V 3.1V VREF OK Thermal Shutdown + UV Lockout Start/Stop S Q G1 Low Sat Gate Driver VC GATE 13.5V SYNC RTCT 3.0V OSC 2V to 1V Trip Points G2 R Q Max Duty Cycle (Sat Sense) SS to 1.8V Max PGnd VBG (1.263V) EAMP VREF 50µA VFB COMP Soft Start Clamp PWM Comp LGnd FF FF Discharge ON VO Off G3 Max SS Det G4 OV Monitor Latching Discharge 5µA SS ISET ILIM DISABLE 150ns Blank (Sat Sense) OV 3.0V 2V UV Monitor UV 1V ISENSE 6 Application Information Typical Performance Characteristics Theory of Operation Feed Forward Voltage Mode Control In conventional voltage mode control, the ramp signal has fixed rising and falling slope. The feedback signal is derived solely from the output voltage. Consequently, voltage mode control has inferior line regulation and audio susceptibility. Feed forward voltage mode control derives the ramp signal from the input line, as shown in Fig.1. Therefore, the ramp of the slope varies with the input voltage. At the start of each switch cycle, the capacitor connected to the FF pin is charged through a resistor connected to the input voltage. Meanwhile, the Gate output is turned on to drive an external power switching device. When the FF pin voltage reaches the error amplifier output VCOMP, the PWM comparator turns off the Gate, which in turn opens the external switch. Simultaneously, the FF capacitor is quickly discharged to 0.3V. Overall, the dynamics of the duty cycle are controlled by both input and output voltages. As illustrated in Fig. 2, with a fixed input voltage the output voltage is regulated solely by the error amplifier. For example, an elevated output voltage reduces VCOMP which in turn causes duty cycle to decrease. However, if the input voltage varies, the slope of the ramp signal will react immediately which provides a much improved line transient response. As an example shown in Fig.3, when the input voltage goes up, the rising edge of the ramp signal increases which reduces duty cycle to counteract the change. VIN Power Stage VOUT CS51221 VOUT VCOMP FF VIN RTCT GATE Figure 2: Pulse Width Modulated by Output Current with Constant Input Voltage. VIN VCOMP FF IOUT RTCT GATE Figure 3: Pulse Width modulated by Input Voltage with constant Output Current. GATE R Latch & Driver Feedback Network Powering the IC & UVL The Under Voltage Lockout (UVL) comparator has two voltage references; the start and stop thresholds. During power-up, the UVL comparator disables VREF (which inturn disables the entire IC) until the controller reaches its VCC start threshold. During power-down, the UVL comparator allows the controller to operate until the VCC stop threshold is reached. The CS51221 requires only 50µA during startup. The output stage is held at a low impedance state in lock out mode. During power up and fault conditions, the soft-start clamps the Comp pin voltage and limits the duty cycle. The power up transition tends to generate temporary duty cycles much greater than the steady state value due to the low output voltage. Consequently, excessive current stresses often take place in the system. Soft Start technique alleviates this problem by gradually releasing the clamp on the duty cycle to eliminate the in-rush current. The duration of the Soft Start can be programmed through a capacitance connected to the SS pin. The constant charging current to the SS pin is 50µA (typ). FF COMP PWM Figure 1: Feed Forward Voltage Mode Control. The feed forward feature can also be employed to provide a volt-second clamp, which limits the maximum product of input voltage and turn on time. This clamp is used in circuits, such as Forward and Flyback converter, to prevent the transformer from saturating. Calculations used in the design of the volt-second clamp are presented in the Design Guidelines section. + C Error Amplifier + - FB 7 CS51221 Application Information: continued Typical Performance Characteristics The VREF (ok) comparator monitors the 3.3V VREF output and latches a fault condition if VREF falls below 3.1V. The fault condition may also be triggered when the OV pin voltage rises above 2V or the UV pin voltage falls below 1V. The under-voltage comparator has a built-in hysteresis of 75mV (typ). The hysteresis for the OV comparator is programmable through a resistor connected to the OV pin. When an OV condition is detected, the over-voltage hysteresis current of 12.5µA (typ) is sourced from the pin. In Fig.4, the fault condition is triggered by pulling the UV pin to the ground. Immediately, the SS capacitor is discharged with 5µA of current (typ) and the GATE output is disabled until the SS voltage reaches the discharge voltage of 0.3V (typ). The IC starts the Soft Start transition again if the fault condition has recovered as shown in Fig.4. However, if the fault condition persists, the SS voltage will stay at 0.10V until the removal of the fault condition. Figure 5: The GATE output is terminated when the ISENSE pin voltage reaches the threshold set by the ISET pin. CH2: ISENSE pin, CH4: ISETpin, CH3: GATE pin Figure 4: The fault condition is triggered when the UV pin voltage falls below 1V. The Soft Start capacitor is discharged and the GATE output is disabled. CH2: Envelop of GATE output, CH3: SS pin with 0.01µF capacitor, CH4: UV pin. The current sense signal is prone to leading edge spikes caused by the switching transition. A RC low-pass filter is usually applied to the current signals to avoid premature triggering. However, the low pass filter will inevitably change the shape of the current pulse and also add cost. The CS51221uses leading edge blanking circuitry that blocks out the first 150ns (typ) of each current pulse. This removes the leading edge spikes without altering the current waveform. The blanking is disabled during Soft Start and when the VCOMP is saturated high so that the minimum on-time of the controller does not have the additional blanking period. The max SS detect comparator keeps the blanking function disabled until SS charges fully. The output of the max Duty Cycle detector goes high when the error amplifier output gets saturated high, indicating that the output voltage has fallen well below its regulation point and the power supply may be under load stress. Oscillator and Synchronization The switching frequency is programmable through a RC network connected to the RTCT Pin. As shown in Fig.6, when the RTCT pin reaches 2V, the capacitor is discharged by a 1mA current source and the Gate signal is disabled. When the RTCT pin decreases to 1V, the Gate output is turned on and the discharge current is removed to let the RTCT pin ramp up. This begins a new switching cycle. The CT charging time over the switch period sets the maximum duty cycle clamp which is programmable through the RT value as shown in the Design Guidelines. At the beginning of each switching cycle, the SYNC pin generates a 2.5V, 320nS (typ) pulse. This pulse can be utilized to synchronize other power supplies. Current Sense and Over Current Protection The current can be monitored by the ISENSE pin to achieve pulse by pulse current limit. Various techniques, such as a using current sense resistor or current transformer, can be adopted to derive current signals. The voltage of the ISET pin sets the threshold for maximum current. As shown in Fig. 5, when the ISENSE pin voltage exceeds the ISET voltage, the current limit comparator will reset the GATE latch flipflop to terminate the GATE pulse. 8 Application Information: continued Typical Performance Characteristics Design Guidelines Switch Frequency and Maximum Duty Cycle Calculations Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the discharge time, the internal clock signal sets the Gate output to the low state, thus providing a user selectable maximum duty cycle clamp. Charge and discharge times are determined by following general formulas; CS51221 tC = RTCTln ( (VREF - VVALLEY) (VREF - VPEAK) ) ) , Figure 6: The Sync pin generates a sync pulse at the beginning of each switching cycle. CH2: GATE Pin, CH3: RTCT, CH4: SYNC pin. td = RTCTln ( (VREF - VPEAK - IdRT) (VREF - VVALLEY - IdRT) The bi-directional SYNC pin can also receive an external sync signal of a greater frequency. As show in Fig.7, when the SYNC pin is triggered by an incoming signal, the IC immediately discharges CT. The GATE signal is turned on once the RTCT pin reaches the valley voltage. Because of the steep falling edge, this valley voltage falls below the regular 1V threshold. However, the RTCT pin voltage is then quickly raised by a clamp. When the RTCT pin reaches the 0.95V(typ) Valley Clamp Voltage, the clamp is disconnected after a brief delay and CT is charged through RT. where tC = charging time; td = discharging time; VVALLEY = valley voltage of the oscillator; VPEAK = peak voltage of the oscillator. Substituting in typical values for the parameters in the above formulas: VREF = 3.3V, VVALLEY = 1V, VPEAK = 2V, Id = 1mA tC = 0.57RTCT td = RTCTln ( 1.3 - 0.001RT 2.3- 0.001RT 0.57 ) ) Dmax = 0.57+ In ( 1.3 - 0.001RT 2.3- 0.001RT It is noticed from the equation that for the oscillator to function properly, RT has to be greater than 2.3k. Figure 7: Operation with external sync. CH 2: SYNC pin, CH3: Gate pin, G4: RTCT pin. 9 CS51221 Application Information: continued 800000 700000 Frequency 600000 500000 400000 300000 200000 100000 0 0.0001 50K 10K RT = 5K VIN × TON ≈ ( VOUT × TS n ) n = transformer turns ratio which is a constant determined by the regulated output voltage, switching period and transformer turns ration (use 1 for buck converter). It is interesting to notice from the aforementioned two equations that during steady state, VCOMP doesn’t change for input voltage variations. This intuitively explains why FF voltage mode control has superior line regulation and line transient response. Knowing the nominal value of VIN and TON, one can also select the value of RC to place VCOMP at the center of its dynamic range. Select Feedback Voltage Divider As shown in Fig.10, the voltage divider output feeds to the FB pin, which connects to the inverting input of the error amplifier. The non-inverting input of the error amplifier is connected to a 1.27V (typ) reference voltage. The FB pin has an input current which has to be considered for accurate DC outputs. The following equation can be used to calculate the R1 and R2 value 0.001 CT (µF) 0.01 Figure 8: Typical Performance Characteristics: Oscillator frequency vs CT 1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 1000 10000 100000 1000000 ( R2 R1 + R2 ) VOUT = 1.27 − ∇ where ∇ is the correction factor due to the existence of the FB pin input current Ier. ∇ = (Ri + R1//R2)Ier Ri = DC resistance between the FB pin and the voltage divider output. Ier = VFB input current, 1.3µA typical. Figure 9: Typical Performance Characteristics: Oscillator duty cycle vs RT Select RC for Feed Forward Ramp If the line voltage is much greater than the FF pin Peak Voltage, the charge current can be treated as a constant and is equal to VIN/R. Therefore, the volt-second value is determined by: VIN × TON = (VCOMP − VFF(d)) × R × C where VCOMP = COMP pin voltage VFF(d) = FF pin discharge voltage. As shown in the equation, the volt-second clamp is set by the VCOMP clamp voltage which is equal to 1.8V. In Forward or Flyback circuits, the volt-second clamp value is designed to prevent transformers from saturation. In a buck or forward converter, volt-second is equal to 10 CS51221 Application Information: continued VIN(LOW). Otherwise, two voltage dividers have to be used to program OV and UV separately. VOUT Ier R1 FB VIN R1 R2 R3 COMP Figure 10. The design of feedback voltage divider has to consider the error amplifier input current. Design voltage dividers for OV and UV detection In Fig.11, the voltage divider uses three resistors in series to set OV and UV threshold seen from the input voltage. The values of the resistors can be calculated from the following three equations, where the third equation is derived from OV hysteresis requirement. VIN(LOW) × ( ( R2 + R3 R2 + R3 + R1 ) ) = 1V VIN(HIGH) × R3 R2 + R3 + R1 = 2V 12.5µA × (R1 + R2) = VHYST where VLINE(LOW), VLINE(HIGH) = input voltage OV and UV threshold VHYST = OV hysteresis seen at VIN It is self-evident from equation A and B that to use this design, VIN(HIGH) has to be two times greater than + + - Ri 1.27 R2 VUV Figure 11. OV/UV Monitor Divider. VOV (A) (B) (C) 11 CS51221 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA D Lead Count 16L SO Narrow 16L PDIP Metric Max Min 10.00 9.80 19.69 18.67 English Max Min .394 .386 .775 .735 Thermal Data RΘJC RΘJA typ typ 16L SO Narrow 28 115 16L PDIP 42 80 ˚C/W ˚C/W Surface Mount Narrow Body (D); 150 mil wide 4.00 (.157) 3.80 (.150) 6.20 (.244) 5.80 (.228) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 1.75 (.069) MAX 1.57 (.062) 1.37 (.054) 1.27 (.050) 0.40 (.016) 0.25 (.010) 0.19 (.008) D REF: JEDEC MS-012 0.25 (0.10) 0.10 (.004) Plastic DIP (N); 300 mil wide 7.11 (.280) 6.10 (.240) 8.26 (.325) 7.62 (.300) 3.68 (.145) 2.92 (.115) 1.77 (.070) 1.14 (.045) 2.54 (.100) BSC .356 (.014) .203 (.008) 0.39 (.015) MIN. .558 (.022) .356 (.014) Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. REF: JEDEC MS-001 D Ordering Information Part Number CS51221ED16 CS51221EDR16 CS51221EN16 Rev. 3/26/99 Description 16L SO Narrow 16L SO Narrow (tape & reel) 16L PDIP 12 Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. © 1999 Cherry Semiconductor Corporation