CS8126

CS8126, -1, -2 CS8126,-1,-2 5V, 750mA Low Dropout Linear Regulator with Delayed RESET Description The CS8126 is a low dropout, high current 5V linear regulator. It is an improved replacement for the CS8156. Improvements include higher accuracy, tighter saturation control, better supply rejection, and enhanced RESET circuitry. Familiar PNP regulator features such as reverse battery protection, overvoltage shutdown, thermal shutdown, and current limit make the CS8126 suitable for use in automotive and battery operated equipment. Additional onchip filtering has been included to enhance rejection of high frequency transients on all external leads. An active microprocessor RESET function is included on-chip with externally programmable delay time. During power-up, or after detection of any error in the regulated output, the RESET lead will remain in the low state for the duration of the delay. Types of errors include short circuit, low input voltage, overvoltage shutdown, thermal shutdown, or others that cause the output to become unregulated. This function is independent of the input voltage and will function correctly with an output voltage as low as 1V. Hysteresis is included in both the reset and Delay comparators for enhanced noise immunity. A latching discharge circuit is used to discharge the Delay capacitor, even when triggered by a relatively short fault condition. This circuit improves upon the commonly used SCR structure by providing full capacitor discharge (0.2V type). Note:The CS8126 is lead compatible with the LM2925, TLE4260, L4947, LM2927, and LM2926. Features s Low Dropout Voltage (0.6V at 0.5A) s 3% Output Accuracy s Active RESET s External RESET Delay for Reset s Protection Circuitry Reverse Battery Protection +60V, -50V Peak Transient Voltage Short Circuit Protection Internal Thermal Overload Protection Package Options 16 Lead SOIC Wide VIN NC NC NC 1 Block Diagram VOUT NC VOUT(SENSE) NC NC Gnd NC NC VIN Over Voltage Shutdown NC ÐÐÐÐÐÐ RESET NC VOUT PreRegulator Regulated Supply for Circuit Bias Bandgap Reference Charge Current Generator Error Amp Anti-Saturation and Current Limit Delay 7 L D2PAK Tab (Gnd) + 5 L TO-220 Tab (Gnd) Thermal Shutdown 1 Delay Q - Latching Discharge S R + + Reset Comparator Delay Comparator VDischarge + - RESET 1 2 3 4 5 6 7 VIN VOUT VOUT(SENSE) Gnd Delay RESET NC 1 CS8126-1 1 VIN 2 VOUT 3 Gnd 4 Delay 5 RESET CS8126-2 1 VIN 2 RESET 3 Gnd 4 Delay 5 VOUT Gnd Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com Rev. 5/4/99 1 A ¨ Company CS8126, -1, -2 Absolute Maximum Ratings Power Dissipation.............................................................................................................................................Internally Limited Peak Transient Voltage (46V Load Dump) .................................................................................................................-50V, 60V Output Current .................................................................................................................................................Internally Limited ESD Susceptibility (Human Body Model)..............................................................................................................................4kV Junction Temperature .............................................................................................................................................-40¡C to 150¡C Storage Temperature...............................................................................................................................................-55¡C to 150¡C Lead Temperature Soldering Wave Solder (through hole styles only) ..........................................10 sec. max, 260¡C peak Reflow (SMD styles only) ..........................................60 sec. max above 183¡C, 230¡C peak Electrical Characteristics: TA = -40ûC to +125ûC, TJ = -40ûC to +150ûC, VIN = 6 to 26V, IO=5 to 500mA, RRESET = 4.7k½ to VCC, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT s Output Stage (VOUT) Output Voltage Dropout Voltage Supply Current IOUT = 500mA IOUT ² 10mA IOUT ² 100mA IOUT ² 500mA VIN = 6 to 26V, IOUT = 50mA IOUT = 50 to 500mA, VIN = 14V f = 120Hz, VIN = 7 to 17V, IOUT = 250mA 54 0.75 32 VOUT ² 5.5V VOUT ³ -0.6V, 10½ Load 1% Duty Cycle, T < 100ms, 10½ Load Guaranteed by Design 150 -15 95 -30 -80 180 210 4.85 5.00 0.35 2 6 55 5 10 75 1.20 40 5.15 0.60 7 12 100 50 50 V V mA Line Regulation Load Regulation Ripple Rejection Current Limit Overvoltage Shutdown Maximum Line Transient Reverse Polarity Input Voltage DC Reverse Polarity Input Voltage Transient Thermal Shutdown s RESET and Delay Functions Delay Charge Current RESET Threshold RESET Hysteresis Delay Threshold Delay Hysteresis RESET Output Voltage Low RESET Output Leakage Current Delay Capacitor Discharge Voltage Delay Time mV mV dB A V V V V ¡C VDelay = 2V VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) VRH = VRT(ON) - VRT(OFF) Charge, VDC(HI) Discharge, VDC(LO) 1V < VOUT < VRTL , 3k½ to VOUT VOUT > VRT(ON) Discharge Latched ÒONÓ, VOUT > VRT CDelay = 0.1µF* (Note 1) 5 4.65 4.50 150 3.25 2.85 200 10 4.90 4.70 200 3.50 3.10 400 0.1 0 0.2 15 VOUT - 0.01 VOUT - 0.15 250 3.75 3.35 800 0.4 10 0.5 48 µA V V mV V V mV V µA V ms 16 32 Delay Time = CDelay ´ VDelay Threshold Charge = CDelay x 3.2 x 10 5 (typ) ICharge Note 1: assumes ideal capacitor 2 CS8126, -1, -2 Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION 5 Lead TO-220 8126-1 8126-2 1 2 3 4 5 1 5 3 4 2 7Lead D2PAK 1 2 4 5 6 16 Lead SOIC Wide 1 16 11 8 6 VIN VOUT Gnd Delay RESET Unregulated supply voltage to IC. Regulated 5V output. Ground connection. Timing capacitor for RESET function. CMOS/TTL compatible output lead. RESET goes low after detection of any error in the regulated output or during power up. Remote sensing of output voltage. No Connection. 3 7 14 2, 3, 4, 5, 7, 9, 10, 12, 13, 15 VOUT(SENSE) NC Typical Performance Characteristics ICQ vs. VIN over Temperature RLOAD= 25W ICQ vs. VIN over RLOAD Room Temp. 55.0 50.0 45.0 40.0 ICQ (mA) 30.0 25.0 20.0 15.0 10.0 5.0 0.0 125ûC 25ûC ICQ (mA) 35.0 -40ûC 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VIN (V) 120.0 110.0 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 VIN (V) Rload = 6.67 Rload = 10 Rload = 25 Rload = NO LOAD 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VOUT vs VIN over Temperature RLOAD = 25W VOUT vs. VIN over RLOAD Room Temp. 5.5 5.0 4.5 4.0 3.5 VOUT (V) VOUT (V) 5.5 5.0 4.5 4.0 3.5 125ûC Rload = 6.67 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Rload = NO LOAD Rload = 10 25ûC -40ûC 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VIN (V) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VIN (V) 3 CS8126, -1, -2 Typical Performance Characteristics: continued Line Regulation vs. Output Current over Temperature 100 80 60 Load Regulation (mV) Line Regulation (mV) VIN 6-26V Load Regulation vs. Output Current over Temperature 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 VIN = 14V TEMP = 125ûC TEMP = 25ûC TEMP = -40ûC 40 20 0 -20 -40 -60 -80 -100 0 100 200 300 400 500 600 700 800 Output Current (mA) TEMP = 125ûC TEMP = 25ûC TEMP = 40ûC 0 100 200 300 400 500 600 700 800 Output Current (mA) Dropout Voltage vs. Output Current over Temperature 900 800 Quiescent Current (mA) Dropout Voltage (mV) Quiescent Current vs. Output Current over Temperature 100 90 80 70 60 50 40 30 20 10 0 VIN = 14V 25ûC 125ûC 700 600 500 400 300 200 100 0 0 100 200 300 400 500 600 700 800 Output Current (mA) -40ûC 125ûC 25ûC -40ûC 0 100 200 300 400 500 600 700 800 Output Current (mA) Ripple Rejection IOUT= 250mA Output Capacitor ESR 103 102 101 ESR (ohms) COUT= 47/68mF Stable Region 90 80 70 Rejection (dB) COUT= 10mF, ESR = 1 & 0.1mF, ESR = 0 60 50 40 30 20 10 0 10 0 100 10-1 10-2 COUT= 10mF, ESR = 1W COUT= 47mF COUT= 68mF COUT= 10mF, ESR = 10W 10 7 8 -3 10 1 10 2 10 3 10 4 10 5 10 6 10 10 10-4 100 101 102 103 Freq. (Hz) Output Current (mA) 4 CS8126, -1, -2 RESET Circuit Waveform (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0V) VOUT VRT(ON) VRT(OFF) VRH RESET (1) (2) VRL (3) tDelay Delay VDH VDC(HI) VDC(LO) (2) VDIS Circuit Description The CS8126 RESET function, has hysteresis on both the Reset and Delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram). Low Voltage Inhibit Circuit This circuit monitors output voltage, and when the output voltage falls below VRT(OFF), causes the RESET output transistor to be in the ON (saturation) state. When the output voltage rises above VRT(ON), this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit. RESET Delay Circuit This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the "Low Voltage Inhibit" circuit indicates that output voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage falls below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a controlled RESET pulse is generated following detection of an error condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(H1). The Delay time for the RESET function is calculated from the formula: CDelay ´ VDelay Threshold Delay time = ICharge Delay time = CDelay ´ 3.2 ´ 10 5 If CDelay = 0.1µF, Delay time (ms) = 32ms ± 50%: i.e. 16ms to 48ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. 5 CS8126, -1, -2 Application Diagram VIN C 1* 100nF VOUT CS8126 Delay RESET RRST 4.7kW C2** 10mF to 100mF Gnd Delay 0.1mF C1* is required if the regulator is far from the power source filter. C2** is required for stability Application Notes Stability Considerations The output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25¡C to -40¡C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. 6 This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Remove the unit from the environmental chamber and heat the IC with a heat gun. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of +/- 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 1) is: PD(max) = {VIN(max) - VOUT(min)}IOUT(max) + VIN(max)IQ where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). (1) CS8126, -1, -2 Application Notes: continued Once the value of PD(max) is known, the maximum permissible value of RQJA can be calculated: 150¡C - TA RQJA = PD (2) Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RQJA. RQJA = RQJC + RQCS + RQSA where: RQJC = the junctionÐtoÐcase thermal resistance, RQCS = the caseÐtoÐheatsink thermal resistance, and RQSA = the heatsinkÐtoÐambient thermal resistance. IIN VIN The value of RQJA can then be compared with those in the package section of the data sheet. Those packages with RQJA's less than the calculated value in equation 2 will keep the die temperature below 150¡C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. (3) Smart Regulator IOUT VOUT } RQJC appears in the package section of the data sheet. Like RQJA, it is a function of package type. RQCS and RQSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. Control Features IQ Figure 1. Single output regulator with key performance parameters labeled. 7 CS8126 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA D Lead Count 16 Lead SO Wide Metric Max Min 10.50 10.10 English Max Min .413 .398 Thermal Data RQJC typ RQJA typ 5 Lead TO-220 2.1 50 7 Lead D2PAK 2.1 10-50* 16 Lead SOIC Wide 23 ûC/W 105 ûC/W *Depending on thermal properties of substrate. RQJA = RQJC + RQCA. Surface Mount Wide Body (DW); 300 mil wide 5 Lead TO-220 (THA) Horizontal 4.83 (.190) 10.54 (.415) 9.78 (.385) 1.40 (.055) 3.96 (.156) 3.71 (.146) 1.14 (.045) 4.06 (.160) 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) 2.87 (.113) 2.62 (.103) 6.55 (.258) 5.94 (.234) 14.99 (.590) 14.22 (.560) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 2.77 (.109) 6.83 (.269) 2.49 (.098) 2.24 (.088) 2.65 (.104) 2.35 (.093) 0.81(.032) 1.68 (.066) TYP 1.70 (.067) 6.81(.268) 0.56 (.022) 0.36 (.014) 6.60 (.260) 5.84 (.230) 2.92 (.115) 2.29 (.090) 1.27 (.050) 0.40 (.016) REF: JEDEC MS-013 0.32 (.013) 0.23 (.009) D 0.30 (.012) 0.10 (.004) 5 Lead TO-220 (T) Straight 5 Lead TO-220 (TVA) Vertical 4.83 (.190) 4.06 (.160) 3.96 (.156) 3.71 (.146) 6.55 (.258) 5.94 (.234) 2.87 (.113) 2.62 (.103) 14.99 (.590) 14.22 (.560) 1.40 (.055) 1.14 (.045) 10.54 (.415) 9.78 (.385) 3.96 (.156) 3.71 (.146) 4.83 (.190) 4.06 (.160) 10.54 (.415) 9.78 (.385) 2.87 (.113) 6.55 (.258) 2.62 (.103) 5.94 (.234) 1.40 (.055) 1.14 (.045) 14.99 (.590) 14.22 (.560) 1.78 (.070) 14.22 (.560) 13.72 (.540) 8.64 (.340) 7.87 (.310) 2.92 (.115) 2.29 (.090) 4.34 (.171) 1.68 (.066) typ 6.80 (.268) 0.56 (.022) 0.36 (.014) 7.51 (.296) 1.02 (.040) 0.76 (.030) 1.70 (.067) 1.02(.040) 0.63(.025) 6.93(.273) 6.68(.263) 1.83(.072) 1.57(.062) 0.56 (.022) 0.36 (.014) .94 (.037) .69 (.027) 2.92 (.115) 2.29 (.090) 8 CS8126 Package Specification: continued PACKAGE DIMENSIONS IN mm (INCHES) 7 Lead D2PAK (DPS)* Short-Leaded 1.68 (.066) 1.40 (.055) 10.31 (.406) 10.05 (.396) 1.40 (.055) 1.14 (.045) 5 Lead TO-220 (THE) SMD 3.96 (.156) 3.71 (.146) 10.3 (.405) 10.0 (.395) 5° (5 Places) 2.87 (.113) 2.61 (.103) 14.6 (.575) 14.0 (.550) 8.40 (.331) 2.66 (.105) 2.56 (.101) 1.98 (.078) 1.47 (.058) 1.40 (.055) 1.14 (.045) 8.53 (.336) 8.28 (.326) 14.71 (.579) 13.69 (.539) 2.79 (.110) 2.54 (.100) 0.91 (.036) 0.66 (.026) TERMINAL 8 6.50 (.256) REF 1.27 (.050) REF .254 (.010) REF .914 (.036) .711 (.028) 1.70 (.067) A 6.80 (.268) 2.03 (.080) .254 (.010) REF 7.75 (.305) REF 4.57 (.180) 4.31 (.170) 4.44 (.175) B .102 (.004) MAX .254 (.010) .000 (.000) Notes: 1. Dimensions exclusive of mold flash and metal burrs. 2. Footpad length measured from lead tip with ref. to datum A . 3. Coplanarity .004² max. Reference plane B standoff height .000Ð.010². 0.10 (.004) 0.00 (.000) *CHERRY SEMICONDUCTOR SHORT-LEADED FOOTPRINT Ordering Information Part Number CS8126-1YT5 CS8126-1YTVA5 CS8126-1YTHA5 CS8126-2GT5 CS8126-2GTVA5 CS8126-2GTHA5 CS8126-1YTHE5 CS8126-1YTHER5 CS8126YDPS7 CS8126YDPSR7 CS8126YDW16 CS8126YDWR16 Rev. 5/4/99 Description 5 Lead TO-220 Straight 5 Lead TO-220 Vertical 5 Lead TO-220 Horizontal 5 Lead TO-220 Straight 5 Lead TO-220 Vertical 5 Lead TO-220 Horizontal 5 Lead TO-220 Surface Mount 5 Lead TO-220 Surface Mount (tape & reel) 7 Lead D2PAK Short-Leaded 7 Lead D2PAK Short-Leaded (tape & reel) 16 Lead SOIC Wide 16 Lead SOIC Wide (tape & reel) 9 Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. © 1999 Cherry Semiconductor Corporation