CS5102A-BL

CS5101A CS5102A 16-bit, 100 kSps / 20 kSps A/D Converters Features Monolithic CMOS A/D Converters – Inherent Sampling Architecture – 2-channel Input Multiplexer – Flexible Serial Output Port Description The CS5101A and CS5102A are 16-bit monolithic CMOS analog-to-digital converters (ADCs) capable of 100 kSps (5101A) and 20 kSps (5102A) throughput. The CS5102A’s low power consumption of 44mW, coupled with a power-down mode, makes it particularly suitable for battery-powered operation. On-chip self-calibration circuitry achieves nonlinearity of ±0.001% of FS and guarantees 16-bit, no missing codes over the entire specified temperature range. Superior linearity also leads to 92 dB S/(N+D) with harmonics below -100 dB. Offset and full-scale errors are minimized during the calibration cycle, eliminating the need for external trimming. The CS5101A and CS5102A each consist of a 2-channel input multiplexer, DAC, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. The inherent sampling architecture of the device eliminates the need for an external track-and-hold amplifier. The converters’ 16-bit data is output in serial form with either binary or two’s complement coding. Three output timing modes are available for easy interfacing to microcontrollers and shift registers. Unipolar and bipolar input ranges are digitally selectable ORDERING INFORMATION See “Ordering Information” on page 38. Ultra-low Distortion – S/(N+D): 92 dB – TDH: 0.001% Conversion Time – CS5101A: 8µs – CS5102A: 40 µs Linearity Error: ±0.001% FS – Guaranteed No Missing Codes Self-calibration Maintains Accuracy – Accurate Over Time & Temperature Low Power Consumption – CS5101A: 320 mW – CS5102A: 44 mW I HOLD SLEEP RST STBY CODE BP/UP CRS/FIN TRK1 TRK2 SSH/SDL SDATA 12 28 2 5 16 17 10 8 9 11 15 CLKIN XOUT REFBUF VREF AIN1 AIN2 CH1/2 AGND 3 4 21 20 19 24 13 22 Clock Generator 14 Control Calibration SRAM SCLK + + + 25 VA+ 23 VA- Microcontroller 26 TEST SCKMOD OUTMOD 16-Bit Charge Redistribution DAC + Comparator 27 18 6 DGND 1 VD- 7 VD+ http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) JAN ‘06 DS45F6 CS5101A CS5102A TABLE OF CONTENTS 1. CHARACTERISTICS & SPECIFICATIONS ............................................................................. 4 ANALOG CHARACTERISTICS, CS5101A............................................................................... 4 SWITCHING CHARACTERISTICS, CS5101A ......................................................................... 6 ANALOG CHARACTERISTICS, CS5102A............................................................................... 7 SWITCHING CHARACTERISTICS, CS5102A ......................................................................... 9 SWITCHING CHARACTERISTICS, ALL DEVICES ............................................................... 11 DIGITAL CHARACTERISTICS, ALL DEVICES...................................................................... 13 RECOMMENDED OPERATING CONDITIONS ..................................................................... 13 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 14 2. OVERVIEW ............................................................................................................................. 15 3. THEORY OF OPERATION ..................................................................................................... 15 3.1 Calibration ........................................................................................................................ 16 4. FUNCTIONAL DESCRIPTION ............................................................................................... 17 4.1 Initiating Conversions ....................................................................................................... 17 4.2 Tracking the Input ............................................................................................................ 17 4.3 Master Clock .................................................................................................................... 18 4.4 Asynchronous Sampling Considerations ......................................................................... 18 4.5 Analog Input Range/Coding Format ................................................................................ 19 4.6 Output Mode Control ........................................................................................................ 19 4.6.1 Pipelined Data Transmission .............................................................................. 19 4.6.2 Register Burst Transmission (RBT) .................................................................... 20 4.6.3 Synchronous Self-clocking (SSC) ....................................................................... 20 4.6.4 Free Run (FRN) .................................................................................................. 20 5. SYSTEM DESIGN USING THE CS5101A & CS5102A ......................................................... 22 5.1 System Initialization ......................................................................................................... 22 5.2 Single-channel Operation ................................................................................................ 23 6. ANALOG CIRCUIT CONNECTIONS ...................................................................................... 23 6.1 Reference Considerations ............................................................................................... 23 6.2 Analog Input Connection ................................................................................................. 24 6.3 Sleep Mode Operation ..................................................................................................... 24 6.4 Grounding & Power Supply Decoupling ........................................................................... 25 7. CS5101A & CS5102A PERFORMANCE ............................................................................... 26 7.1 Differential Nonlinearity .................................................................................................... 26 7.2 FFT Tests and Windowing ............................................................................................... 28 7.3 Sampling Distortion .......................................................................................................... 30 7.4 Noise ................................................................................................................................ 31 7.5 Aperture Jitter .................................................................................................................. 31 7.6 Power Supply Rejection ................................................................................................... 32 8. PIN DESCRIPTIONS .............................................................................................................. 33 8.1 Power Supply Connections .............................................................................................. 33 8.2 Oscillator .......................................................................................................................... 34 8.3 Digital Inputs .................................................................................................................... 34 8.4 Analog Inputs ................................................................................................................... 35 8.5 Digital Outputs ................................................................................................................. 35 8.6 Analog Outputs ................................................................................................................ 35 8.7 Miscellaneous .................................................................................................................. 35 9. PARAMETER DEFINITIONS .................................................................................................. 36 10. PACKAGE DIMENSIONS ..................................................................................................... 37 11. ORDERING INFORMATION ................................................................................................ 38 12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .......................... 38 13. REVISIONS .......................................................................................................................... 39 2 DS45F6 CS5101A CS5102A LIST OF FIGURES Figure 1. Reset, Calibration, and Control Timing .......................................................................... 10 Figure 2. Serial Communication Timing ........................................................................................ 12 Figure 3. Coarse Charge Input Buffers & Charge Redistribution DAC.......................................... 15 Figure 4. Coarse/Fine Charge Control .......................................................................................... 18 Figure 5. Pipelined Data Transmission (PDT) Mode Timing ......................................................... 20 Figure 6. Register Burst Transmission (RBT) Mode Timing.......................................................... 21 Figure 7. Synchronous Self-clocking (SSC) Mode Timing ............................................................ 21 Figure 8. Free Run (FRN) Mode Timing........................................................................................ 21 Figure 9. CS5101A/CS5102A System Connection Diagram......................................................... 22 Figure 10. Power-up Reset Circuit ................................................................................................ 23 Figure 11. Reference Connections................................................................................................ 24 Figure 12. Charge Settling Time ................................................................................................... 24 Figure 13. CS5101A DNL Plot - Ambient Temperature at 25 °C .................................................. 27 Figure 14. CS5101A DNL Plot - Ambient Temperature at 138 °C ................................................ 27 Figure 15. CS5102A DNL Plot - Ambient Temperature at 25 °C .................................................. 27 Figure 16. CS5102A DNL Plot - Ambient Temperature at 138 °C ................................................ 27 Figure 17. CS5101A DNL Error Distribution.................................................................................. 28 Figure 18. CS5102A DNL Error Distribution.................................................................................. 28 Figure 19. CS5101A FFT (SSC Mode, 1-Channel)....................................................................... 29 Figure 20. CS5101A FFT (SSC Mode, 1-Channel)....................................................................... 29 Figure 21. CS5102A FFT (SSC Mode, 1-Channel)....................................................................... 29 Figure 22. CS5102A FFT (SSC Mode, 1-Channle)....................................................................... 29 Figure 23. CS5101A Histogram Plot of 8192 Conversion Inputs .................................................. 31 Figure 24. CS5102A Histogram Plot of 8192 Conversion Inputs .................................................. 31 Figure 25. Power Supply Rejection ............................................................................................... 32 Figure 26. CS5101A & CS5102A 28-pin PLCC Pinout ................................................................. 33 Figure 27. 28-Pin PLCC Mechanical Drawing............................................................................... 37 LIST OF TABLES Table 1. Output Coding ................................................................................................................. 19 Table 2. Output Mode Control ....................................................................................................... 19 DS45F6 3 CS5101A CS5102A 1. CHARACTERISTICS & SPECIFICATIONS ANALOG CHARACTERISTICS, CS5101A (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; Full-scale Input sine wave, 1 kHz; CLKIN = 8 MHz; fs = 100 kSps; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each channel tested separately; Analog Source Impedance = 50 Ω with 1000 pF to AGND unless otherwise specified) CS5101A-J Parameter* Specified Temperature Range Accuracy Linearity Error -J (Note 1) -B Drift (Note 2) (Note 3) -J (Note 1) -B Drift (Note 2) -J (Note 1) -B Drift (Note 2) -J (Note 1) -B Drift (Note 2) -J (Note 1) -B Drift (Note 2) (Note 1) -J -B -J -B -J -B (Note 1) -J -B -J -B (Note 4) Unipolar Mode Bipolar Mode 35 70 87 90 90 92 30 32 96 98 85 85 100 102 88 91 0.002 0.001 16 CS5101A-B Min Typ Max Unit ºC %FS %FS ∆LSB Bits LSB LSB ∆LSB LSB LSB ∆LSB LSB LSB ∆LSB LSB LSB ∆LSB -40 to +85 16 0.002 0.003 0.001 0.002 ±¼ ±1 ±1 ±1 ±2 ±2 ±1 ±2 ±2 ±2 ±1 ±1 ±1 ±4 ±3 ±5 ±4 ±5 ±3 ±4 ±3 - Min Typ 0 to +70 Max 0.002 0.003 0.001 0.002 ±¼ ±1 ±1 ±1 ±2 ±2 ±1 ±2 ±2 ±1 ±1 ±1 ±1 ±4 ±3 ±5 ±4 ±5 ±3 ±4 ±3 - Differential Linearity Full-scale Error - Unipolar Offset Bipolar Offset Bipolar Negative Full-scale Error Dynamic Performance (Bipolar Mode) Peak Harmonic or Spurious Noise 1-kHz Input 12-kHz Input Total Harmonic Distortion Signal-to-Noise Ratio 0 dB Input -60 dB Input Noise 96 98 85 85 87 90 100 102 88 91 0.002 0.001 90 92 30 32 35 70 dB dB dB dB % % dB dB dB dB µVrms µVrms Notes: 1. Applies after calibration at any temperature within the specified temperature range. 2. Total drift over specified temperature range after calibration at power-up, at 25º C. 3. 4. Minimum resolution for which no missing codes is guaranteed over the specified temperature range. Wideband noise aliased into the baseband, referred to the input. * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet. 4 DS45F6 CS5101A CS5102A ANALOG CHARACTERISTICS, CS5101A (Continued) CS5101A-J Parameter* Specified Temperature Range Analog Input Aperture Time Aperture Jitter Input Capacitance Unipolar Mode Bipolar Mode Conversion and Throughput Conversion Time Acquisition Time Throughput Power Supplies Power Supply Current (SLEEP High) Power Consumption Positive Analog Negative Analog Positive Digital Negative Digital (Note 9, Note 10) (SLEEP High) (SLEEP Low) (Note 9) I A+ I AID+ IDPdo Pds PSR PSR 21 -21 11 -11 320 1 84 84 28 -28 15 -15 430 21 -21 11 -11 320 1 84 84 28 -28 15 -15 430 mA mA mA mA mW mW dB dB (Note 6) tc (Note 7) ta (Note 8) ftp 100 100 kSps 1.88 1.88 µs 8.12 8.12 µs (Note 5) 320 200 425 265 320 200 425 265 pF pF - CS5101A-B Min Typ Max Unit ºC ns ps -40 to +85 25 100 Symbol - Min Typ 0 to +70 25 100 Max Power Supply Rejection (Note 11) Positive Supplies Negative Supplies 6. Notes: 5. Applies only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN) mode) with 8.0 MHz CLKIN. In PDT, RBT, and SSC modes, asynchronous delay between the falling edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1.5 master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can be increased as long as the HOLD sample rate is 100 kHz max. The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 µs of fine charge. FRN mode allows 9 cycles for fine charge which provides for the minimum 1.125 µs with an 8MHz clock, however; in PDT, RBT, or SSC modes and at clock frequencies of 8 MHz or less, fine charge may be less than 9 clock cycles. This reflects the typical specification (6 clock cycles + 1.125 µs). Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition and conversion times, as described above. All outputs unloaded. All inputs at VD+ or DGND. Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low). With 300 mV p-p, 1-kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipolar mode to 90 dB. Figure 25 shows a plot of typical power supply rejection versus frequency. 7. 8. 9. 10. 11. DS45F6 5 CS5101A CS5102A SWITCHING CHARACTERISTICS, CS5101A (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF). Parameter CLKIN Period Symbol tclk Min 108 37.5 37.5 2.0 150 66tclk 1tclk+20 15 95 Typ 2 100 11,528,160 80 60 120 - Max 10,000 9.216 68tclk+260 68tclk+260 63tclk 64tclk 1tclk+10 Unit ns ns ns MHz ms ns ns tclk ns ns ns ns ns ns ns ns CLKIN Low Time CLKIN High Time Crystal Frequency SLEEP Rising to Oscillator Stable RST Pulse Width RST to STBY falling RST Rising to STBY Rising CH1/2 Edge to TRK1, TRK2 Rising CH1/2 Edge to TRK1, TRK2 Falling HOLD to SSH Falling HOLD to TRK1, TRK2 Falling HOLD to TRK1, TRK2, SSH Rising HOLD Pulse Width HOLD to CH1/2 Edge HOLD Falling to CLKIN Falling FRN mode (100 kSps). 13. 14. 15. tclkl tclkh (Note 12) fxtal (Note 13) trst tdrrs tcal (Note 14) (Note 14) (Note 15) (Note 15) (Note 15) (Note 16) (Note 15) (Note 16) tdrsh1 tdfsh4 tdfsh2 tdfsh1 tdrsh thold tdhlri thcf Notes: 12. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 8.0 MHz in With an 8.0 MHz crystal, two 10 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 9). These timings are for FRN mode. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge occurs after HOLD rises to 64tclk after HOLD has fallen. These timings are for PDT and RBT modes. 16. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling edge of CLLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as narrow as 150 ns for all CLKIN frequencies if CLKIN falls 95 ns after HOLD falls. This ensures that the HOLD pulse will meet the minimum specification for thcf. 6 DS45F6 CS5101A CS5102A ANALOG CHARACTERISTICS, CS5102A (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; Full-scale Input Sine Wave, 200 Hz; CLKIN = 1.6 MHz; fs = 20 kSps; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each channel tested separately; Analog Source Impedance = 50 Ω with 1000 pF to AGND unless otherwise specified) CS5102A-J Parameter* Specified Temperature Range Accuracy Linearity Error -J (Note 1) -B Drift (Note 2) (Note 3) -J (Note 1) -B Drift (Note 2) -J (Note 1) -B Drift (Note 2) -J (Note 1) -B Drift (Note 2) -J (Note 1) -B Drift (Note 2) (Note 1) -J -B Total Harmonic Distortion Signal-to-Noise Ratio 0 dB Input -60 dB Input Noise Unipolar Mode Bipolar Mode -J -B (Note 1) -J -B -J -B (Note 4) 35 70 87 90 90 92 30 32 87 90 96 98 100 102 0.002 0.001 96 98 16 CS5102A-B Min Typ Max Unit ºC %FS %FS ∆LSB Bits LSB LSB ∆LSB LSB LSB ∆LSB LSB LSB ∆LSB LSB LSB ∆LSB -40 to +85 16 0.002 0.003 0.001 0.0015 ±¼ ±2 ±2 ±1 ±1 ±1 ±1 ±1 ±1 ±2 ±2 ±2 ±2 ±4 ±3 ±4 ±3 ±4 ±3 ±4 ±3 - Min Typ 0 to +70 Max 0.002 0.003 0.001 0.0015 ±¼ ±2 ±2 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±2 ±2 ±1 ±4 ±3 ±4 ±3 ±4 ±3 ±4 ±3 - Differential Linearity Full-scale Error - Unipolar Offset Bipolar Offset Bipolar Negative Full-scale Error Dynamic Performance (Bipolar Mode) Peak Harmonic or Spurious Noise 100 102 0.002 0.001 90 92 30 32 35 70 dB dB % % dB dB dB dB µVrms µVrms * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet. DS45F6 7 CS5101A CS5102A ANALOG CHARACTERISTICS, CS5102A (Continued) CS5102A-J Parameter* Specified Temperature Range Analog Input Aperture Time Aperture Jitter Input Capacitance Unipolar Mode Bipolar Mode Conversion and Throughput Conversion Time Acquisition Time Throughput Power Supplies Power Supply Current (SLEEP High) Power Consumption Positive Analog Negative Analog Positive Digital Negative Digital (Note 10, Note 20) (SLEEP High) (SLEEP Low) (Note 20) I A+ I AID+ IDPdo Pds PSR PSR 2.4 -2.4 2.5 -1.5 44 1 84 84 3.5 -3.5 3.5 -2.5 65 2.4 -2.4 2.5 -1.5 44 1 84 84 3.5 -3.5 3.5 -2.5 65 mA mA mA mA mW mW dB dB (Note 17) (Note 18) (Note 19) tc ta ftp 20 40.625 9.375 20 40.625 9.375 µs µs kSps (Note 5) 320 200 425 265 320 200 425 265 pF pF - CS5102-B Min Typ Max Unit ºC ns ps -40 to +85 30 100 Symbol - Min Typ 0 to +70 30 100 Max Power Supply Rejection (Note 21) Positive Supplies Negative Supplies Notes: 17. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN) mode. In PDT, RBT, and SSC modes, asynchronous delay between the falling edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge. FRN mode allows 9 cycles for fine charge which provides for the minimum 5.625 µs with a 1.6 MHz clock, however; in PDT, RBT, or SSC modes and at clock frequencies of less than 1.6 MHz, fine charge may be less than 9 clock cycles. 19. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition and conversion times, as described above. 20. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation versus clock frequency. 21. With 300 mV p-p, 1-kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipolar mode to 90 dB. Figure 25 shows a plot of typical power supply rejection versus frequency. 18. Typical Power (mW) 34 37 39 41 44 CLKIN (MHz) 0.8 1.0 1.2 1.4 1.6 8 DS45F6 CS5101A CS5102A SWITCHING CHARACTERISTICS, CS5102A (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF). Parameter CLKIN Period CLKIN Low Time CLKIN High Time Crystal Frequency SLEEP Rising to Oscillator Stable RST Pulse Width RST to STBY falling RST Rising to STBY Rising CH1/2 Edge to TRK1, TRK2 Rising CH1/2 Edge to TRK1, TRK2 Falling HOLD to SSH Falling HOLD to TRK1, TRK2 Falling HOLD to TRK1, TRK2, SSH Rising HOLD Pulse Width HOLD to CH1/2 Edge HOLD Falling to CLKIN Falling 23. 24. 25. 26. 27. Symbol (Note 22) tclk tclkl tclkh (Note 22, Note 23) (Note 24) fxtal trst tdrrs tcal (Note 25) (Note 25) (Note 26) (Note 26) (Note 26) (Note 27) (Note 26) (Note 27) tdrsh1 tdfsh4 tdfsh2 tdfsh1 tdrsh thold tdhlri thcf Min 0.5 200 200 0.9 150 66tclk 1tclk+20 15 55 Typ 1.6 20 100 2,882,040 80 60 120 - Max 10 2.0 68tclk+260 68tclk+260 63tclk 64tclk 1tclk+10 Unit µs ns ns MHz ms ns ns tclk ns ns ns ns ns ns ns ns Notes: 22. Minimum CLKIN period is 0.625 ms in FRN mode (20 kSps). External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 1.6 MHz in FRN mode (20 kSps). With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 9). These timings are for FRN mode. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge occurs after HOLD rises to 64tclk after HOLD has fallen. These timings are for PDT and RBT modes. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling edge of CLLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as narrow as 150 ns for all CLKIN frequencies if CLKIN falls 55 ns after HOLD falls. This ensures that the HOLD pulse will meet the minimum specification for thcf. DS45F6 9 CS5101A CS5102A t rst RST t ca l STBY t drrs Reset and Calibration Timing HO LD C H 1 /2 S S H /S D L t drsh 1 T R K 1,T R K 2 T R K 1,T R K 2 t dfsh4 S S H ,T R K 1 ,T R K 2 T R K 1,T R K 2 a. FRN Mode t dfsh2 t drsh t dfsh1 b. PDT, RBT Mode Control Output Timing th c f C H 1 /2 t d h lri H OLD t ho ld Channel Selection Timing Start Conversion Timing C LK IN HOLD Figure 1. Reset, Calibration, and Control Timing 10 DS45F6 CS5101A CS5102A SWITCHING CHARACTERISTICS, ALL DEVICES (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF). Parameter PDT & RBT Modes SCLK Input Pulse Period SCLK Input Pulse Width Low SCLK Input Pulse Width High SCLK Input Falling to SDATA Valid HOLD Falling to SDATA Valid TRK1, TRK2 Falling to SDATA Valid FRN & SSC Modes SCLK Output Pulse Width Low SCLK Output Pulse Width High SDATA Valid Before Rising SCLK SDATA Valid After RIsing SCLK SDL Falling to 1st Rising SCLK Last Rising SCLK to SDL Rising HOLD Falling to 1st Falling SCLK CH1/2 Edge to 1st Falling SCLK valid tdss time after the next falling SCLK. Symbol tsclk tsclkl tsclkh tdss PDT Mode (Note 28) tdhs tdts tslkl tslkh tss tsh trsclk CS5101A CS5102A CS5101A CS5102A trsdl trsdl thfs thfs tdhlri Min 200 50 50 2tclk-100 2tclk-100 66tclk 6tclk 6tclk - Typ 100 140 65 2tclk 2tclk 2tclk 2tclk 2tclk 7tclk Max 150 230 125 68tclk+260 2tclk+165 2tclk+200 8tclk+165 8tclk+200 64tclk Unit ns ns ns ns ns ns tclk tclk ns ns ns ns ns tclk Notes: 28. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is DS45F6 11 CS5101A CS5102A H O LD t h fs t chfs C H 1 /2 S S H /S D L t rsclk t sclkl S C LK t sc lkh SCLK t d ss t sclk t ss SDATA t sh MSB LSB t slkl t slkh t d ss t rsd l SDATA a. SCLK Input (PDT & RBT Modes) b. SCLK Output (FRN & SSC Modes) Serial Data Timing HOLD t dhs SDATA MSB T R K 1, T R K 2 t d ts MSB t dss M S B -1 SDATA SCLK SCLK a. Pipelined Data Transmission (PDT) b. Register Burst Transmission (RBT) Data Transmission Timing Figure 2. Serial Communication Timing 12 DS45F6 CS5101A CS5102A DIGITAL CHARACTERISTICS, ALL DEVICES (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10% Parameter Calibration Memory Retention Power Supply Voltage VA+ and VD+ High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage (except XOUT) Input Leakage Current Digital Output Pin Capacitance 29. Symbol (Note 29) VMR VIH VIL (Note 30) Iout = 1.6 mA VOH VOL Iin Cout Min 2.0 2.0 (VD+) -1.0 - Typ 9 Max 0.8 0.4 10 - Unit V V V V V µA pF VA- and VD- can be any value from 0 to +5V for memory retention. Neither VA- nor VD- should be allowed to go positive. AIN1, AIN2, or VREF must not be greater than VA+ or VD+. This parameter is guaranteed by characterization. 30. IOUT = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40 µA). RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 31) Parameter DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog Analog Reference Voltage DC Power Supplies: Unipolar Bipolar 31. 32. Symbol VD+ VDVA+ VAVREF (Note 32) VAIN VAIN Min 4.5 -4.5 4.5 -4.5 2.5 AGND -VREF Typ 5.0 -5.0 5.0 -5.0 4.5 - Max VA+ -5.5 5.5 -5.5 (VA+)-0.5 VREF VREF Unit V V V V V V V All voltages with respect to ground. The CS5101A and CS5102A can accept input voltages up to the analog supplies (VA+ and VA-). They will produce an output of all 1s for input above VREF and all 0s for inputs below AGND in unipolar mode, and -VREF in bipolar mode, with binary coding (CODE = low). DS45F6 13 CS5101A CS5102A ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to ground.) Parameter DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature (Note 34) (AIN and VREF pins) (Note 33) Symbol VD+ VDVA+ VAIIN VINA VIND TA Tstg Min -0.3 0.3 -0.3 0.3 (VA-) - 0.3 -0.3 -55 -65 Typ - Max 6.0 -6.0 6.0 -6.0 ±10 (VA+) + 0.3 (VA+) + 0.3 125 150 Unit V V V V mA V V °C °C Notes: 33. In addition, VD+ must not be greater than (VA+) + 0.3 V. 34. Transient currents of up to 100 mA will not cause SCR latch-up WARNING: Operation beyond these limits may result in permanent damage to the device. 14 DS45F6 CS5101A CS5102A 2. OVERVIEW As shown in Figure 3, their other terminals are capable of being connected to AGND, VREF, or AIN (1 or 2). When the device is not calibrating or converting, all capacitors are tied to AIN. Switch S1 is closed and the charge on the array, tracks the input signal. When the conversion command is issued, switch S1 opens. This traps the charge on the comparator side of the capacitor array and creates a floating node at the comparator's input. The conversion algorithm operates on this fixed charge, and the signal at the analog input pin is ignored. In effect, the entire DAC capacitor array serves as analog memory during conversion much like the hold capacitor in a sample/hold amplifier. The conversion consists of manipulating the free plates of the capacitor array to VREF and AGND to form a capacitive divider. Since the charge at the floating node remains fixed, the voltage at that point depends on the proportion of capacitance tied to VREF versus AGND. The successive approximation algorithm is used to find the proportion of capacitance, which when connected to the reference will drive the voltage at the floating node to zero. That binary fraction of capacitance represents the converter's digital output. The CS5101A and CS5102A are 2-channel, 16-bit A/D converters. The devices include an inherent sample/hold and an on-chip analog switch for 2channel operation. Both channels can thus be sampled and converted at rates up to 50 kSps each (CS5101A) or 10 kSps each (CS5102A). Alternatively, each of the devices can be operated as a single channel ADC operating at 100 kSps (CS5101A) or 20 kSps (CS5102A). Both the CS5101A and CS5102A can be configured to accept either unipolar or bipolar input ranges, and data is output serially in either binary or 2's complement coding. The devices can be configured in 3 different output modes, as well as an internal, synchronous loopback mode. The CS5101A and CS5102A provide coarse charge/fine charge control, to allow accurate tracking of high-slew signals. 3. THEORY OF OPERATION The CS5101A and CS5102A implement the successive approximation algorithm using a charge redistribution architecture. Instead of the traditional resistor network, the DAC is an array of binaryweighted capacitors. All capacitors in the array share a common node at the comparator's input. A IN Fine + VREF C o arse Fine C C /2 C /4 C /3 2 ,7 6 8 C /3 2 ,7 6 8 S1 + AGND C o a rse Fine Bit 15 MSB Bit 14 Bit 13 Bit 0 LSB Dum m y + + - C to t C o a rse = C + C /2 + C /4 + C /8 + ... C /3 2 ,7 68 Figure 3. Coarse Charge Input Buffers & Charge Redistribution DAC DS45F6 15 CS5101A CS5102A 3.1 Calibration tion scheme. Each bit capacitor shown in Figure 3 actually consists of several capacitors in parallel which can be manipulated to adjust the overall bit weight. An on-chip microcontroller precisely adjusts each capacitor with a resolution of 18 bits. The CS5101A and CS5102A should be reset upon power-up, thus initiating a calibration cycle. The device then stores its calibration coefficients in onchip SRAM. When the CS5101A and CS5102A are in power-down mode (SLEEP low), they retain the calibration coefficients in memory, and need not be recalibrated when normal operation is resumed. The ability of the CS5101A or the CS5102A to convert accurately to 16-bits clearly depends on the accuracy of its comparator and DAC. Each device utilizes an “auto-zeroing” scheme to null errors introduced by the comparator. All offsets are stored on the capacitor array while in the track mode and are effectively subtracted from the input signal when a conversion is initiated. Auto-zeroing enhances power supply rejection at frequencies well below the conversion rate. To achieve 16-bit accuracy from the DAC, the CS5101A and CS5102A use a novel self-calibra- 16 DS45F6 CS5101A CS5102A 4. FUNCTIONAL DESCRIPTION Monolithic design and inherent sampling architecture make the CS5101A and CS5102A extremely easy to use. to provide the bulk of the charge on the capacitor array (coarse-charge), thereby reducing the current load on the external analog circuitry. Coarsecharge is internally initiated for 6 clock cycles at the end of every conversion. The buffer amplifier is then bypassed, and the capacitor array is directly connected to the input. This is referred to as finecharge, during which the charge on the array is allowed to accurately settle to the input voltage (see Figure 12). With a full-scale input step, the coarse-charge input buffer of the CS5101A will charge the capacitor array within 1% in 650 ns. The converter timing allows 6 clock cycles for coarse charge settling time. When the CS5101A switches to fine-charge mode, its slew rate is somewhat reduced. In fine-charge, the CS5101A can slew at 2 V/µs in unipolar mode. In bipolar mode, only half the capacitor array is connected to the analog input, so the CS5101A can slew at 4V/µs. With a full-scale input step, the coarse-charge input buffer of the CS5102A will charge the capacitor array within 1% in 3.75 µs. The converter timing allows 6 clock cycles for coarse charge settling time. When in fine-charge mode, the CS5102A can slew at 0.4 V/µs in unipolar mode; and at 0.8 V/µs in bipolar mode. Acquisition of fast slewing signals can be hastened if the voltage change occurs during or immediately following the conversion cycle. For instance, in multiple channel applications (using either the device's internal channel selector or an external MUX), channel selection should occur while the CS5101A or the CS5102A is converting. Multiplexer switching and settling time is thereby removed from the overall throughput equation. If the input signal changes drastically during the acquisition period (such as changing the signal source), the device should be in coarse-charge for an adequate period following the change. The CS5101A and CS5102A can be forced into coarsecharge by bringing CRS/FIN high. The buffer amplifier is engaged when CRS/FIN is high, and may be switched in any number of times during tracking. If CRS/FIN is held low, the CS5101A and CS5102A will only coarse-charge for the first 6 clock cycles following a conversion, and will stay in 17 4.1 Initiating Conversions A falling transition on the HOLD pin places the input in the hold mode and initiates a conversion cycle. The charge is trapped on the capacitor array the instant HOLD goes low. The device will complete conversion of the sample within 66 master clock cycles, then automatically return to the track mode. After allowing a short time for acquisition, the device will be ready for another conversion. In contrast to systems with separate track-andholds and A/D converters, a sampling clock can simply be connected to the HOLD input. The duty cycle of this clock is not critical. The HOLD input is latched internally by the master clock, so it need only remain low for 1/fclk + 20 ns, but no longer than the minimum conversion time minus two master clocks or an additional conversion cycle will be initiated with inadequate time for acquisition. In Free Run mode, SCKMOD = OUTMOD = 0, the device will convert at a rate of CLKIN/80, and the HOLD input is ignored. As with any high-resolution A-to-D system, it is recommended that sampling is synchronized to the master system clock in order to minimize the effects of clock feed through. However, the CS5101A and CS5102A may be operated entirely asynchronous to the master clock if necessary. 4.2 Tracking the Input Upon completing a conversion cycle the CS5101A and CS5102A immediately return to the track mode. The CH1/2 pin directly controls the input switch, and therefore directly determines which channel will be tracked. Ideally, the CH1/2 pin should be switched during the conversion cycle, thereby nullifying the input mux switching time, and guaranteeing a stable input at the start of acquisition. If, however, the CH1/2 control is changed during the acquisition phase, adequate coarse charge and fine charge time must be allowed before initiating conversion. When the CS5101A or the CS5102A enters tracking mode, it uses an internal input buffer amplifier DS45F6 CS5101A CS5102A fine-charge until HOLD goes low. To get an accurate sample using the CS5101A, at least 750 ns of coarse-charge, followed by 1.125 µs of fine-charge is required before initiating a conversion. If coarse charge is not invoked, then up to 25 µs should be allowed after a step change input for proper acquisition. To get an accurate sample using the CS5102A, at least 3.75 µs of coarse-charge, folC L K IN M in: 750 ns* 3.75 µ s** M in : 1 .1 2 5 µ s* 5 .62 5 µ s** lowed by 5.625 µs of fine-charge is required before initiating a conversion (see Figure 4). If coarse charge is not invoked, then up to 125 µs should be allowed after a step change input for proper acquisition. The CRS/FIN pin must be low prior to HOLD becoming active and be held low during conversion. C R S /F IN 6 clk In te rn al S tatus TR K 1 or TR K2 C onv. C o arse 2 clk F in e C hg. C o arse Fine C hg. C on v. HOLD * A pplies to 5101A ** A pplies to 51 02A Figure 4. Coarse/Fine Charge Control 4.3 Master Clock 4.4 The CS5101A and CS5102A can operate either from an externally-supplied master clock, or from their own crystal oscillator (with a crystal). To enable the internal crystal oscillator, simply tie a crystal across the XOUT and CLKIN pins and add 2 capacitors and a resistor, as shown on the system connection diagram in Figure 9. Calibration and conversion times directly scale to the master clock frequency. The CS5101A can operate with clock or crystal frequencies up to 9.216 MHz (8.0 MHz in FRN mode). This allows maximum throughput of up to 50 kSps per channel in dual-channel operation, or 100 kSps in a singlechannel configuration. The CS5102A can operate with clock or crystal frequencies up to 2.0 MHz (1.6 MHz in FRN mode). This allows maximum throughput of up to 10 kSps per channel in dualchannel operation, or 20 kSps in a single channel configuration. For 16-bit performance a 1.6 MHz clock is recommended. This 1.6 MHz clock yields a maximum throughput of 20 kSps in a singlechannel configuration. Asynchronous Sampling Considerations When HOLD goes low, the analog sample is captured immediately. The HOLD signal is latched by the next falling edge of CLKIN, and conversion then starts on the subsequent rising edge. If HOLD is asynchronous to CLKIN, then there will be a 1.5CLKIN-cycle uncertainty as to when conversion starts. Considering the CS5101A with an 8 MHz CLKIN, with a 100 kHz HOLD signal, then this 1.5CLKIN uncertainty will result in a 1.5-CLKIN-period possible reduction in fine charge time for the next conversion. This reduced fine charge time will be less than the minimum specification. If the CLKIN frequency is increased slightly (for example, to 8.192 MHz) then sufficient fine charge time will always occur. The maximum frequency for CLKIN is specified at 9.216 MHz. It is recommended that for asynchronous operation at 100 kSps, CLKIN should be between 8.192 MHz and 9.216 MHz. 18 DS45F6 CS5101A CS5102A 4.5 Analog Input Range/Coding Format curs 0.5 LSB above -VREF and the last transition occurs 1.5 LSBs below +VREF. The CS5101A and CS5102A can output data in either 2's complement, or binary format. If the CODE pin is high, the output is in 2's complement format with a range of -32,768 to +32,767. If the CODE pin is low, the output is in binary format with a range of 0 to +65,535. See Table 1 for output coding. Two’s Complement 7FFF 7FFF 7FFE 0000 FFFF 8001 8000 8000 The reference voltage directly defines the input voltage range in both the unipolar and bipolar configurations. In the unipolar configuration (BP/UP low), the first code transition occurs 0.5 LSB above AGND, and the final code transition occurs 1.5 LSBs below VREF. In the bipolar configuration (BP/UP high), the first code transition ocOffset Binary FFFF FFFF FFFE 8000 7FFF 0001 0000 0000 Table 1. Output Coding Unipolar Input Voltage >(VREF-1.5 LSB) VREF-1.5 LSB (VREF/2)-0.5 LSB +0.5 LSB (VREF-1.5 LSB) VREF-1.5 LSB -0.5 LSB -VREF+0.5 LSB