CS5378-ISZR

CS5378 Low-power Single-channel Decimation Filter Features Description  Single-channel Digital Decimation Filter  Multiple On-chip FIR and IIR Coefficient Sets  Programmable Coefficients for Custom Filters  Synchronous Operation  Integrated PLL for Clock Generation  1.024 MHz, 2.048 MHz, or 4.096 MHz Input  Standard Clock or Manchester Input  Selectable Output Word Rate  4000, 2000, 1000, 500, 333, 250 SPS  200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS  Digital Gain and Offset Corrections  Test DAC Bit-stream Generator  Digital Sine Wave Output  Time Break Controller, General-purpose I/O  Microcontroller or EEPROM Configuration  Small-footprint, 28-pin SSOP Package  Low Power Consumption  16 mW at 500 SPS OWR  Flexible Power Supplies  I/O Interface and PLL: 3.3 V or 5.0 V  Digital Logic Core: 2.5 V, 3.3 V or 5.0 V The CS5378 is a multi-function digital filter utilizing a lowpower signal processing architecture to achieve efficient filtering for a delta-sigma-type modulator. By combining the CS537 8 with a CS33 01A/02A di fferential a mplifier and a CS5373A modulator + test DAC, a synchronous high-resolution, self- testing, sin gle-channel m easurement system can be designed quickly and easily. Digital filter coefficients for the CS5378 FIR and IIR filters are included on-chip for a sim ple setup, or they can be programmed for custom ap plications. Selectable digital filter decimation r atios p roduce ou tput wor d r ates fro m 4000 SPS to 1 SPS, resulting in measurement bandwidths ra nging fro m 16 00 Hz down to 400 mHz whe n using the on-chip coefficient sets. The CS5378 includes integrated peripherals to simplify system d esign: a low- jitter PL L for standard clo ck or Manchester inpu ts, offset and gain co rrections, a test DAC bit stream generator, a tim e break controller, and eight general-purpose I/O pins. ORDERING INFORMATION See page 86. VDDCORE VDDPLL VDDPAD DRDY MISO MOSI SCK SS:EECS I PLL, Clock Generation Serial Interface Decimation and Filtering Engine RESET SYNC MSYNC Time Break Controller TIMEB GNDPLL TBSDATA GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0 GNDCORE GPIO General Purpose I/O GNDPAD MFLAG MDATA http://www.cirrus.com MCLK Reset, Synchronization Test Bit Stream Controller Modulator Data Interface CLK Copyright  Cirrus Logic, Inc. 2010 (All Rights Reserved) 2&7 ‘10 DS639F3 CS5378 TABLE OF CONTENTS 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1. 1.2. 1.3. 1.4. Digital Filter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Integrated Peripheral Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 System Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Configuration Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 12 Specified Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3. System Design with CS5378. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PLL and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Data Collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Integrated peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.2. Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3. Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5. Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.2. Reset Self-Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.3. Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6. PLL and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1. 6.2. 6.3. 6.4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PLL Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Synchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Master Clock Jitter and Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 7. Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1. 7.2. 7.3. 7.4. 7.5. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 MSYNC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Digital Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Modulator Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Test Bit Stream Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 8. Configuration By EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1. 8.2. 8.3. 8.4. 8.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 EEPROM Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 EEPROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 EEPROM Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Example EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 9. Configuration By Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DS639F3 2 CS5378 9.1. 9.2. 9.3. 9.4. 9.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Microcontroller Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Microcontroller Serial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Microcontroller Configuration Commands . . . . . . . . . . . . . . . . . . . . . . .33 Example Microcontroller Configuration . . . . . . . . . . . . . . . . . . . . . . . . .35 10. Modulator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1. 10.2. 10.3. 10.4. 10.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Modulator Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Modulator Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Modulator Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Modulator Flag Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 11. Digital Filter Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.1. Filter Coefficient Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 11.2. Filter Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 12. SINC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.1. 12.2. 12.3. 12.4. SINC1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 SINC2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 SINC3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 SINC Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 13. FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13.1. 13.2. 13.3. 13.4. 13.5. FIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 FIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 On-Chip FIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Programmable FIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 FIR Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 14. IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.1. 14.2. 14.3. 14.4. 14.5. 14.6. 14.7. IIR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 IIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 IIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 IIR3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 On-Chip IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Programmable IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 IIR Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 15. Gain and Offset Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.1. Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 15.2. Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 15.3. Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 16. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 16.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 16.2. Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 16.3. Serial Data Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 17. Test Bit Stream Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17.1. 17.2. 17.3. 17.4. 17.5. 17.6. DS639F3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 TBS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 TBS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 TBS Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 TBS Sine Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 TBS Loopback Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3 CS5378 17.7. TBS Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 18. Time Break Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 18.1. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 18.2. Time Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 18.3. Time Break Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 19. General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19.1. 19.2. 19.3. 19.4. 19.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 GPIO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 GPIO Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 GPIO Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 20. Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.1. SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 20.2. Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 21. 22. 23. 24. 25. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Environmental, Manufacturing, & Handling Information . . . . . . . 86 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 LIST OF FIGURES Figure 1. CS5378 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Digital Filtering Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. FIR and IIR Coefficient Set Selection Word . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. MOSI Write Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. MISO Read Timing in SPI Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Serial Data Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing. . . . . . . . . . . . . . . . . . . . . 16 Figure 8. TBS Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Single-Channel System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10. Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11. Reset Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12. Clock Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. Synchronization Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. EEPROM Configuration Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15. EEPROM Serial Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16. 8 Kbyte EEPROM Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17. Serial Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 18. Microcontroller Serial Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 19. SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 20. Modulator Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 21. Digital Filter Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 22. FIR and IIR Coefficient Set Selection Word . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 23. SINC Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 24. SINC Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 25. FIR Filter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 26. FIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 27. FIR1 Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 28. FIR2 Linear Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DS639F3 4 CS5378 Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. FIR2 Minimum Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain and Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Data Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD Port Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Bit Stream Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Time Break Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Control Register SPICTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Command Register SPICMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Register SPIDAT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Register SPIDAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Configuration Register CONFIG. . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Configuration Register GPCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter Configuration Register FILTCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Correction Register GAIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset Correction Register OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Break Counter Register TIMEBRK . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Bit Stream Configuration Register TBSCFG. . . . . . . . . . . . . . . . . . . . . Test Bit Stream Gain Register TBSGAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . User Defined System Register SYSTEM1 . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Version ID Register VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Test Result Register SELFTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS5378 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 52 54 56 58 58 59 60 63 64 67 68 69 70 72 73 74 75 76 77 78 79 80 81 82 83 LIST OF TABLES Table 1. Microcontroller and EEPROM Configuration Commands . . . . . . . . . . . . . . . . . 9 Table 2. TBS Configurations Using On-Chip Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. SPI and Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. PLL and BOOT Mode Reset Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. PLL Mode Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. Maximum EEPROM Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7. EEPROM Boot Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8. Example EEPROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 9. Microcontroller Boot Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 10. Example Microcontroller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 11. SINC Filter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 12. SINC1 and SINC2 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 13. SINC3 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 14. FIR Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 15. SINC + FIR Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 16. Minimum Phase Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 16. IIR Filter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 17. IIR Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 18. TBS Configurations Using On-chip Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DS639F3 5 VDDCORE VDDPLL VDDPAD DRDY MISO MOSI SCK SS:EECS CS5378 PLL, Clock Generation CLK MCLK Reset, Synchronization RESET SYNC MSYNC Time Break Controller TIMEB Serial Interface Decimation and Filtering Engine Test Bit Stream Controller GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0 GNDCORE GNDPAD MFLAG MDATA GNDPLL GPIO General Purpose I/O Modulator Data Interface TBSDATA Figure 1. CS5378 Block Diagram 1. GENERAL DESCRIPTION The CS5378 is a single channel digital filter with integrated system peripherals. Figure 1 illustrates a simplified block diagram of the CS5378. 40, 25, 20, 10, 5, 1 SPS. • 1.1 Digital Filter Features Flexible digital filter configuration. (See Figure 2) - Cascaded SINC, FIR, and IIR filters with selectable output stage. • Single channel decimation filter for CS5373A ΔΣ modulator. - • Synchronous operation for simultaneous sampling in multi-sensor systems. Linear and minimum phase FIR low-pass filter coefficients included. - 3 Hz Butterworth IIR high-pass filter coefficients included. - FIR and IIR coefficients programmable to create a custom filter response. • Internal synchronization of digital filter phase to an external SYNC signal. Output word rates, including low bandwidth rates. - Standard output rates: 4000, 2000, 1000, 500, 333, 250 SPS. - Low bandwidth rates: 200, 125, 100, 50, DS639F3 • Digital gain correction to normalize sensor gain. • Digital offset correction and calibration. - Offset correction to remove measurement 6 CS5378 Modulator Input 512 kHz Sinc Filter 2 - 64000 FIR1 FIR2 4 Gain & DC Offset Corrections IIR1 st 2 1 Order IIR2 2 nd Order Output to High Speed Serial Interface Output Word Rate from 4000 SPS ~ 1 SPS Figure 2. Digital Filtering Stages DC offset. - • Calibration engine for automatic calculation of offset correction factor. 1.2 Integrated Peripheral Features • • Dedicated TB status bit in the output data stream. - Programmable output delay to match system group delay. 1.024 MHz, 2.048 MHz, 4.096 MHz standard clock or Manchester encoded input. • 8 General Purpose I/O (GPIO) pins for local hardware control. Synchronous operation for simultaneous sampling in multi-sensor systems. 1.3 System Level Features - • MCLK / MSYNC output signals to synchronize external components. Flexible configuration options. - Configuration 'on-the-fly' via microcontroller or system telemetry. - Fixed configuration via stand-alone boot EEPROM. High speed serial data output. - Asynchronous operation to 4 MHz for direct connection to system telemetry. - Internal 8-deep data FIFO for flexible output timing. • - Low jitter PLL to generate local clocks. - • Time break controller to record system timing information. Selectable 24-bit data only or 32-bit status+data output. • • Low power consumption. - 16 mW at 500 SPS OWR. - 100 μW standby mode. Flexible power supply configurations. Digital test bit stream signal generator suitable for CS5373A ΔΣ test DAC. - Separate digital logic core, telemetry I/O, and PLL power supplies. - - Telemetry I/O and PLL interfaces operate Sine wave output mode for testing total harmonic distortion. DS639F3 7 CS5378 - from 3.3 V or 5 V. • Digital logic core operates from 2.5 V, 3.3 V or 5 V. Small 28-pin SSOP package. Configuration commands written through the serial interface. (See Table 1) - - Standardized microcontroller interface using SPI™ registers. (See Table 3) - Commands write digital filter registers and FIR / IIR filter coefficients. - Digital filter registers set hardware configuration options. Total footprint 8 mm x 10 mm plus three bypass capacitors. • 1.4 Configuration Interface • EEPROM boot sets a fixed operational configuration. Configuration from microcontroller or standalone boot EEPROM. - Microcontroller boot permits reconfiguration during operation. DS639F3 8 CS5378 Microcontroller Boot Configuration Commands Name CMD 24-bit DAT1 24-bit DAT2 24-bit Description NOP 000000 - - WRITE DF REGISTER 000001 REG DATA Write Digital Filter Register READ DF REGISTER 000002 REG [DATA] - Read Digital Filter Register WRITE FIR COEFFICIENTS 000003 NUM FIR1 (FIR COEF) NUM FIR2 (FIR COEF) Write Custom FIR Coefficients WRITE IIR COEFFICIENTS 000004 a11 b11 a22 b21 b10 a21 b20 b22 Write Custom IIR Coefficients WRITE ROM COEFFICIENTS 000005 COEF SEL - Use On-Chip Coefficients NOP 000006 - - No Operation NOP 000007 - - No Operation FILTER START 000008 - - Start Digital Filter Operation FILTER STOP 000009 - - Stop Digital Filter Operation No Operation EEPROM Boot Configuration Commands Name CMD 8-bit DATA 24-bit Description NOP 00 - WRITE DF REGISTER 01 REG DATA WRITE FIR COEFFICIENTS 02 NUM FIR1 NUM FIR2 (FIR COEF) Write Custom FIR Coefficients WRITE IIR COEFFICIENTS 03 a11 b10 b11 a21 a22 b20 b21 b22 Write Custom IIR Coefficients WRITE ROM COEFFICIENTS 04 COEF SEL NOP 05 - No Operation NOP 06 - No Operation FILTER START 07 - Start Digital Filter Operation No Operation Write Digital Filter Register Use On-Chip Coefficients [DATA] indicates data word returned from digital filter. (DATA) indicates multiple words of this type are to be written. Table 1. Microcontroller and EEPROM Configuration Commands DS639F3 9 CS5378 Bits 23:20 19:16 15:12 11:8 7:4 3:0 Selection 0000 0000 IIR2 IIR1 FIR2 FIR1 Bits 15:12 IIR2 Coefficients Bits 11:8 IIR1 Coefficients Bits 3:0 FIR1 Coefficients 0000 3 Hz @ 2000 SPS 0000 3 Hz @ 2000 SPS 0000 Linear Phase 0001 3 Hz @ 1000 SPS 0001 3 Hz @ 1000 SPS 0001 Minimum Phase 0010 3 Hz @ 500 SPS 0010 3 Hz @ 500 SPS 0011 3 Hz @ 333 SPS 0011 3 Hz @ 333 SPS Bits 7:4 FIR2 Coefficients 0100 3 Hz @ 250 SPS 0100 3 Hz @ 250 SPS 0000 Linear Phase 0001 Minimum Phase Figure 3. FIR and IIR Coefficient Set Selection Word Test Bit Stream Characteristic Equation: (Signal Freq) * (# TBS Data) * (Interpolation + 1) = Output Rate Example: (31.25 Hz) * (1024) * (0x07 + 1) = 256 kHz Signal Frequency (TBSDATA) Output Rate (TBSCLK) Output Rate Selection (RATE) Interpolation Selection (INTP) 10.00 Hz 256 kHz 0x4 0x18 10.00 Hz 512 kHz 0x5 0x31 25.00 Hz 256 kHz 0x4 0x09 25.00 Hz 512 kHz 0x5 0x13 31.25 Hz 256 kHz 0x4 0x07 31.25 Hz 512 kHz 0x5 0x0F 50.00 Hz 256 kHz 0x4 0x04 50.00 Hz 512 kHz 0x5 0x09 125.00 Hz 256 kHz 0x4 0x01 125.00 Hz 512 kHz 0x5 0x03 Table 2. TBS Configurations Using On-Chip Data DS639F3 10 CS5378 SPI Registers Addr. Type # Bits SPICTRL Name 00 - 02 R/W 8, 8, 8 SPI Control Description SPICMD 03 - 05 R/W 8, 8, 8 SPI Command SPIDAT1 06 - 08 R/W 8, 8, 8 SPI Data 1 SPIDAT2 09 - 0B R/W 8, 8, 8 SPI Data 2 Addr. Type # Bits Digital Filter Registers Name CONFIG RESERVED GPCFG RESERVED Description 00 R/W 24 Hardware Configuration 01-0D R/W 24 Reserved 0E R/W 24 GPIO[7:0] Direction, Pull-up Enable, and Data 0F-1F R/W 24 Reserved FILTCFG 20 R/W 24 Digital Filter Configuration GAIN 21 R/W 24 Gain Correction 22-24 R/W 24 Reserved 25 R/W 24 Offset Correction RESERVED OFFSET RESERVED 26-28 R/W 24 Reserved TIMEBRK 29 R/W 24 Time Break Delay TBSCFG 2A R/W 24 Test Bit Stream Configuration TBSGAIN 2B R/W 24 Test Bit Stream Gain SYSTEM1 2C R/W 24 User Defined System Register 1 SYSTEM2 2D R/W 24 User Defined System Register 2 VERSION 2E R/W 24 Hardware Version ID SELFTEST 2F R/W 24 Self-Test Result Code Table 3. SPI and Digital Filter Registers PLL[2:0] Mode Selection on Reset BOOT Mode Selection on Reset 111 32.768 MHz clock input (PLL bypass). 1 EEPROM boot 110 1.024 MHz clock input. 0 Microcontroller boot 101 2.048 MHz clock input. 100 4.096 MHz clock input. 011 32.768 MHz clock input (PLL bypass). 010 1.024 MHz Manchester input. 001 2.048 MHz Manchester input. 000 4.096 MHz Manchester input. Configuration Note: States of the PLL[2:0] and BOOT pins are latched immediately after reset to select modes. These pins have a weak (~100 kΩ) pull-up resistor enabled by default. An external 10 kΩ pull-down is required to set a low condition. Table 4. PLL and BOOT Mode Reset Configurations DS639F3 11 CS5378 2. CHARACTERISTICS AND SPECIFICATIONS • Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions. • Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. • GND, GND1, GND2 = 0 V, all voltages with respect to 0 V. SPECIFIED OPERATING CONDITIONS Parameter Logic Core Power Supply Symbol Min Nom Max Unit VDDCORE 2.375 2.5 5.25 V VDDPLL 3.135 3.3 5.25 V VDDPAD 3.135 3.3 5.25 V TA -40 - 85 °C PLL Power Supply I/O Power Supply Ambient Operating Temperature Industrial (-IQ) ABSOLUTE MAXIMUM RATINGS Parameter DC Power Supplies Symbol (Note 1) Input Current, Power Supplies (Note 1) Output Current (Note 1) Digital Input Voltages Ambient Operating Temperature (Power Applied) Storage Temperature Range Max Units -0.3 -0.3 -0.3 6.0 6.0 6.0 V V V IIN - ±10 mA IIN - ±50 mA IOUT - ±25 mA PDN - 500 mW VIND -0.3 VDD+0.3 V -40 85 °C TSTG -65 150 °C Logic Core VDDCORE PLL VDDPLL I/O VDDPAD Input Current, Any Pin Except Supplies Power Dissipation Min TA 1. Transient currents up to 100 mA will not cause SCR latch-up. DS639F3 12 CS5378 THERMAL CHARACTERISTICS Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance (4-Layer PCB) Ambient Operating Temperature (Power Applied) Symbol Min Typ Max Unit TJ - - 135 °C - 50 -40 - Symbol Min Typ Max Unit VIH 0.6 * VDD - VDD V 0.0 - 0.8 V ΘJA TA °C +85 /W °C DIGITAL CHARACTERISTICS Parameter High-Level Input Drive Voltage Low-Level Input Drive Voltage VIL High-Level Output Drive Voltage Iout = -40 µA VOH VDD - 0.3 - VDD V Low-Level Output Drive Voltage Iout = +40 µA VOL 0.0 - 0.3 V tRISE Rise Times, Digital Inputs Fall Times, Digital Inputs Rise Times, Digital Outputs Fall Times, Digital Outputs Input Leakage Current (Note 2) 3-State Leakage Current Digital Input Capacitance Digital Output Pin Capacitance - - 100 ns tFALL - - 100 ns tRISE - - 100 ns tFALL - - 100 ns IIN - ± 10 1 µA IOZ - - ± 0 µA1 CIN - 9 - pF COUT - 9 - pF ± Notes: 2. Maximum leakage for pins with pull-up resistors (RESET, SS:EECS, GPIO, MOSI, SCK) is ±250 μA. t risein t riseout t fallin t fallout 0.902.6 * VDD V 4.6 V 0.90 * VDD V 0.100.7 * VDD 0.10 * 0.4 VDD V POWER CONSUMPTION Parameter Symbol Min Typ Max Unit PWR1 - 12 - mW PWR2 - 14 - mW PWR4 - 16 - mW PWR8 - 24 - mW PWRS - 100 - µW Operational Power Consumption 1.024 MHz Digital Filter Clock 2.048 MHz Digital Filter Clock 4.096 MHz Digital Filter Clock 8.192 MHz Digital Filter Clock Standby Power Consumption 32 kHz Digital Filter Clock, Filter Stopped DS639F3 13 CS5378 SWITCHING CHARACTERISTICS Serial Configuration Interface Timing (External Master) SSI SS:EECS MOSI MSB LSB MSB - 1 t1 t2 t3 t4 t5 t6 SCK SCLK Figure 4. MOSI Write Timing in SPI Slave Mode SS I SS:EECS t 10 MISO MSB MSB - 1 t7 SCK SCLK LSB t8 t9 Figure 5. MISO Read Timing in SPI Slave Mode Parameter Symbol Min Typ Max Unit SS:EECS Enable to Valid Latch Clock t1 60 - - ns Data Set-up Time Prior to SCK Rising t2 60 - - ns Data Hold Time After SCK Rising t3 120 - - ns SCK High Time t4 120 - - ns SCK Low Time t5 120 - - ns SCK Falling Prior to SS:EECS Disable t6 60 - - ns SCK Falling to New Data Bit t7 - - 60 ns SCK High Time t8 120 - - ns SCK Low Time t9 120 - - ns SS:EECS Rising to MISO Hi-Z t10 - - 150 ns MOSI Write Timing MISO Read Timing DS639F3 14 CS5378 SWITCHING CHARACTERISTICS Serial Data Interface Timing DRDY SCK t3 t4 MISO t1 t2 t5 Figure 6. Serial Data Read Timing Parameter Symbol Min Typ Max Unit DRDY Falling Edge to SCK Rising t1 60 - - ns SCK Falling to New Data Bit t2 - - 120 ns SCK High Time t3 120 - - ns SCK Low Time t4 120 - - ns Final SCK Falling to DRDY Rising t5 60 - - ns DS639F3 15 CS5378 SWITCHING CHARACTERISTICS CLK, SYNC, MCLK, MSYNC, and MDATA SYNC MCLK MSYNC tmsd tmsh tmsd Data1 MDATA Data2 Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge. fMCLK 2.048 MHz 1.024 MHz tmsd = TMCLK / 4 tmsd = 122 ns tmsd = 244 ns tmsh = TMCLK tmsh = 488 ns tmsh = 976 ns Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing Parameter Symbol Min Typ Max Unit CLK 32 32.768 33 MHz Master Clock Duty Cycle DTY 40 - 60 % Master Clock Rise Time tRISE - - 20 ns - - 20 ns JTR - - 300 ps SYNC -2 - 2 μs tmss 20 - - ns - - 75 ns tmsf 20 - - ns Master Clock Frequency (Note 3) Master Clock Fall Time tFALL Master Clock Jitter Synchronization after SYNC rising MSYNC Setup Time to MCLK rising MCLK rising to Valid MDATA MSYNC falling to MCLK rising (Note 4) tmdv Notes: 3. PLL bypass mode. The PLL generates a 32.768 MHz master clock when enabled. 4. Sampling synchronization between multiple CS5378 devices receiving identical SYNC signals. DS639F3 16 CS5378 SWITCHING CHARACTERISTICS Test Bit Stream (TBS) TBSDATA t1 t2 MCLK Note: Example timing shown for a 256 kHz output rate and no programmable delays. Figure 8. TBS Output Data Timing Parameter Symbol Min Typ Max Unit - 256 - kbps t1 60 - - ns t2 60 - - ns TBS Data Output Timing TBS Data Bit Rate TBS Data Rising to MCLK Rising Setup Time MCLK Rising to TBS Data Falling Hold Time (Note 5) 5. TBSDATA can be delayed from 0 to 63 full bit periods. The timing diagram shows no TBSDATA delay. DS639F3 17 CS5378 CS5373A Differential Sensor M U X CS3301A CS3302A AMP CS5378 ΔΣ Modulator μController or Configuration EEPROM Digital Filter System Telemetry Test DAC Figure 9. Single-Channel System Block Diagram 3. SYSTEM DESIGN WITH CS5378 Figure 9 illustrates a simplified block diagram of the CS5378 in a single channel measurement system. A differential sensor is connected through the CS3301A/02A differential amplifiers to the CS5373A ΔΣ modulator, where analog to digital conversion occurs. The modulator’s 1-bit output connects to the CS5378 MDATA input, where the oversampled ΔΣ data is decimated and filtered to 24-bit output samples at a programmed output rate. These output samples are buffered into an 8-deep data FIFO and then passed to the system telemetry. System self tests are performed by connecting the CS5378 test bit stream (TBS) generator to the CS5373A test DAC. Analog tests drive differential signals from the CS5373A test DAC into the multiplexed inputs of the CS3301A/02A amplifiers or directly to the differential sensor. Digital loopback tests internally connect the TBS digital output directly to the CS5378 modulator input. DS639F3 3.1 Power Supplies The system shown in Figure 9 typically operates from a ±2.5 V analog power supply and a 3.3 V digital power supply. The CS5378 logic core can be powered from 2.5 V to minimize power consumption, if required. 3.2 Reset Control System reset is required only for the CS5378 device, and is a standard active low signal that can be generated by a power supply monitor or microcontroller. Other system devices default to a powerdown state when the CS5378 is reset. 3.3 PLL and Clock Generation A PLL is included on the CS5378 to generate an internal 32.768 MHz master clock from a 1.024 MHz, 2.048 MHz, or 4.096 MHz standard clock or Manchester encoded input. Clock inputs for other system devices are driven by clock outputs from the CS5378. 18 CS5378 3.4 Synchronization 3.7 Data Collection Digital filter phase and analog sample timing of the ΔΣ modulator connected to the CS5378 are synchronized by a rising edge on the SYNC pin. If a synchronization signal is received identically by all CS5378 devices in a measurement network, synchronous sampling across the network is guaranteed. Data is collected from the CS5378 through the serial data interface. When data is available, serial transactions are automatically initiated to transfer 24-bit data or 32-bit status+data from the output FIFO to the system telemetry. The output FIFO has eight data locations to permit latency in data collection. 3.5 System Configuration 3.8 Integrated peripherals Through the serial configuration interface, filter coefficients and digital filter register settings can either be programmed by a microcontroller or automatically loaded from an external EEPROM after reset. System configuration is only required for the CS5378 device, as other devices are configured via the CS5378 General Purpose I/O pins. Test Bit Stream (TBS) Two registers in the digital filter, SYSTEM1 and SYSTEM2 (0x2C, 0x2D), are provided for user defined system information. These are general purpose registers that will hold any 24-bit data values written to them. 3.6 Digital Filter Operation After analog to digital conversion occurs in the modulator, the oversampled 1-bit ΔΣ data is read into the CS5378 through the MDATA pin. The digital filter then processes data through the enabled filter stages, decimating it to 24-bit words at a programmed output word rate. The final 24-bit samples are concatenated with 8-bit status words and placed into an output FIFO. DS639F3 A digital signal generator built into the CS5378 produces a 1-bit ΔΣ sine wave. This digital test bit stream is connected to the CS5373A test DAC to create high quality analog test signals or internally looped back to the CS5378 MDATA input to test the digital filter and data collection circuitry. Time Break Timing information is recorded during data collection by strobing the TIMEB pin. A dedicated flag in the sample status bits, TB, is set high to indicate during which measurement the timing event occurred. General Purpose I/O (GPIO) Eight general purpose pins are available on the CS5378 for system control. Each pin can be set as input or output, high or low, with an internal pullup enabled or disabled. The CS3301A/02A and CS5373A devices in Figure 9 are configured by simple pin settings controlled through the CS5378 GPIO pins. 19 CS5378 VDDPAD GNDPAD 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 GNDCORE VDDCORE GNDPLL VDDPLL Figure 10. Power Supply Block Diagram 4. POWER SUPPLIES The CS5378 has three sets of power supply inputs. One set supplies power to the I/O pins of the device (VDDPAD), another supplies power to the logic core (VDDCORE) and the third supplies power to the PLL (VDDPLL). The I/O pin power supplies determine the maximum input and output voltages when interfacing to peripherals, the logic core power supply largely determines the power consumption of the CS5378 and the PLL power supply powers the internal PLL circuitry. 4.1 Pin Descriptions VDDPAD, GNDPAD - Pins 9, 10 Sets the interface voltage to a microcontroller, system telemetry, modulator, and test DAC. VDDPAD can be driven with voltages from 3.3 V to 5 V. VDDPLL, GNDPLL - Pins 15, 16 Sets the operational voltage of the internal CS5378 PLL circuitry. Can be driven with voltages from 3.3 V to 5 V. DS639F3 VDDCORE, GNDCORE - Pins 21, 22 Sets the operational voltage of the CS5378 logic core. VDDCORE can be driven with voltages from 2.5 V to 5 V. A 2.5 V supply will minimize total power consumption. 4.2 Bypass Capacitors Each power supply pin should be bypassed with parallel 1 μF and 0.01 μF caps, or by a single 0.1 μF cap, placed as close as possible to the CS5378. Bypass capacitors should be ceramic (X7R, C0G), tantalum, or other good quality dielectric type. 4.3 Power Consumption Power consumption of the CS5378 depends primarily on the power supply voltage of the logic core (VDDCORE) and the programmed digital filter clock rate. Digital filter clock rates are selected based on the required output word rate as explained in “Digital Filter Initialization” on page 38. 20 CS5378 RESET Self-Tests BOOT Pin 0 1 SELFTEST Register EEPROM Boot μController Boot Figure 11. Reset Control Block Diagram 5. RESET CONTROL The CS5378 reset signal is active low. When released, a series of self-tests are performed and the device either actively boots from an external EEPROM or enters an idle state waiting for microcontroller configuration. combined into the SELFTEST register (0x2F), with 0x0AAAAA indicating all passed. Self-tests require 60 ms to complete. 5.3 Boot Configurations Reset input, active low. The logic state of the BOOT pin after reset determines if the CS5378 actively reads configuration information from EEPROM or enters an idle state waiting for a microcontroller to write configuration commands. GPIO7:BOOT - Pin 28 EEPROM Boot Boot mode select, latched immediately following reset. Weak (~100 kΩ) internal pull-up defaults high, external 10 kΩ pull-down required to set low. When the BOOT pin is high after reset, the CS5378 actively reads data from an external serial EEPROM and then begins operation in the specified configuration. Configuration commands and data are encoded in the EEPROM as specified in the ‘Configuration By EEPROM’ section of this data sheet, starting on page 25. 5.1 Pin Descriptions RESET - Pin 18 BOOT Reset Mode 1 EEPROM boot 0 Microcontroller boot 5.2 Reset Self-Tests Microcontroller Boot After RESET is released but before booting, a series of digital filter self-tests are run. Results are Self-Test Type Pass Code Fail Code Program ROM 0x00000A 0x00000F Data ROM 0x0000A0 0x0000F0 Program RAM 0x000A00 0x000F00 Data RAM 0x00A000 0x00F000 Execution Unit 0x0A0000 0x0F0000 DS639F3 When the BOOT pin is low after reset, the CS5378 enters an idle state waiting for a microcontroller to write configuration commands and initialize filter operation. Configuration commands and data are written as specified in the ‘Configuration By Microcontroller’ section of this data sheet, starting on page 30. 21 CS5378 CLK PLL 32.768 MHz Internal Clocks Clock Divider and MCLK Generator PLL[2:0] MCLK Output DSPCFG Register Figure 12. Clock Generation Block Diagram 6. PLL AND CLOCK GENERATION The CS5378 requires a 32.768 MHz master clock, which can be supplied directly or from an internal phase locked loop. This master clock is used to generate an internal digital filter clock and an external modulator clock. The internal PLL will lock to standard clock or Manchester encoded input signals. The input type and input frequency are selected by the reset state of the PLL mode select pins. 6.1 Pin Descriptions CLK - Pin 17 Clock or PLL input, standard clock or Manchester. GPIO[4:6]:PLL[0:2] - Pins 5, 6, 7 PLL mode select, latched immediately after reset. Weak (~100 kΩ) internal pull-ups default high, external 10 kΩ pull-downs required to set low. 6.2 PLL Mode Select The CS5378 PLL operational mode and frequency are selected immediately after reset based on the state of the PLL[0:2] pins. On the rising edge of the reset signal, the digital high or low state of the PLL[0:2] pins is latched and used to program the clock input type and frequency. A weak internal pull-up resistor (~100 kΩ) will hold the PLL mode select pins high by default. To force the pin low on reset, an external 10 kΩ pulldown resistor should be connected. Once the pin state is latched following reset, the GPIO[4:6] pins function without affecting PLL operation. 6.3 Synchronous Clocking To guarantee synchronous measurements throughout a sensor network, a system clock should be distributed to arrive at all nodes in phase. The distributed system clock can either be the full 32.768 MHz master clock, or the CS5378 PLL can create a synchronous 32.768 MHz clock from a slower clock. To ensure the generated clock remains synchronous with the network, the CS5378 PLL uses a phase/frequency detector architecture. PLL[2:0] PLL Mode 111 32.768 MHz clock input (PLL bypass). 110 1.024 MHz clock input. 101 2.048 MHz clock input. 100 4.096 MHz clock input. 011 32.768 MHz clock input (PLL bypass). 010 1.024 MHz Manchester input. 001 2.048 MHz Manchester input. 000 4.096 MHz Manchester input. Table 5. PLL Mode Selections DS639F3 22 CS5378 6.4 Master Clock Jitter and Skew Care must be taken to minimize jitter and skew on the distributed system clock as both parameters affect measurement performance. DS639F3 Jitter on the input clock causes jitter in the generated modulator clock, resulting in sample timing errors and increased noise. Skew between input clocks from node to node creates a sample timing offset, resulting in systematic measurement errors in a reconstructed signal. 23 CS5378 0 SYNC 1 MSYNC Generator Digital Filter 0 1 MSYNC Output MSEN Test Bit Stream TSYNC Figure 13. Synchronization Block Diagram 7. SYNCHRONIZATION The CS5378 has a dedicated SYNC input that aligns the internal digital filter phase and generates an external signal for synchronizing modulator analog sampling. By providing simultaneous rising edges to the SYNC pins of multiple CS5378 devices, synchronous sampling across a network can be guaranteed. phase. Filter convolutions restart, and the next output word is available one full sample period later. 7.1 Pin Description 7.4 SYNC - Pin 19 The external MSYNC signal phase aligns modulator analog sampling when connected to the CS5373A MSYNC input. This ensures synchronous analog sampling relative to MCLK. Synchronization input, rising edge triggered. 7.2 MSYNC Generation The SYNC signal rising edge is used to generate a retimed synchronization signal, MSYNC. The MSYNC signal reinitializes internal digital filter phase and is driven onto the MSYNC output pin to phase align modulator analog sampling. The MSEN bit in the digital filter CONFIG register (0x00) enables MSYNC generation. See “Modulator Interface” on page 36 for more information about MSYNC. 7.3 Digital Filter Synchronization The internal MSYNC signal resets the digital filter state machine to establish a known digital filter DS639F3 Repetitive synchronization is supported when SYNC events occur at exactly the selected output rate. In this case, re-synchronization will occur at the start of a convolution cycle when the digital filter state machine is already reset. Modulator Synchronization Repetitive synchronization of the modulators is supported when SYNC events occur at exactly the selected output rate. In this case, re-synchronization always occurs at the start of analog sampling. 7.5 Test Bit Stream Synchronization When the test bit stream generator is enabled, an MSYNC signal can reset the internal data pointer. This restarts the test bit stream from the first data point to establish a known output signal phase. The TSYNC bit in the digital filter TBSCFG register (0x2A) enables synchronization of the test bit stream by MSYNC. When TSYNC is disabled, the test bit stream phase is not affected by MSYNC. 24 CS5378 VD SS:EECS SCK CS5378 MISO MOSI 27 1 24 6 25 2 26 5 CS 3 8 7 WP VCC HOLD SCK AT25640 SO SI 4 GND Figure 14. EEPROM Configuration Block Diagram 8. CONFIGURATION BY EEPROM After reset, the CS5378 reads the state of the GPIO7:BOOT pin to determine a source for configuration commands. If BOOT is high, the CS5378 initiates serial transactions to read configuration information from an external EEPROM. 8.1 Pin Descriptions Pins required for EEPROM boot are listed here, other serial pins are inactive. SCK - Pin 24 Serial clock output, nominally 1.024 MHz. MISO - Pin 25 Serial data input pin. Valid on rising edge of SCK, transition on falling edge. MOSI - Pin 26 Serial data output pin. Valid on rising edge of SCK, transition on falling edge. SS:EECS - Pin 27 EEPROM chip select output, active low. to read configuration commands and data. 8-bit SPI opcodes and 16-bit addresses are combined to read back 8-bit configuration commands and 24-bit configuration data. System design should include a connection to the configuration EEPROM for in-circuit reprogramming. The CS5378 serial pins tri-state when inactive to support external connections to the serial bus. 8.3 EEPROM Organization The boot EEPROM holds the 8-bit commands and 24-bit data required to initialize the CS5378 into an operational state. Configuration information starts at memory location 0x10, with addresses 0x00 to 0x0F free for use as manufacturing header information. The first serial transaction reads a 1-byte command from memory location 0x10 and then, depending on the command type, reads multiple 3-byte data words to complete the command. Command and data reads continue until the ‘Filter Start’ command is recognized. 8.2 EEPROM Hardware Interface When booting from EEPROM the CS5378 actively performs serial transactions, as shown in Figure 15, DS639F3 25 CS5378 Instruction Read Opcode Address 0x03 Definition ADDR[15:0] Read data beginning at the address given in ADDR. Serial Read from EEPROM 2 BYTE ADDR READ CMD 0x03 MOSI ADDR ADDR DATA1 DATA2 DATA3 MISO 1 BYTE / 3 BYTE DATA SS:EECS Cycle 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SCK MOSI MISO MSB X SS:EECS Figure 15. EEPROM Serial Read Transactions DS639F3 26 CS5378 Write DF Register - 0x01 0000h 0010h Mfg Header 8-bit Command N x 24-bit Data 8-bit Command N x 24-bit Data 1FFFh EEPROM Manufacturing Information EEPROM Command and Data Values This EEPROM command writes a data value to the specified digital filter register. Digital filter registers control hardware peripherals and filtering functions. See “Digital Filter Registers” on page 71 for the bit definitions of the digital filter registers. Sample Command: Write digital filter register 0x00 with data value 0x060431. Then write 0x20 with data 0x000240. ... 01 00 00 00 06 04 31 Figure 16. 8 Kbyte EEPROM Memory Organization 01 00 00 20 00 02 40 Write FIR Coefficients - 0x02 The maximum number of bytes that will be written for a single configuration is less than 2 KByte (16 Kbit), including command overhead: Memory Requirement Digital Filter Registers (12) FIR Coefficients (255+255) IIR Coefficients (3+5) ‘Filter Start’ Command Total Bytes Bytes 84 1537 25 1 1647 This EEPROM command writes custom coefficients for the FIR1 and FIR2 filters. The first two data words set the number of FIR1 and FIR2 coefficients to be written. The remaining data words are the concatenated FIR1 and FIR2 coefficients. A maximum of 255 coefficients can be written for each FIR filter, though the available digital filter computation cycles will limit their practical size. See “FIR Filter” on page 44 for more information about FIR filter coefficients. Sample Command: Write FIR1 coefficients 0x00022E, 0x000771 then FIR2 coefficients 0xFFFFB9, 0xFFFE8D. Table 6. Maximum EEPROM Configuration 02 00 00 02 00 00 02 00 02 2E 00 07 71 FF FF B9 FF FE 8D Supported serial configuration EEPROMs are SPI mode 0 (0,0) compatible, 16-bit addresses, 8bit data, larger than 2 KByte (16 KBit). ATMEL AT25640, AT25128, or similar serial EEPROMs are recommended. 8.4 EEPROM Configuration Commands A summary of available EEPROM commands is shown in Table 7. DS639F3 Write IIR Coefficients - 0x03 This EEPROM command writes custom coefficients for the two stage IIR filter. The IIR architecture and number of coefficients is fixed, so eight data words containing coefficient values always immediately follow the command byte. The IIR coefficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. See “IIR Filter” on page 52 for more information about IIR filter coefficients. 27 CS5378 Sample Command: Sample Command: Write IIR1 coefficients 0x84BC9D, 0x7DA1B1, 0x825E4F, and IIR2 coefficients 0x83694F, 0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5104. Select IIR1 and IIR2 3 Hz @ 500 SPS low-cut coefficients, with FIR1 and FIR2 linear phase highcut coefficients. Data word 0x002200. 03 04 00 22 00 84 BC 9D 7D A1 B1 82 5E 4F 83 69 4F Filter Start - 0x07 3C AD 5F 3E 51 04 83 5D F8 3E 51 04 This EEPROM command initializes and starts the digital filter. Measurement data becomes available one full sample period after this command is issued. No data words are required for this EEPROM command. Write ROM Coefficients - 0x04 This EEPROM command selects the on-chip coefficients for the FIR1, FIR2, IIR 1st order, and IIR 2nd order filters for use by the digital filter. One data word is required to select which internal coefficient sets to use. See “Filter Coefficient Selection” on page 38 for information about selecting on-chip FIR and IIR coefficient sets. Name CMD 8-bit Sample Command: 07 DATA 24-bit Description NOP 00 - WRITE DF REGISTER 01 REG DATA No Operation WRITE FIR COEFFICIENTS 02 NUM FIR1 NUM FIR2 (FIR COEF) Write Custom FIR Coefficients WRITE IIR COEFFICIENTS 03 a11 b10 b11 a21 a22 b20 b21 b22 Write Custom IIR Coefficients WRITE ROM COEFFICIENTS 04 COEF SEL NOP 05 - No Operation NOP 06 - No Operation FILTER START 07 - Start Digital Filter Operation Write Digital Filter Register Use On-Chip Coefficients (DATA) indicates multiple words of this type are to be written. Table 7. EEPROM Boot Configuration Commands DS639F3 28 CS5378 8.5 Example EEPROM Configuration Table 8 shows an example EEPROM file for a minimal CS5378 configuration. Addr Data Description 00 00 01 00 22 40 02 00 23 01 03 00 24 00 04 00 25 00 05 00 26 2A 06 00 27 07 07 00 28 40 08 00 29 40 Mfg header Addr Data 21 02 09 00 2A 01 0A 00 2B 00 0B 00 2C 00 0C 00 2D 2B 0D 00 2E 04 0E 00 2F B0 0F 00 30 00 10 04 31 07 11 00 12 22 13 00 14 01 15 00 16 00 17 00 18 06 19 04 1A 31 1B 01 1C 00 1D 00 1E 20 1F 00 Write ROM Coefficients Description Write TBSCFG Register Write TBSGAIN Register Filter Start Write CONFIG Register Write FILTCFG Register Table 8. Example EEPROM File DS639F3 29 CS5378 Digital Filter Command Interpreter SPI™ Registers Serial Pin Logic SS:EECS SCK MOSI MISO Figure 17. Serial Interface Block Diagram 9. CONFIGURATION BY MICROCONTROLLER After reset, the CS5378 reads the state of the GPIO7:BOOT pin to determine a source for configuration commands. If BOOT is low, the CS5378 receives configuration commands from a microcontroller. 9.1 Pin Descriptions Pins required for microcontroller boot are listed here, other serial pins are inactive. SS:EECS - Pin 27 Slave select input pin, active low. Serial chip select input from a microcontroller. 9.2 Microcontroller Hardware Interface When booting from a microcontroller the CS5378 receives configuration commands and configuration data through serial transactions, as shown in Figure 18. 8-bit SPI opcodes and 8-bit addresses are combined to read and write 24-bit configuration commands and data. Microcontroller serial transactions require toggling the SS:EECS pin as the CS5378 chip select and writing a serial clock to the SCK input. Serial data is input to the CS5378 on the MOSI pin, and output on the MISO pin. MOSI - Pin 26 9.3 Microcontroller Serial Transactions Serial data input pin. Valid on rising edge of SCK, transition on falling edge. Microcontroller configuration commands are written to the digital filter through SPI registers. A 24bit command and two 24-bit data words can be written to the SPI registers in any single serial transaction. Some commands require additional data words through additional serial transactions to complete. MISO - Pin 25 Serial data output pin. Valid on rising edge of SCK, transition on falling edge. Open drain output requiring a 10 kΩ pull-up resistor. SCK - Pin 24 Serial clock input pin. Serial clock input from microcontroller, maximum 4.096 MHz. DS639F3 9.3.1 SPI opcodes A microcontroller communicates with the CS5378 serial port using standard 8-bit SPI opcodes and an 8-bit address. The standard SPI ‘Read’ and ‘Write’ opcodes are listed in Figure 18. 30 CS5378 Instruction Opcode Address Definition Write 0x02 ADDR[7:0] Write SPI registers beginning at the address in ADDR. Read 0x03 ADDR[7:0] Read SPI registers beginning at the address in ADDR. Microcontroller Write to SPI Registers SS:EECS MISO 0x02 ADDR Data1 Data2 DataN Data2 DataN MOSI Microcontroller Read from SPI Registers SS:EECS 0x03 MISO ADDR Data1 MOSI Cycle 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SCK MOSI MISO MSB X SS:EECS Figure 18. Microcontroller Serial Transactions DS639F3 31 CS5378 9.3.2 SPI registers The SPI registers are shown in Figure 19 and are 24-bit registers mapped into an 8-bit register space as high, mid, and low bytes. See “SPI Registers” on page 66 for the bit definitions of the SPI registers. MOSI: 03 01 00 MISO: xx xx 12 5-byte read of SPIDAT1 MOSI: 03 06 00 00 00 MISO: xx xx 12 34 56 9.3.3 Serial transactions A serial transaction to the SPI registers starts with an SPI opcode, followed by an address, and then some number of data bytes written or read starting at that address. Typical serial write transactions require sending groups of 5, 8, or 11 total bytes to the SPICMD or SPIDAT1 registers: 9.3.4 Multiple serial transactions Some configuration commands require multiple serial transactions to complete. There must be a small delay between transactions for the CS5378 to process the incoming data. Two methods can be used to ensure the CS5378 is ready to receive the next configuration command. 1) Delay a fixed 1 ms period to guarantee enough time for the command to be completed. 5-byte write to SPICMD 02 03 12 34 56 2) Verify the status of the E2DREQ bit by reading the SPICTRL register. When low, the CS5378 is ready for the next command. 5-byte write to SPIDAT1 02 06 12 34 56 8-byte write to SPICMD, SPIDAT1 9.3.5 Polling E2DREQ One transaction type that can always be performed no matter the delay from the previous configuration command is reading E2DREQ in the mid-byte of the SPICTRL register. A 3-byte read transaction. 02 03 12 34 56 AB CD EF 8-byte write to SPIDAT1, SPIDAT2 02 06 12 34 56 AB CD EF 11-byte write to SPICMD, SPIDAT1, SPIDAT2 MOSI: 03 01 00 02 03 12 34 56 AB CD EF 65 43 21 Typical serial read transactions require groups of 3 or 5 bytes, split between writing into MOSI and reading from MISO. 3-byte read of mid-byte of SPICTRL Name MISO: xx xx 01 EXP] YSUM(n) = Y(n) + YSUM(n-1) Offset Correction = YSUM >> EXP Once the EXP bits are written, the ORCAL bit in the FILTCFG register is set to enable offset calibration. When enabled, an updated offset correction value is automatically written to the OFFSET register. When the offset calibration algorithm is fully settled, the ORCAL bit should be cleared to maintain the final value in the OFFSET register. 57 CS5378 System Telemetry CS5378 DRDY SCK MISO Data Ready Clock Out Data In Figure 33. Serial Data Interface Block Diagram 16. SERIAL DATA INTERFACE Once digital filtering is complete, each 24-bit output sample is combined with an 8-bit status byte. These data words are written to an 8-deep FIFO buffer and then transmitted to the communications channel through a high speed serial data interface. MISO - Pin 25 Serial data output. 16.2 Serial Data Format Data ready output signal, active low. Open drain output requiring an external pull-up resistor. Serial data transactions transfer either 24-bit data words or 32-bit status+data words, depending on the STAT bit in the CONFIG register. When transmitting status information, each 8-bit status byte has an MFLAG bit, a time break bit, and a FIFO overflow bit encoded as shown in Figure 34. SCK - Pin 24 MFLAG Bit - MFLAG Serial clock input. The MFLAG bit is set in the status byte when an signal is received on the MFLAG pin. When re- 16.1 Pin Descriptions DRDY - Pin 23 31 MFLAG 31 -30 0 - Modulator Ok 1 - Modulator Error -29 23 Status -28 0 Data -27 TB 26 -25 0 - No Time Break 1 - Time Break W 24 0 - FIFO Ok 1 - FIFO Overflow Figure 34. 32-bit Serial Data Format DS639F3 58 CS5378 ceived, the MFLAG bit is set in the next output word. See “Modulator Interface” on page 36 for more information about MFLAG. Time Break Bit - TB The time break bit marks a timing reference based on a rising edge into the TIMEB pin. After a programmed delay, the TB bit in the status byte is set for one output sample. The TIMEBRK digital filter register (0x29) programs the sample delay for the TB bit output. See “Time Break Controller” on page 63 for more information about time break. FIFO Overflow Bit - W The FIFO overflow bit indicates an error condition in the serial data FIFO, and is set if new digital filter data overwrites a FIFO location containing data which has not yet been sent. The W bit is sticky, meaning it persists indefinitely once set. Clearing the W bit requires sending the ‘Filter Stop’ and ‘Filter Start’ configuration commands to reinitialize the data FIFO. Conversion Data Word The lower 24-bits of the serial data word is the conversion sample for the specified channel. Conversion data is 24-bit two’s complement format. 16.3 Serial Data Transactions The CS5378 automatically initiates serial data transactions whenever data becomes available in the output FIFO by driving the DRDY pin low. Once a serial data transaction is initiated, serial clocks received into SCK cause data to be output to MISO, as shown in Figure 35. When all available data is read from the serial data FIFO, DRDY is released. DRDY SCK MISO MSB LSB Figure 35. SD Port Transaction DS639F3 59 CS5378 Digital Filter Data Bus 24-bit TBSGAIN Register 24-bit Digital ΔΣ Modulator 1-bit TBSDATA Figure 36. Test Bit Stream Generator Block Diagram 17. TEST BIT STREAM GENERATOR The CS5378 test bit stream (TBS) generator creates sine wave ΔΣ bit stream data to drive an external test DAC. The TBS digital output can also be internally connected to the MDATA inputs for loopback testing of the digital filter. 17.3 TBS Configuration 17.1 Pin Descriptions Interpolation Factor - INTP[7:0] TBSDATA - Pin 8 MCLK - Pin 11 Selects how many times the interpolator uses a data point when generating the output bit stream. Interpolation is zero based and represents one greater than the programmed register value. Test bit stream clock output. Output Rate - RATE[2:0] Test bit stream 1-bit ΔΣ data output. 17.2 TBS Architecture The test bit stream generator consists of a data interpolator and a digital ΔΣ modulator. It receives periodic 24-bit data from the digital filter to create a 1-bit ΔΣ data output on the TBSDATA pin. The TBS input data from the digital filter is scaled by the TBSGAIN register (0x2B). Maximum stable amplitude is 0x04FFFF, with 0x04B000 approximately full scale for the CS5373A test DAC. The full scale 1-bit ΔΣ output from the TBS generator is defined as 25% minimum and 75% maximum one’s density. DS639F3 Configuration options for the TBS generator are set through the TBSCFG register (0x2A). Gain scaling of the TBS generator output is set by the TBSGAIN register (0x2B). Selects the TBSDATA output rate. Synchronization - TSYNC Enables synchronization of the TBS output phase to the MSYNC signal. Loopback - LOOP Enables digital loopback from the TBS output to the MDATA inputs. Run - RUN Enables the test bit stream generator. 60 CS5378 Test Bit Stream Characteristic Equation: (Signal Freq) * (# TBS Data) * (Interpolation + 1) = Output Rate Example: (31.25 Hz) * (1024) * (0x07 + 1) = 256 kHz Signal Frequency (TBSDATA) Output Rate (TBSCLK) Output Rate Selection (RATE) Interpolation Selection (INTP) 10.00 Hz 256 kHz 0x4 0x18 10.00 Hz 512 kHz 0x5 0x31 25.00 Hz 256 kHz 0x4 0x09 25.00 Hz 512 kHz 0x5 0x13 31.25 Hz 256 kHz 0x4 0x07 31.25 Hz 512 kHz 0x5 0x0F 50.00 Hz 256 kHz 0x4 0x04 50.00 Hz 512 kHz 0x5 0x09 125.00 Hz 256 kHz 0x4 0x01 125.00 Hz 512 kHz 0x5 0x03 Table 18. TBS Configurations Using On-chip Data Data Delay - DDLY[5:0] 17.5 TBS Sine Wave Output Programs full period delays for TBSDATA, up to a maximum of 63 bits. The TBS generator uses data from digital filter memory to create a sine wave test signal that can drive a test DAC. Sine wave frequency and output data rate are calculated as shown by the characteristic equation of Table 18. Gain - TBSGAIN[23:0] Scales the amplitude of the sine wave output. Maximum 0x04FFFF, nominal 0x04B000. 17.4 TBS Data Source An on-chip 24-bit 1024 point digital sine wave is stored on the CS5378 which will produce the test signal frequencies listed in Table 18. Additional discrete test frequencies and output rates can be programmed by varying the interpolation factor and output rate. DS639F3 The sine wave maximum ΔΣ one’s density output from the TBS generator is set by the TBSGAIN register. TBSGAIN can be programmed up to a maximum of 0x04FFFF, with the TBS generator unstable for higher amplitudes. For the CS5373A test DAC, a gain value of 0x04B000 produces an approximately full scale sine wave output (5 Vpp differential). 61 CS5378 17.6 TBS Loopback Testing Included as part of the CS5378 test bit stream generator is a feedback path to the digital filter MDATA input. This loopback mode provides a fully digital signal path to test the TBS generator, digital filter, and data collection interface. Digital loopback testing expects 512 kHz ΔΣ data into the MDATA input. A mismatch of the TBS generator full scale output and the MDATA full scale input results in an amplitude mismatch when testing in loopback mode. The TBS generator outputs a 75% maximum one’s density, while the MDATA inputs expect an 86% maximum one’s density from a ΔΣ modulator, re- DS639F3 sulting in a measured full scale error of approximately -3.6 dB. 17.7 TBS Synchronization When the TSYNC bit is set in the TBSCFG register, the MSYNC signal resets the sine wave data pointer and phase aligns the TBS signal output. Once the digital filter is settled, all CS5378 devices receiving the SYNC signal will have identical TBS signal phase. See “Synchronization” on page 24 for more information about the SYNC and MSYNC signals. If TSYNC is clear, MSYNC has no effect on the TBS data pointer and no change in the TBS output phase will occur during synchronization. 62 CS5378 TIMEBRK Delay Counter TIMEB TB Flag in Serial Data Status Byte Figure 37. Time Break Block Diagram 18. TIME BREAK CONTROLLER A time break signal is used to mark timing events that occur during measurement. An external signal sets a flag in the status byte of an output sample to mark when the external event occurred. A rising edge input to the TIMEB pin causes the TB timing reference flag to be set in the serial data status byte. When set, the TB flag appears for only one output sample in the status byte. The TB flag output can be delayed by programming a sample delay value into the TIMEBRK digital filter register. 18.1 Pin Description TIMEB - Pin 20 Time break input pin, rising edge triggered. 18.2 Time Break Operation An externally generated timing reference signal applied to the TIMEB pin initiates an internal sample counter. After a number of output samples have passed, programmed in the TIMEBRK digital filter register (0x29), the TB flag is set in the status byte of the serial data output word. The TB flag is automatically cleared for subsequent data words, and appears for only one output sample. DS639F3 18.3 Time Break Delay The TIMEBRK register (0x29) sets a sample delay between a received rising edge on the TIMEB pin and writing the TB flag into the serial data status byte. The programmable sample counter can compensate for group delay through the digital filters. When the proper group delay value is programmed into the TIMEBRK register, the TB flag will be set in the status byte of the measurement sample taken when the timing reference signal was received. 18.3.1 Step Input and Group Delay A simple method to empirically measure the step response and group delay of a CS5378 measurement channel is to use the time break signal as both a timing reference input and an analog step input. When a rising edge is received on the TIMEB pin with no delay programmed into the TIMEBRK register, the TB flag is set in the next serial data status byte. The same rising edge can act as a step input to the analog channel, propagating through the digital filter to appear as a rising edge in the measurement data. By comparing the timing of the TB status flag output and the rising edge in the measurement data, the measurement channel group delay can be determined. 63 CS5378 GP_PULL Pull Up Logic R GPIO GP_DATA GP_DIR Figure 38. GPIO Block Diagram 19. GENERAL PURPOSE I/O The General Purpose I/O (GPIO) block provides 8 general purpose pins to interface with external hardware. GP_PULL bits enable/disable the internal pull-up resistor, and GP_DATA bits set the output data value. After reset, GPIO pins default as inputs with pull-up resistors enabled. 19.1 Pin Descriptions GPIO[3:0] - Pins 4 - 1 19.4 GPIO Input Mode Standard GPIO pins also used to select the PLL mode after reset. Internal pull-ups default high, 10 kΩ external pull-downs required to set low. When reading a value from the GP_DATA bits, the returned data reports the current state of the pins. If a pin is externally driven high it reads a logical 1, if externally driven low it reads a logical 0. When a GPIO pin is used as an input, the pull-up resistor should be disabled to save power if it isn’t required. GPIO7:BOOT - Pin 28 19.5 GPIO Output Mode Standard GPIO pin also used to select boot mode after reset. Internal pull-up defaults high, 10 kΩ external pull-down required to set low. When a GPIO pin is programmed as an output with a data value of 0, the pin is driven low and the internal pull-up resistor is automatically disabled. When programmed as an output with a data value of 1, the pin is driven high and the pull-up resistor is inconsequential. Standard GPIO pins. GPIO[6:4]:PLL[2:0] - Pins 7 - 5 19.2 GPIO Architecture Each GPIO pin can be configured as input or output, high or low, with a weak (~100 kΩ) internal pull-up resistor enabled or disabled. Figure 38 shows the structure of a bi-directional GPIO pin. 19.3 GPIO Registers GPIO pin settings are programmed in the GPCFG register. GP_DIR bits set the input/output mode, DS639F3 Any GPIO pin can be used as an open-drain output by setting the data value to 0, enabling the pull-up, and using the GP_DIR direction bits to control the pin value. This open-drain output configuration uses the internal pull-up resistor to hold the pin high when GP_DIR is set as an input, and drives the pin low when GP_DIR is set as an output. 64 CS5378 19.5.1 GPIO Reads in Output Mode When reading GPIO pins the GP_DATA register value always reports the current state of the pins, so a value written in output mode does not necessarily read back the same value. If a pin in output mode is written as a logical 1, the CS5378 attempts to drive the pin high. If an external device forces the pin DS639F3 low, the read value reflects the pin state and returns a logical 0. Similarly, if an output pin is written as a logical 0 but forced high externally, the read value reflects the pin state and returns a logical 1. In both cases the CS5378 is in contention with the external device resulting in increased power consumption. 65 CS5378 20. REGISTER SUMMARY 20.1 SPI Registers The CS5378 SPI registers interface the serial port to the digital filter. Name Addr. Type # Bits SPICTRLH 00 R/W 8 SPI Control Register, High Byte SPICTRLM 01 R/W 8 SPI Control Register, Middle Byte SPICTRLL 02 R/W 8 SPI Control Register, Low Byte SPICMDH 03 R/W 8 SPI Command, High Byte SPICMDM 04 R/W 8 SPI Command, Middle Byte SPICMDL 05 R/W 8 SPI Command, Low Byte SPIDAT1H 06 R/W 8 SPI Data 1, High Byte SPIDAT1M 07 R/W 8 SPI Data 1, Middle Byte SPIDAT1L 08 R/W 8 SPI Data 1, Low Byte SPIDAT2H 09 R/W 8 SPI Data 2, High Byte SPIDAT2M 0A R/W 8 SPI Data 2, Middle Byte SPIDAT2L 0B R/W 8 SPI Data 2, Low Byte DS639F3 Description 66 CS5378 20.1.1 SPICTRL : 0x00, 0x01, 0x02 Figure 39. SPI Control Register SPICTRL (MSB) 23 22 21 20 19 18 17 16 -- -- -- -- -- -- -- -- R/W R/W1 R/W R/W R/W R/W R/W R/W 0 0 0 0 1 0 1 1 15 14 13 12 11 10 9 8 SMODF -- -- EMOP SWEF -- -- E2DREQ R R/W R R R R/W R/W R/W 0 0 0 0 0 0 1 0 7 6 5 4 3 2 1 (LSB) 0 -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 0 0 0 0 15 SMODF SPI Address: 0x00 0x01 0x02 -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 -- DS639F3 reserved SPI mode fault flag 14:13 -- reserved 12 EMOP External master to SPI operation in progress flag 11 SWEF SPI write collision error flag 10:9 -- reserved 8 E2DREQ External master to digital filter request flag 7:0 -- reserved 67 CS5378 20.1.2 SPICMD : 0x03, 0x04, 0x05 Figure 40. SPI Command Register SPICMD (MSB) 23 22 21 20 19 18 17 16 SCMD23 SCMD22 SCMD21 SCMD20 SCMD19 SCMD18 SCMD17 SCMD16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SCMD15 SCMD14 SCMD13 SCMD12 SCMD11 SCMD10 SCMD9 SCMD8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SPI Address: 0x03 0x04 0x05 -- 7 6 5 4 3 2 1 (LSB) 0 SCMD7 SCMD6 SCMD5 SCMD4 SCMD3 SCMD2 SCMD1 SCMD0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 SCMD[23:16] DS639F3 SPI Command High 15:8 Byte SCMD[15:8] SPI Command Mid- 15:8 dle Byte SCMD[7:0] SPI Command Low Byte 68 CS5378 20.1.3 SPIDAT1 : 0x06, 0x07, 0x08 Figure 41. SPI Data Register SPIDAT1 (MSB) 23 22 21 20 19 18 17 16 SDAT23 SDAT22 SDAT21 SDAT20 SDAT19 SDAT18 SDAT17 SDAT16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SDAT15 SDAT14 SDAT13 SDAT12 SDAT11 SDAT10 SDAT9 SDAT8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SPI Address: 0x06 0x07 0x08 -- 7 6 5 4 3 2 1 (LSB) 0 SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 SDAT[23:16] SPI Data High Byte DS639F3 15:8 SDAT[15:8] SPI Data Middle Byte 15:8 SDAT[7:0] SPI Data Low Byte 69 CS5378 20.1.4 SPIDAT2 : 0x09, 0x0A, 0x0B Figure 42. SPI Data Register SPIDAT2 (MSB) 23 22 21 20 19 18 17 16 SDAT23 SDAT22 SDAT21 SDAT20 SDAT19 SDAT18 SDAT17 SDAT16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SDAT15 SDAT14 SDAT13 SDAT12 SDAT11 SDAT10 SDAT9 SDAT8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SPI Address: 0x09 0x0A 0x0B -- 7 6 5 4 3 2 1 (LSB) 0 SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 SDAT[23:16] SPI Data High Byte DS639F3 15:8 SDAT[15:8] SPI Data Middle Byte 15:8 SDAT[7:0] SPI Data Low Byte 70 CS5378 20.2 Digital Filter Registers The CS5378 digital filter registers control hardware peripherals and filtering functions. Name Addr. Type # Bits 00 R/W 24 Hardware Configuration 01-0D R/W 24 Reserved 0E R/W 24 GPIO[7:0] Direction, Pull-Up Enable, and Data 0F-1F R/W 24 Reserved FILTCFG 20 R/W 24 Digital Filter Configuration GAIN 21 R/W 24 Gain Correction 22-24 R/W 24 Reserved 25 R/W 24 Offset Correction RESERVED 26-28 R/W 24 Reserved TIMEBRK 29 R/W 24 Time Break Delay TBSCFG 2A R/W 24 Test Bit Stream Configuration TBSGAIN 2B R/W 24 Test Bit Stream Gain SYSTEM1 2C R/W 24 User Defined System Register 1 SYSTEM2 2D R/W 24 User Defined System Register 2 VERSION 2E R/W 24 Hardware Version ID SELFTEST 2F R/W 24 Self-Test Result Code CONFIG RESERVED GPCFG RESERVED RESERVED OFFSET DS639F3 Description 71 CS5378 20.2.1 CONFIG : 0x00 Figure 43. Hardware Configuration Register CONFIG (MSB)23 22 21 20 19 18 17 16 -- -- -- -- -- DFS2 DFS1 DFS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 0 1 15 14 13 12 11 10 9 8 -- -- -- -- -- MCKFS2 MCKFS1 MCKFS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 0 0 7 6 5 4 3 2 1 (LSB)0 STAT -- -- MCKEN MDIFS -- BOOT MSEN R/W R/W R/W R/W R/W R/W R R/W 0 0 0 0 0 0 0 1 DF Address: 0x00 -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:19 -- reserved 15:11 -- reserved 18:16 DFS [2:0] Digital filter frequency select 111: Reserved 110: 8.192 MHz 101: 4.096 MHz 100: 2.048 MHz 011: 1.024 MHz 010: 512 kHz 001: 256 kHz 000: 32 kHz 10:8 MCLK frequency select 5 111: reserved 110: reserved 4 101: 4.096 MHz 100: 2.048 MHz 011: 1.024 MHz 010: 512 kHz 3 001: reserved 000: reserved DS639F3 MCKFS [2:0] 7:6 STAT Serial Data Status Byte 1: Disabled (24-bit output) 0: Enabled (32-bit output) -- reserved MCKEN MCLK output enable 1: Enabled 0: Disabled MDIFS MDATA input frequency select 1: 256 kHz 0: 512 kHz 2 -- reserved 1 BOOT Boot source indicator 1: Booted from EEPROM 0: Booted from Micro 0 MSEN MSYNC enable 1: MSYNC generated 0: MSYNC remains low 72 CS5378 20.2.2 GPCFG : 0x0E Figure 44. GPIO Configuration Register GPCFG (MSB) 23 22 21 20 19 18 17 16 GP_DIR7 GP_DIR6 GP_DIR5 GP_DIR4 GP_DIR3 GP_DIR2 GP_DIR1 GP_DIR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 GP_PULL7 GP_PULL6 GP_PULL5 GP_PULL4 GP_PULL3 GP_PULL2 GP_PULL1 GP_PULL0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 (LSB) 0 GP_DATA7 GP_DATA6 GP_DATA5 GP_DATA4 GP_DATA3 GP_DATA2 GP_DATA1 GP_DATA0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 DF Address: 0x0E -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 GP_DIR [7:0] GPIO pin direction 1: Output 0: Input 15:8 GP_PULL GPIO pullup resistor [7:0] 1: Enabled 0: Disabled 7:0 GP_DATA GPIO data value [7:0] 1: VDD 0: GND Notes: GPIO[7] also used as BOOT mode select after reset GPIO[6:4] also used as PLL mode select after reset. DS639F3 73 CS5378 20.2.3 FILTCFG : 0x20 Figure 45. Filter Configuration Register FILTCFG (MSB) 23 22 21 20 19 18 17 16 -- -- -- EXP4 EXP3 EXP2 EXP1 EXP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 -- ORCAL USEOR USEGR -- FSEL2 FSEL1 FSEL0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 DEC3 DEC2 DEC1 DEC0 -- -- -- (LSB) 0 -- R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DF Address: 0x20 -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:21 -- reserved 20:16 EXP[4:0] OFFSET calibration exponent DS639F3 15 -- reserved 7:4 14 ORCAL Run OFFSET calibration 1: Enable 0: Disable 0111: 0110: 0101: 0100: 0011: 4000 SPS 2000 SPS 1000 SPS 500 SPS 333 SPS 13 USEOR Use OFFSET correction 1: Enable 0: Disable 0010: 0001: 0000: 1111: 1110: 250 SPS 200 SPS 125 SPS 100 SPS 50 SPS 12 USEGR Use GAIN correction 1: Enable 0: Disable 1101: 1100: 1011: 1010: 1001: 1000: 40 SPS 25 SPS 20 SPS 10 SPS 5 SPS 1 SPS 11 -- reserved 10:8 FSEL[2:0] Output filter stage select 111: reserved 110: reserved 101: IIR 3rd Order 100: IIR 2nd Order 011: IIR 1st Order 010: FIR2 Output 001: FIR1 Output 000: SINC Output 3:0 DEC[3:0] -- Decimation selection (Output word rate) reserved 74 CS5378 20.2.4 GAIN : 0x21 Figure 46. Gain Correction Register GAIN (MSB) 23 22 21 20 19 18 17 16 GAIN23 GAIN22 GAIN21 GAIN20 GAIN19 GAIN18 GAIN17 GAIN16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 GAIN15 GAIN14 GAIN13 GAIN12 GAIN11 GAIN10 GAIN9 GAIN8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 (LSB) 0 GAIN7 GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DF Address: 0x21 -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 GAIN[23:16] Gain Correction Upper Byte DS639F3 15:8 GAIN[15:8] Gain Correction Middle Byte 15:8 GAIN[7:0] Gain Correction Lower Byte 75 CS5378 20.2.5 OFFSET : 0x25 Figure 47. Offset Correction Register OFFSET (MSB) 23 22 21 20 19 18 17 16 OFST23 OFST22 OFST21 OFST20 OFST19 OFST18 OFST17 OFST16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 OFST15 OFST14 OFST13 OFST12 OFST11 OFST10 OFST9 OFST8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 (LSB) 0 OFST7 OFST6 OFST5 OFST4 OFST3 OFST2 OFST1 OFST0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DF Address: 0x25 -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 OFST[23:16] DS639F3 Offset Correction Upper Byte 15:8 OFST[15:8] Offset Correction Middle Byte 15:8 OFST[7:0] Offset Correction Lower Byte 76 CS5378 20.2.6 TIMEBRK : 0x29 Figure 48. Time Break Counter Register TIMEBRK (MSB) 23 22 21 20 19 18 17 16 TBRK23 TBRK22 TBRK21 TBRK20 TBRK19 TBRK18 TBRK17 TBRK16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 TBRK15 TBRK14 TBRK13 TBRK12 TBRK11 TBRK10 TBRK9 TBRK8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 (LSB) 0 TBRK7 TBRK6 TBRK5 TBRK4 TBRK3 TBRK2 TBRK1 TBRK0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DF Address: 0x29 -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 TBRK[23:16] Time Break Counter 15:8 Upper Byte DS639F3 TBRK[15:8] Time Break Counter Middle Byte 15:8 TBRK[7:0] Time Break Counter Lower Byte 77 CS5378 20.2.7 TBSCFG : 0x2A Figure 49. Test Bit Stream Configuration Register TBSCFG (MSB) 23 22 21 20 19 18 17 16 INTP7 INTP6 INTP5 INTP4 INTP3 INTP2 INTP1 INTP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 -- RATE2 RATE1 RATE0 TSYNC -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 (LSB) 0 LOOP RUN DDLY5 DDLY4 DDLY3 DDLY2 DDLY1 DDLY0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Interpolation factor 0xFF: 256 0xFE: 255 ... 0x01: 2 0x00: 1 (use once) 15 DF Address: 0x2A -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 INTP[7:0] DS639F3 -- reserved 7 LOOP Loopback TBSDATA output to MDATA inputs 1: Enabled 0: Disabled 14:12 RATE[2:0] TBSDATA and TBSCLK output rate. 111: 2.048 MHz 110: 1.024 MHz 101: 512 kHz 100: 256 kHz 011: 128 kHz 010: 64 kHz 001: 32 kHz 000: 4 kHz 6 RUN Run Test Bit Stream 1: Enabled 0: Disabled 11 TSYNC Synchronization 1: Sync enabled 0: No sync 5:0 DDLY[5:0] TBSDATA output delay 0x3F: 63 bits 0x3E: 62 bits ... 0x01: 1 bit 0x00: 0 bits ( no delay) 10:8 -- reserved 78 CS5378 20.2.8 TBSGAIN : 0x2B Figure 50. Test Bit Stream Gain Register TBSGAIN (MSB) 23 22 21 20 19 18 17 16 TGAIN23 TGAIN22 TGAIN21 TGAIN20 TGAIN19 TGAIN18 TGAIN17 TGAIN16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 TGAIN15 TGAIN14 TGAIN13 TGAIN12 TGAIN11 TGAIN10 TGAIN9 TGAIN8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 (LSB) 0 TGAIN7 TGAIN6 TGAIN5 TGAIN4 TGAIN3 TGAIN2 TGAIN1 TGAIN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DF Address: 0x2B -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 TGAIN[23:16] Test Bit Stream Gain 15:8 Upper Byte DS639F3 TGAIN[15:8] Test Bit Stream Gain Middle Byte 15:8 TGAIN[7:0] Test Bit Stream Gain Lower Byte 79 CS5378 20.2.9 SYSTEM1, SYSTEM2 : 0x2C, 0x2D Figure 51. User Defined System Register SYSTEM1 (MSB) 23 22 21 20 19 18 17 16 SYS23 SYS22 SYS21 SYS20 SYS19 SYS18 SYS17 SYS16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SYS15 SYS14 SYS13 SYS12 SYS11 SYS10 SYS9 SYS8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 (LSB) 0 SYS7 SYS6 SYS5 SYS4 SYS3 SYS2 SYS1 SYS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DF Address: 0x2C -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 SYS[23:16] DS639F3 System Register Upper Byte 15:8 SYS[15:8] System Register Middle Byte 15:8 SYS[7:0] System Register Lower Byte 80 CS5378 20.2.10 VERSION : 0x2E Figure 52. Hardware Version ID Register VERSION (MSB) 23 22 21 20 19 18 17 16 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0 R/W R/W R/W R/W R/W R/W R/W R/W 0 1 1 1 1 0 0 0 15 14 13 12 11 10 9 8 HW7 HW6 HW5 HW4 HW3 HW2 HW1 HW0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 0 7 6 5 4 3 2 1 (LSB) 0 ROM7 ROM6 ROM5 ROM4 ROM3 ROM2 ROM1 ROM0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 0 DF Address: 0x2E -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:16 TYPE [7:0] DS639F3 Chip Type 78 - CS5378 15:8 HW [7:0] Hardware Revision 01 - CS5378 Rev A 02 - CS5378 Rev B 7:4 ROM [7:0] ROM Version 01 - Ver 1.0 02 - Ver 2.0 81 CS5378 20.2.11 SELFTEST : 0x2F Figure 53. Self Test Result Register SELFTEST (MSB) 23 22 21 20 19 18 17 16 -- -- -- -- EU3 EU2 EU1 EU0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 0 1 0 15 14 13 12 11 10 9 8 DRAM3 DRAM2 DRAM1 DRAM0 PRAM3 PRAM2 PRAM1 PRAM0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 1 0 1 0 1 0 7 6 5 4 3 2 1 (LSB) 0 DROM3 DROM2 DROM1 DROM0 PROM3 PROM2 PROM1 PROM0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 1 0 1 0 1 0 DF Address: 0x2F -R W R/W Not defined; read as 0 Readable Writable Readable and Writable Bits in bottom rows are reset condition Bit definitions: 23:20 -- reserved 15:12 DRAM [3:0] Data RAM Test ‘A’: Pass ‘F’: Fail 7:4 DROM [3:0] Data ROM Test ‘A’: Pass ‘F’: Fail 19:16 EU [3:0] Execution Unit Test ‘A’: Pass ‘F’: Fail 11:8 Program RAM Test ‘A’: Pass ‘F’: Fail 3:0 PROM [3:0] Program ROM Test ‘A’: Pass ‘F’: Fail DS639F3 PRAM [3:0] 82 CS5378 21. PIN DESCRIPTION GPIO0 1 28 GPIO7:BOOT GPIO1 2 27 SS:EECS GPIO2 3 26 MOSI GPIO3 4 25 MISO GPIO4:PLL0 5 24 SCK GPIO5:PLL1 6 23 DRDY GPIO6:PLL2 7 22 GNDCORE TBSDATA 8 21 VDDCORE VDDPAD 9 20 TIMEB GNDPAD 10 19 SYNC MCLK 11 18 RESET MSYNC 12 17 CLK MDATA 13 16 GNDPLL MFLAG 14 15 VDDPLL Figure 54. CS5378 Pin Assignments Pin Name Pin Number Pin Type Pin Description GPIO[0:3] 1, 2, 3, 4 Input / Output General Purpose I/O. GPIO[4:6]:PLL[0:2] 5, 6, 7 Input / Output General Purpose I/O with PLL mode select. GPIO pins have weak (~100 kΩ) internal pull-ups. PLL mode selection latched immediately after reset. General Purpose Input / Output PLL[2:0] 111 GPIO7:BOOT 28 Input / Output 110 1.024 MHz clock input. 101 2.048 MHz clock input. 100 4.096 MHz clock input. 011 32.768 MHz clock input (PLL bypass). 010 1.024 MHz Manchester input. 001 2.048 MHz Manchester input. 000 4.096 MHz Manchester input. General Purpose I/O with boot mode select. GPIO pins have weak (~100 kΩ) internal pull-ups. Boot mode selection latched immediately after reset. BOOT DS639F3 Reset Mode 32.768 MHz clock input (PLL bypass). Reset Mode 1 EEPROM boot 0 Microcontroller boot 83 CS5378 Pin Name Pin Number Pin Type Pin Description TBSDATA 8 Output MCLK 11 Output Modulator clock output. MSYNC 12 Output Modulator sync output. MDATA 13 Input Modulator data input. MFLAG 14 Input Modulator flag input. CLK 17 Input Clock input. Test Bit Stream Test bit stream data output. Modulator Interface Telemetry Interface RESET 18 Input Reset, active low. SYNC 19 Input Sync input. TIMEB 20 Input Time break input. Serial Interface DRDY 23 Output Data ready, active low. SCK 24 Input / Output Serial clock. MISO 25 Input / Output Serial data, master in / slave out. MOSI 26 Input / Output Serial data, master out / slave in. SS:EECS 27 Input Slave select with EEPROM chip select, active low. VDDPAD, GNDPAD 9, 10 Supply Pin power supply. VDDPLL, GNDPLL 15, 16 Supply PLL power supply. VDDCORE, GNDCORE 21, 22 Supply Logic core power supply. Power Supplies DS639F3 84 CS5378 22.PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING N D E11 A2 E e b2 SIDE VIEW A ∝ A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4° MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.15 1.75 -10.20 7.80 5.30 0.65 0.90 4° NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8° 2,3 1 1 JEDEC #: MO-150 Controlling Dimension is Millimeters DS639F3 85 CS5378 23.ORDERING INFORMATION Model CS5378-ISZ (Lead Free) Temperature Package -40 to +85 °C 28-pin SSOP 24.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5378-ISZ (Lead Free) Peak Reflow Temp MSL Rating* Max Floor Life 260 °C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS639F3 86 CS5378 25.REVISION HISTORY Revision Date PP1 FEB 2004 Initial “Preliminary Product” release. F1 OCT 2005 Added lead-free device ordering information. Added MSL data. F2 SEP 2008 Rev B. Update Single-S part numbers. Remove TBS impulse mode. F3 OCT 2010 DS639F3 Changes Removed lead-containing device ordering information. 87 CS5378 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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I F THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OT HER AGENTS FROM ANY AND AL L LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. DS639F3 88