CS5464

CS5464 Three-channel, Single-phase Power/Energy IC Features & Description • Energy Linearity: ±0.1% of Reading over 1000:1 Dynamic Range • On-chip Functions: Voltage and Current Measurement Active, Reactive, and Apparent Power/Energy RMS Voltage and Current Calculations Current Fault and Voltage Sag Detection Calibration Phase Compensation Temperature Sensor Energy Pulse Outputs Description The CS5464 is a watt-hour meter on a chip. It measures line voltage and current and calculates active, reactive, apparent power, energy, power factor, and RMS voltage and current. There are two separate inputs to measure line, ground, and/or neutral current enabling the meter to detect tampering and to continue operating. An internal RMS voltage reference can be used if voltage measurement is disabled by tampering. Four ∆Σ analog-to-digital converters are used to measure voltage, two currents, and temperature. The CS5464 is designed to interface to a variety of voltage and current sensors. Additional features include system-level calibration, voltage sag and current fault detection, peak detection, phase compensation, and energy pulse outputs. ORDERING INFORMATION See Page 44. • • • • • • • • Meets Accuracy Spec for IEC, ANSI, & JIS Low Power Consumption Tamper Detection and Correction Ground-referenced Inputs with Single Supply On-chip 2.5 V Reference (25 ppm / °C typ.) Power Supply Monitor Function Three-wire Serial Interface to Microcontroller or E2PROM Power Supply Configurations GND: 0 V, VA+: +5 V, VD+: +3.3 V to +5 V http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) MAR ‘07 DS682F1 CS5464 TABLE OF CONTENTS 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Control Pins and Serial Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Analog Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Analog Inputs (All Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Analog Inputs (Current Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Analog Inputs (Voltage Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Master Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SDI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SDO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 E2PROM mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 E1, E2, and E3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. Signal Path Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 DC Offset and Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Low-Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 RMS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Power and Energy Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Peak Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Analog Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Voltage Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Current1 and Current2 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Power Fail Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 14 14 14 14 15 15 15 15 16 16 16 17 17 17 17 17 DS682F1 CS5464 5.1.4 Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5 Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.6 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 CPU Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Interrupt Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Energy Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. Setting Up the CS5464 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 CPU Clock Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Interrupt Pin Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Current Input Gain Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Cycle Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Energy Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 No Load Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 Energy Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Energy Pulse Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 Voltage Sag/Current Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 Epsilon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. Using the CS5464 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Tamper Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Register Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Page 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1.1 DC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1.2 AC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2 Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.1 AC Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2.2 DC Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 Calibration Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS682F1 17 17 17 17 17 17 17 17 18 19 19 19 19 19 19 19 19 20 20 20 20 21 21 22 22 22 22 23 23 24 28 28 28 33 38 39 39 39 39 39 40 40 40 40 3 CS5464 9.1.4 Temperature Sensor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.4.1 Temperature Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . 9.1.4.2 Temperature Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . 10. E2PROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 E2PROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 E2PROM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Which E2PROMs Can Be Used? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . 15. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 41 41 41 41 42 43 44 44 45 LIST OF FIGURES Figure 1. CS5464 Read and Write Timing Diagrams ................................................................. 12 Figure 2. Timing Diagram for E1, E2, and E3 .............................................................................. 13 Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements ............................................................ 14 Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements ............................................................ 14 Figure 5. Low-rate Calculations .................................................................................................. 16 Figure 6. Oscillator Connections................................................................................................. 17 Figure 7. Sag and Fault Detect................................................................................................... 21 Figure 8. Energy Channel Selection ........................................................................................... 22 Figure 9. Fixed RMS Voltage Selection...................................................................................... 22 Figure 10. Calibration Data Flow ................................................................................................ 39 Figure 11. System Calibration of Offset...................................................................................... 39 Figure 12. System Calibration of Gain........................................................................................ 40 Figure 13. Typical Interface of E2PROM to CS5464 .................................................................. 41 Figure 14. Typical Connection Diagram .................................................................................... 42 LIST OF TABLES Table 1. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2. Current Input Gain Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3. High-pass Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4. E2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5. E3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6. E1 / E2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7. E3 Pin with E1MODE enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 19 20 20 20 4 DS682F1 CS5464 1. OVERVIEW The CS5464 is a CMOS power measurement integrated circuit utilizing four ∆Σ analog-to-digital converters to measure line voltage, temperature, and current from up to two sources. It calculates active, reactive, and apparent power as well as RMS and peak voltage and current. It handles other system-related functions, such as pulse output conversion, voltage sag, current fault, voltage zero crossing, line frequency, and tamper detection. The CS5464 is optimized to interface to current transformers or shunt resistors for current measurement, and to a resistive divider or voltage transformer for voltage measurement. Two full-scale ranges are provided on the current inputs to accommodate both types of current sensors. The second current channel can be used for tamper detection or as a second current input. The CS5464’s three differential inputs have a common-mode input range from analog ground (AGND) to the positive analog supply (VA+). An additional analog input (PFMON) is provided to allow the application to determine when a power failure is in progress. By monitoring the unregulated power supply, the application can take any required action when a power loss occurs. An on-chip voltage reference (nominally 2.5 volts) is generated and provided at analog output, VREFOUT. This reference can be supplied to the chip by connecting it to the reference voltage input, VREFIN. Alternatively, an external voltage reference can be supplied to the reference input. Three digital outputs (E1, E2, E3) provide a variety of output signals and, depending on the mode selected, provide energy pulses, power failure indication, or other choices. The CS5464 includes a three-wire serial host interface to an external microcontroller or serial E2PROM. Signals include serial data input (SDI), serial data output (SDO), serial clock (SCLK), and optionally, a chip select (CS), which allows the CS5464 to share the SDO signal with other devices. A MODE input is used to control whether an E2PROM will be used instead of a host microcontroller. DS682F1 5 CS5464 2. PIN DESCRIPTION Crystal Out CPU Clock Output Positive Digital Supply Digital Ground Serial Clock Serial Data Ouput Chip Select Mode Select Differential Voltage Input Differential Voltage Input Voltage Reference Output Voltage Reference Input Factory Test Factory Test XOUT CPUCLK VD+ DGND SCLK SDO CS MODE VIN+ VINVREFOUT VREFIN TEST1 TEST2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 XIN SDI E2 E1 INT RESET E3 PFMON IIN1+ IIN1VA+ AGND IIN2+ IIN2Crystal In Serial Data Input Energy Output 2 Energy Output 1 Interrupt Reset Energy Output 3 Power Fail Monitor Differential Current Input Differential Current Input Positive Analog Supply Analog Ground Differential Current Input Differential Current Input Clock Generator Crystal Out Crystal In CPU Clock Output Serial Clock Serial Data Output Chip Select Mode Select Energy Outputs Reset Interrupt Serial Data Input 1,28 2 5 6 7 8 XOUT, XIN — Connect to an external quartz crystal. Alternatively, an external clock can be supplied to the XIN pin to provide the system clock for the device. CPUCLK - Logic-level output from crystal oscillator. Can be used to clock an external CPU. Control Pins and Serial Data I/O SCLK — Clocks serial data from the SDI pin and to the SDO pin when CS is low. SCLK is a Schmitt-trigger input when MODE is low and a driven output when MODE is high. SDO — Serial data output. Data is clocked out by SCLK. CS — An input that enables the serial interface when MODE is low and a driven output when MODE is high. MODE — High selects external E2PROM, Low selects external microcontroller. MODE includes a weak internal pull-down and therefore selects microcontroller mode if not connected. 22, 25, E3, E1, E2 — Primarily active-low energy pulse outputs. These can be programmed to output other conditions. 26 23 24 27 9,10 RESET — An active-low Schmitt-trigger input used to reset the chip. INT — Active-low output, indicates that an enabled condition has occurred. SDI — Serial data input. Data is clocked in by SCLK. Analog Inputs/Outputs Differential Voltage Inputs Differential Current Inputs Power Fail Monitor Voltage Reference Output Voltage Reference Input VIN+, VIN- — Differential analog inputs for the voltage channel. 20,19, IIN1+, IIN1-, IIN2+, IIN2- — Differential analog inputs for the current channels. 16,15 21 11 12 PFMON — Used to monitor the unregulated power supply via a resistive divider. If the PFMON voltage drops below its low limit, the low-supply detect (LSD) bit is set in the Status register. VREFOUT — The on-chip voltage reference output. Nominally 2.5 V, referenced to AGND. VREFIN — The voltage reference input. Can be connected to VREFOUT or external 2.5 V reference. Power Connections Positive Digital Supply Digital Ground Positive Analog Supply Analog Ground 3 4 18 17 13,14 VD+ — The positive digital supply. DGND — Digital ground. VA+ — The positive analog supply. AGND — Analog ground. Other Pins Test1, Test2 NC — Factory use only. Connect to AGND. 6 DS682F1 CS5464 3. CHARACTERISTICS & SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter Positive Digital Power Supply Positive Analog Power Supply Voltage Reference Specified Temperature Range Symbol VD+ VA+ VREFIN TA Min 3.135 4.75 -40 Typ 5.0 5.0 2.5 Max 5.25 5.25 +85 Unit V V V °C ANALOG CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V. DCLK = 4.096 MHz. Parameter Accuracy Active Power (Note 1) All Gain Ranges Input Range 0.1% - 100% All Gain Ranges Input Range 0.1% - 100% All Gain Ranges Input Range 1.0% - 100% Input Range 0.1% - 1.0% All Gain Ranges Input Range 1.0% - 100% Input Range 0.1% - 1.0% All Gain Ranges Input Range 5% - 100% Symbol PActive QAvg PF Min Typ Max Unit 80 -0.25 80 30 - ±0.1 ±0.2 ±0.2 ±0.27 ±0.1 ±0.17 ±0.1 500 100 94 -115 27 4.0 ±0.4 VA+ 22.5 4.5 - % % % % % % % % dB V mVP-P mVP-P dB dB pF kΩ µVrms µVrms µV/°C % Reactive Power (Note 1 and 2) Power Factor (Note 1 and 2) Current RMS (Note 1) IRMS VRMS CMRR Voltage RMS (Note 1) Analog Inputs (All Inputs) Common Mode Rejection Common Mode + Signal Analog Inputs (Current Inputs) Differential Input Range [(IIN+) – (IIN-)] (DC, 50, 60 Hz) (Gain = 10) (Gain = 50) (Gain = 50) (50, 60 Hz) IIN THD IC EII Total Harmonic Distortion Crosstalk from Voltage Input at Full Scale Input Capacitance Effective Input Impedance Noise (Referred to Input) Offset Drift (Without the High-pass Filter) Gain Error (Gain = 10) (Gain = 50) NI OD GE (Note 3) Notes: 1. Applies when the HPF option is enabled. 2. Applies when the line frequency is equal to the product of the output word rate (OWR) and the value of Epsilon. DS682F1 7 CS5464 ANALOG CHARACTERISTICS (Continued) Parameter Analog Inputs (Voltage Inputs) Differential Input Range Symbol [(VIN+) – (VIN-)] Min 65 2 48 68 60 2.3 - Typ 500 75 -70 2.0 16.0 ±3.0 ±5 1.5 3.5 2.3 25 15 7 10 55 75 65 2.45 2.55 Max 140 - Unit mVP-P dB dB pF MΩ µVrms µV/°C % °C mA mA mA mW mW mW uW dB dB dB V V VIN THD IC EII NV OD GE T Total Harmonic Distortion Crosstalk from Current Inputs at Full Scale (50, 60 Hz) Input Capacitance All Gain Ranges Effective Input Impedance Noise (Referred to Input) Offset Drift (Without the High-pass Filter) Gain Error Temperature Temperature Accuracy Power Supplies Power Supply Currents (Active State) (Note 3) 33 20 2.7 IA+ ID+ (VA+ = VD+ = 5 V) ID+ (VA+ = 5 V, VD+ = 3.3 V) PSCA PSCD PSCD Power Consumption (Note 4) Active State (VA+ = VD+ = 5 V) Active State (VA+ = 5 V, VD+ = 3.3 V) Stand-by State Sleep State PC Power Supply Rejection Ratio (50, 60 Hz) (Note 5) Voltage Current (Gain = 50x) Current (Gain = 10x) (Note 6) (Note 7) PSRR PMLO PMHI PFMON Low-voltage Trigger Threshold PFMON High-voltage Power-on Trip Point Notes: 3. Applies before system calibration. 4. All outputs unloaded. All inputs CMOS level. 5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to AGND. The CS5464 is then commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is (in dB): 150 PSRR = 20 ⋅ log --------V eq 6. When voltage level on PFMON is sagging, and LSD bit = 0, the voltage at which LSD is set to 1. 7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at which the LSD bit can be permanently reset back to 0. 8 DS682F1 CS5464 VOLTAGE REFERENCE Parameter Reference Output Output Voltage Temperature Coefficient Load Regulation Reference Input Input Voltage Range Input Capacitance Input CVF Current VREFIN +2.4 +2.5 4 100 +2.6 V pF nA (Note 8) (Note 9) Symbol VREFOUT TCVREF ∆ VR Min +2.4 - Typ +2.5 25 6 Max +2.6 60 10 Unit V ppm/°C mV Notes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements the following formula is used to calculate the VREFOUT temperature coefficient:. TCVREF = MAX MIN) AVG AMAX 1 - TAMIN 6 9. Specified at maximum recommended output of 1 µA, source or sink. DS682F1 ( 9 ( ( ( (VREFOUT - VREFOUT VREFOUT (T ( 1.0 x 10 CS5464 DIGITAL CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V. DCLK = 4.096 MHz. Parameter Symbol Master Clock Characteristics Master Clock Frequency Internal Gate Oscillator (Note 11) DCLK Master Clock Duty Cycle CPUCLK Duty Cycle (Note 12 and 13) Filter Characteristics Phase Compensation Range (60 Hz, OWR = 4000 Hz) Input Sampling Rate DCLK = MCLK/K Digital Filter Output Word Rate (Both channels) OWR High-pass Filter Corner Frequency -3 dB Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR Channel-to-channel Time-shift Error (Note 15) Input/Output Characteristics High-level Input Voltage All Pins Except XIN and SCLK and RESET XIN SCLK and RESET Min 2.5 40 40 -5.4 25 Typ 4.096 DCLK/8 DCLK/1024 0.5 1.0 Max 20 60 60 +5.4 100 Unit MHz % % ° Hz Hz Hz %FS µs VIH 0.6 VD+ (VD+) – 0.5 0.8 VD+ (VD+) - 1.0 - ±1 5 0.8 1.5 0.2 VD+ 0.48 0.3 0.2 VD+ 0.4 0.4 ±10 ±10 - V V V V V V V V V V V V µA µA pF Low-level Input Voltage (VD = 5 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIL Low-level Input Voltage (VD = 3.3 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIL VOH VOL Iin IOZ Cout High-level Output Voltage Low-level Output Voltage Iout = +5 mA Iout = -5 mA (VD = +5V) Iout = -2.5 mA (VD = +3.3V) Input Leakage Current 3-state Leakage Current Digital Output Pin Capacitance (Note 16) Notes: 10. All measurements performed under static conditions. 11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz. 12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification. 13. The frequency of CPUCLK is equal to MCLK. 14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the full-scale signal applied to the input. 15. Configuration register (Config) bits PC[6:0] are set to “0000000”. 16. The MODE pin is pulled low by an internal resistor. 10 DS682F1 CS5464 SWITCHING CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V. Logic Levels: Logic 0 = 0 V, Logic 1 = VD+. Parameter Rise Times (Note 17) Fall Times (Note 17) Start-up Oscillator Start-up Time Serial Port Timing Serial Clock Frequency Serial Clock SDI Timing CS Falling to SCLK Rising Data Set-up Time Prior to SCLK Rising Data Hold Time After SCLK Rising SDO Timing CS Falling to SDO Driving SCLK Falling to New Data Bit (hold time) CS Rising to SDO Hi-Z E2PROM mode Timing Serial Clock MODE setup time to RESET Rising RESET rising to CS falling CS falling to SCLK rising SCLK falling to CS rising CS rising to driving MODE low SDO setup time to SCLK rising Pulse Width Low Pulse Width High Pulse Width High Pulse Width Low XTAL = 4.096 MHz (Note 11) Any Digital Output Symbol trise tfall Any Digital Output Min 200 200 Typ 50 50 60 - Max 1.0 1.0 2 - Unit µs ns µs ns ms MHz ns ns tost SCLK t1 t2 t3 t4 t5 t6 t7 t8 50 50 100 - 20 20 20 50 50 50 ns ns ns ns ns ns t9 t10 t11 t12 t13 t14 t15 t16 50 100 50 48 100 8 8 DCLK DCLK ns DCLK 8 16 DCLK DCLK ns ns Notes: 17. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 18. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. DS682F1 11 CS5464 t3 CS t1 t2 SC LK t4 MSB-1 MSB-1 MSB MSB LSB t5 MSB-1 MSB-1 MSB MSB LSB LSB LSB L o w B y te SDI C o m m a n d T im e 8 S C L K s H ig h B y te M id B y te SDI Write Timing (Not to Scale) CS t6 MSB-1 MSB H igh B yte MSB-1 MSB LSB M id B yte MSB-1 MSB LSB Low B yte LSB t15 t14 t7 STOP bit Last 8 B it s t8 SDO UNKNOW N t1 t2 t7 SCLK MSB-1 MSB SDI C om m and T im e 8 S C LK s LSB S Y N C 0 or S Y N C 1 C om m and S Y N C 0 or S Y N C 1 C om m and S Y N C 0 or S Y N C 1 C om m and SDO Read Timing (Not to Scale) t11 MODE ( IN P U T ) RESET ( IN P U T ) t12 t13 CS (O U T P U T ) SCLK (O U T P U T ) t10 t16 t9 t4 t5 SDO (O U T P U T ) SDI ( IN P U T ) D a ta fro m E E P R O M E2PROM mode Sequence Timing (Not to Scale) Figure 1. CS5464 Read and Write Timing Diagrams 12 DS682F1 CS5464 SWITCHING CHARACTERISTICS (Continued) Parameter E1, E2, and E3 Timing Period Pulse Width Rising Edge to Falling Edge E2 Setup to E1 and/or E3 Falling Edge E1 Falling Edge to E3 Falling Edge (Note 19 and 20) Symbol tperiod tpw t3 t4 t5 Min 500 244 6 1.5 248 Typ - Max - Unit µs µs µs µs µs Notes: 19. Pulse output timing is specified at DCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0. Refer to 6.7 Energy Pulse Outputs on page 19 for more information on pulse output pins. 20. Timing is proportional to the frequency of DCLK. tpw E1 E2 tperiod t3 t4 tpw t5 tperiod t3 t5 t4 E3 Figure 2. Timing Diagram for E1, E2, and E3 ABSOLUTE MAXIMUM RATINGS WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter DC Power Supplies (Notes 21 and 22) Positive Digital Positive Analog (Notes 23, 24, 25) Symbol VD+ VA+ IIN IOUT (Note 26) All Analog Pins All Digital Pins Min -0.3 -0.3 - 0.3 -0.3 -40 -65 Typ - Max +6.0 +6.0 ±10 100 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V mA mA mW V V °C °C Input Current, Any Pin Except Supplies Output Current, Any Pin Except VREFOUT Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature PD VINA VIND TA Tstg Notes: 21. VA+ and AGND must satisfy [(VA+) - (AGND)] ≤ + 6.0 V. 22. VD+ and AGND must satisfy [(VD+) - (AGND)] ≤ + 6.0 V. 23. Applies to all pins including continuous over-voltage conditions at the analog input pins. 24. Transient current of up to 100 mA will not cause SCR latch-up. 25. Maximum DC input current for a power supply pin is ±50 mA. 26. Total power dissipation, including all input currents and output currents. DS682F1 13 CS5464 V1OFF V1GAIN FGA I1OFF I1GAIN Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements 4. SIGNAL PATH DESCRIPTION The data flow for voltage and current measurement and the other calculations are shown in Figures 3, 4, and 5. The data flow consists of two current paths and two voltage paths. Both voltage paths are derived from the same differential input pins. Each current path has its own differential input pins. decimation filters. These decimation filters are third-order Sinc. Their outputs are passed through third-order IIR “anti-sinc” filters, used to compensate for the amplitude roll-off of the decimation filters. 4.3 Phase Compensation Phase compensation changes the phase of current relative to voltage by changing the sampling time in the decimation filters. The amount of phase shift is set by bits PC[7:0] in the Configuration register (Config) for channel 1 and bits PC[7:0] in the Control register (Ctrl) for channel 2. Phase compensation, PC[7:0] is a signed two’s complement binary value in the range of -1.0 to almost +1.0 output word rate (OWR) samples. For a sample rate of 4000 Hz, the delay range is ±250 µS, a phase shift of ±4.5° at 50 Hz and ±5.4° at 60 Hz. The step size would be 0.0352° at 50 Hz and 0.0422° at 60 Hz at this sample rate. V2OFF V2GAIN 4.1 Analog-to-Digital Converters The voltage and temperature channels use second-order delta-sigma modulators and the two current channels use fourth-order delta-sigma modulators to convert the analog inputs to single-bit digital data streams. The converters sample at a rate of DCLK/8. This high sampling provides a wide dynamic range and simplifies anti-alias filter design. 4.2 Decimation Filters The single-bit modulator output data is widened to 24 bits and down-sampled to DCLK/1024 with low-pass I2OFF I2GAIN Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements 14 DS682F1 CS5464 4.4 DC Offset and Gain Correction The system and chip inherently have gain and offset errors which can be removed using the gain and offset registers. (See Section 9. System Calibration on page 39). Each measurement channel has its own registers. For every channel, the output of the IIR filter is added to the offset register and multiplied by the gain register. of interest, but passes DC. For more information, see 6.5 High-pass Filters on page 19. The HPF filter multiplexers drive the I1, V1, I2, and V2 result registers. 4.6 Low-Rate Calculations Low-rate results are derived from sample-rate results integrated over N samples, where N is the value stored in the Cycle Count register. The low-rate interval is the sample interval multiplied by N. 4.5 High-pass Filters Optional high-pass filters (HPF in Figures 3 and 4) remove any DC from the selected signal paths. Subsequently, DC will also be removed from power, and all low-rate results. (see Figures 5). Each energy channel has a current and voltage path. If an HPF is enabled in only one path, a phase-matching filter (PMF) is applied to the other path which matches the amplitude and phase delay of the HPF in the band 4.7 RMS Results The root mean square (RMS in Figure 5) calculations are performed on N instantaneous voltage and current samples, using the formula: N–1 I RMS = ∑ I n2 n=0 -------------------N DS682F1 15 CS5464 V1ACOFF (V2ACOFF) P1OFF (P2OFF) I1ACOFF (I2ACOFF) Figure 5. Low-rate Calculations 4.8 Power and Energy Results The instantaneous voltage and current samples are multiplied to obtain the instantaneous power (P1, P2) (see Figure 3 and 4). The product is then averaged over N conversions to compute active power (P1AVG, P2AVG). Apparent power (S1, S2) is the product of RMS voltage and current as shown: S = V RMS × I RMS ed to line frequency, so their gain is corrected by the Epsilon register, which is based on line frequency. Reactive power (Q1AVG, Q2AVG) is generated by integrating the instantaneous quadrature power over N samples. 4.9 Peak Voltage and Current Peak current (I1PEAK, I2PEAK) and peak voltage (V1PEAK, V2PEAK) are the largest current and voltage samples detected in the previous low-rate interval. 4.10 Power Offset Power factor (PF1, PF2) is active power divided by apparent power as shown below. The sign of the power factor is determined by the active power. P ACTIVE PF = ---------------------S Wideband reactive power (Q1WB, Q2WB) is calculated by doing a vector subtraction of active power from apparent power. Q WB = 2 S 2 – P ACTIVE The power offset registers, P1OFF (P2OFF) can be used to offset erroneous power sources resident in the system not originating from the power line. Residual power offsets are usually caused by crosstalk into current paths from voltage paths or from ripple on the meter or chip’s power supply, or from inductance from a nearby transformer. These offsets can be either positive or negative, indicating crosstalk coupling either in phase or out of phase with the applied voltage input. The power offset registers can compensate for either condition. To use this feature, measure the average power at no load using either Single or Continuous Conversion commands. Take the measured result (from the P1AVG (P2AVG) register), invert (negate) the value and write it to the associated power offset register, P1OFF (P2OFF). Quadrature power (Q1, Q2) are sample rate results obtained by multiplying instantaneous current (I1, I2) by instantaneous quadrature voltage (V1Q, V2Q) which are created by phase shifting instantaneous voltage (V1, V2) 90 degrees using first-order integrators. (see Figure 3 and 4). The gain of these integrators is inversely relat- 16 DS682F1 CS5464 5. PIN DESCRIPTIONS 5.1 Analog Pins The CS5464 has three differential inputs: VIN±, IIN1±, and IIN2± are the voltage, current1, and current2 inputs, respectively. A single-ended power fail monitor input, voltage reference input, and voltage reference output are also available. 5.1.6 Crystal Oscillator An external quartz crystal can be connected to the XIN and XOUT pins as shown in Figure 6. To reduce system cost, each pin is supplied with an on-chip, phase-shifting capacitor to ground. . XOUT C1 5.1.1 Voltage Inputs The output of the line voltage resistive divider or transformer is connected to the VIN+ and VIN- input pins of the CS5464. The voltage channel is equipped with a 10x, fixed-gain amplifier. The full-scale signal level that can be applied to the voltage channel is ±250mV. If the input signal is a sine wave, the maximum RMS voltage is 250mVp / √2 ≈ 176.78mVRMS which is approximately 70.7% of maximum peak voltage. Oscillator Circuit XIN C2 DGND 5.1.2 Current1 and Current2 Inputs The output of the current-sensing resistor or transformer is connected to the IIN1+ (IIN2+) and IIN1- (IIN2-) input pins of the CS5464. To accommodate different current-sensing elements, the current channel incorporates a programmable gain amplifier (PGA) with two selectable input gains. The full-scale signal level for the current channels is ±50mV or ±250mV. If the input signal is a sine wave, the maximum RMS voltage is 35.35mVRMS or 176.78mVRMS which is approximately 70.7% of maximum peak voltage. C1 = C2 = 22 pF Figure 6. Oscillator Connections Alternatively, an external clock source can be connected to the XIN pin. 5.2 Digital Pins 5.2.1 Reset Input The active-low RESET pin, when asserted, will halt all CS5464 operations and reset internal hardware registers and states. When de-asserted, an initialization sequence begins, setting default register values. 5.1.3 Power Fail Monitor Input An analog input (PFMON) is provided to determine when a power loss is imminent. By connecting a resistive divider from the unregulated meter power supply to the PFMON input, an interrupt can be generated, or the Low Supply Detected (LSD) Status register bit can be monitored to indicate low-supply conditions. The PFMON input has a comparator that trips around the level of the voltage reference input (VREFIN). 5.2.2 CPU Clock Output A logic-level clock output (CPUCLK) is provided at the crystal frequency to drive an external CPU or microcontroller clock. Two phase choices are available. 5.2.3 Interrupt Output The INT pin indicates an enabled Internal Status register (Status) bit is set. Status register bits indicate conditions such as data ready, modulator oscillations, low supply, voltage sag, current faults, numerical overflows, and result updates. 5.1.4 Voltage Reference Input The CS5464 requires a stable voltage reference of 2.5 V applied to the VREFIN pin. This reference can be supplied from an external voltage reference or from the VREFOUT output. A bypass capacitor of at least 0.1 µF is recommended at the VREFIN pin. 5.2.4 Energy Pulse Outputs The CS5464 provides three pins (E1, E2, E3) for pulse energy outputs. These pins can also be used to output other conditions, such as voltage sign, power fail monitor, or energy channel in use. 5.1.5 Voltage Reference Output The CS5464 generates a 2.5 V reference (VREFOUT). It is suitable for driving the VREFIN pin, but has very little fan-out and is not recommended for driving external circuits. DS682F1 17 CS5464 5.2.5 Serial Interface The CS5464 provides 5 pins, SCLK, SDI, SDO, CS, and MODE for communication between a host microcontroller or serial E2PROM and the CS5464. MODE is an input that, when high, indicates to the CS5464 that a serial E2PROM is being used instead of a host microcontroller. It has a weak pull-down allowing it to be left unconnected if microcontroller mode is used. SCLK is used to shift and qualify serial data. Serial data changes as a result of the falling edge of SCLK and is valid during the rising edge. It is a Schmitt-trigger input for host microcontrollers, and a driven output for serial E2PROMs. SDI is the serial data input to the CS5464. SDO is the serial data output from the CS5464. It’s output drivers are disabled whenever CS is de-asserted, allowing other devices to drive the SDO line. CS is the chip select input for the serial bus. A high logic level de-asserts it, tri-stating the SDO pin and clearing the serial interface. A low logic level enables the serial port. This pin may be tied low for systems not requiring multiple SDO drivers. CS is a driven output when interfacing to serial E2PROMs. 18 DS682F1 CS5464 6. SETTING UP THE CS5464 6.1 Clock Divider The internal clock to the CS5464 needs to operate around 4 MHz. However, by using the internal clock divider, a higher crystal frequency can be used. This is important when driving an external microcontroller requiring a faster clock and using the CPUCLK output. K is the divide ratio from the crystal input to the internal clock and is selected with Configuration register (Config) bits K[3:0]. It has a range of 1 to 16. A value of zero results in a setting of 16. path within a channel, a phase matching filter (PMF) is applied to the other path within that channel. The PMF filter matches the amplitude and phase response of the HPF in the band of interest, but passes DC. VHPF 0 0 1 1 IHPF 0 1 0 1 Filter Configuration No filter on Voltage or Current HPF on Current, PMF on Voltage HPF on Voltage, PMF on Current HPF on Current and Voltage 6.2 CPU Clock Inversion By default, CPUCLK is inverted from XIN. Setting Configuration register bit iCPU removes this inversion. This can be useful when one phase adds more noise to the system than the other. Table 3. High-pass Filter Configuration 6.6 Cycle Count Low-rate calculations, such as average power and RMS voltage and current integrate over several (N) output word rate (OWR) samples. The duration of this averaging window is set by the Cycle Count (N) register. By default, Cycle Count is set to 4000 (1 second at output word rate [OWR] of 4000 Hz). The minimum value for Cycle Count is 10. 6.3 Interrupt Pin Behavior The behavior of the INT pin is controlled by the IMODE and IINV bits in the Configuration register as shown. IMODE IINV INT Pin 6.7 Energy Pulse Outputs By default, E1 outputs active energy, E3, reactive energy, and E2, the sign of both active and reactive energy. (See Figure 2. Timing Diagram for E1, E2, and E3 on page 13.) Three pairs of bits in the Mode Control (Modes) register control the operation of these outputs. These bits are named E1MODE[1:0], E2MODE[1:0], and E3MODE[1:0]. Some combinations of these bits override others, so read the following paragraphs carefully. The E2 pin can output energy sign, apparent energy, or energy channel in use (1 or 2). Table 4 lists the functions of E2 as controlled by E2MODE[1:0] in the Modes register. Note: E2MODE[1:0]=3 is a special mode. E2MODE1 E2MODE0 E2 output 0 0 1 1 0 1 0 1 Active-low Level Active-high Level Low Pulse High Pulse Table 1. Interrupt Configuration If IMODE = 1, the duration of the INT pulse will be two DCLK cycles, where DCLK = MCLK/K. 6.4 Current Input Gain Ranges Control register bits I1gain (I2gain) select the input range of the current inputs. I1gain, I2gain Maximum Input Gain 0 1 ±250 mV ±50 mV 10x 50x 0 0 1 1 0 1 0 1 Energy Sign Apparent Energy Channel in Use Enable E1MODE Table 2. Current Input Gain Ranges 6.5 High-pass Filters Mode Control (Modes) register bits VHPF and IHPF activate the HPF in the voltage and current paths, respectively. Each energy channel has separate VHPF and IHPF bits. When a high-pass filter is enabled in only one Table 4. E2 Pin Configuration The E3 pin can output reactive energy, power fail monitor status, voltage sign, or apparent energy. Table 5 DS682F1 19 CS5464 lists the functions of E3 as controlled by E3MODE[1:0] in the Modes register when E1MODE is not enabled. E3MODE1 E3MODE0 E3 output 6.8 No Load Threshold The No Load Threshold register (LoadMIN) is used to zero out the contents of EPULSE and QPULSE registers if their magnitude is less than the LoadMIN register value. 0 0 1 1 0 1 0 1 Reactive Energy Power Fail Monitor Voltage Sign Apparent Energy 6.9 Energy Pulse Width Note: Energy Pulse Width (PulseWidth) only applies to E1, E2, or E3 pins that are configured to output pulses. When any are configured to output steady-state signals, such as voltage sign, energy channel in use, power fail monitor, or energy sign, pulse widths and output rates do not apply. The pulse width time (tpw) in Figure 2, is set by the value in the PulseWidth register which is an integer multiple of the sample or output word rate (OWR). At OWR of 4000 Hz (a period of 250 uS) tpw = PulseWidth x 250uS. By default, PulseWidth is set to 1. Table 5. E3 Pin Configuration When both E2MODE bits are high, the E1MODE bits are enabled, allowing active, apparent, reactive, or wideband reactive energy for both energy channels to be output on E1 and E2. Table 6 lists the functions of E1 and E2 with E1MODE enabled. E1MODE1 E1MODE0 E1 / E2 outputs 6.10 Energy Pulse Rate The full-scale pulse frequency of enabled E1, E2, E3 pins is the PulseRate x output word rate (OWR)/2. The actual pulse frequency is the full-scale pulse frequency multiplied by the pulse register’s (EPULSE, SPULSE, QPULSE) value. Example: If the output word rate (OWR) is 4000 Hz, and the PulseRate is set to 0.05, the full-rate pulse frequency is 0.05 x 4000 / 2 = 100 Hz. If the EPULSE register, driving E1, is 0.4567, the pulse output rate on E1 will be 100 Hz x 0.4567 = 45.67 Hz. 0 0 1 1 0 1 0 1 Active Energy Apparent Energy Reactive Energy Wideband Reactive Table 6. E1 / E2 Modes When E1MODE bits are enabled, the E3 pin outputs either the power fail monitor status, or the sign of the E1 and E2 outputs. Table 7 list the functions of the E3 pin using E3MODE[1:0] in the Modes register when E1MODE is enabled . E3MODE1 E3MODE0 E3 output 6.11 Voltage Sag/Current Fault Detection Voltage sag detection is used to determine when averaged voltage falls below a predetermined level for a specified interval of time. Current fault detection determines when averaged current falls below a predetermined level for a specified interval of time. The specified interval of time (duration) is set by the value in the V1SagDUR (V2SagDUR) and I1FaultDUR (I2FaultDUR) registers. Setting any of these to zero (default) disables the detect feature for the given channel. The value is in output word rate (OWR) samples. The predetermined level is set by the values in the V1SagLEVEL (V2SagLEVEL) and I1FaultLEVEL (I2FaultLEVEL) registers. Since the values of V1 and V2 come from the same input, only one voltage sag detector is necessary. 0 0 1 1 0 1 0 1 Power Fail Monitor Energy Sign not used not used Table 7. E3 Pin with E1MODE enabled 20 DS682F1 CS5464 For each enabled input channel, the measured value is rectified and compared to the associated level register. Over the duration window, the number of samples above and below the level are counted. If the number of samples below the level exceeds the number of samples above, a Status register bit V1SAG (V2SAG), I1FAULT (I2FAULT) is set, indicating a sag or fault condition. (see Figure 7).. The application program can change both the scale and range of Temperature (T) by changing the Temperature Gain (TGAIN) and Temperature Offset (TOFF) registers. Two values must be known — the transistor’s ∆VBE per degree, and the transistor’s VBE at 0 degrees. At the time of this publication, these values are: ∆VBE (per degree) = 0.2769523 mV/°C or °K VBE0 = 79.2604368 mV at 0°C To determine the values to write to TGAIN and TOFF, use the following formulae: TGAIN = ADFS / ∆VBE / TFS x 217 TOFF = -VBE0 / ADFS x 223 In the above equations, ADFS is the full-scale input range of the temperature A/D converter or 833.333 mV and TFS is the desired full-scale range of the Temperature register. The binary exponents are the bit positions of the binary point of these registers. Figure 7. Sag and Fault Detect 6.12 Epsilon The Epsilon register is used to set the gain of the 90° phase shift used in the quadrature power calculation. The value in the Epsilon register is the ratio of the line frequency to the output word rate (OWR). It is, by default, 50/4000 (0.0125), for 50 Hz line and 4000 Hz sample (OWR) frequencies. For 60 Hz line frequency, it is 60/4000 (0.015). Other output word rates (OWR) can be used. Epsilon can also be calculated automatically by the CS5464 by setting the AFC bit in the Mode Control (Modes) register. The Frequency Update bit (FUP) in the Status register is set every time the Epsilon register has been automatically updated. To use the Celsius scale (°C) and cover the chip’s operating temperature range of -40°C to +85°C, the Temperature register range needs to be ±128 degrees. TFS should be 128 degrees. TGAIN = 833.333 / 0.2769523 / 128 x 131072 = 3081155 (0x2F03C3) TOFF = -79.2604368 / 833.333 x 8388608 = -797862 (0xF3D35A) These are the actual default values for these registers. TGAIN and TOFF can also be used to calibrate the gain and/or offset of the temperature sensor or A/D converter. (See Section 9. System Calibration on page 39). ∆VBE / ADFS x 223 to TOFF since 0°C = 273°K,. You will To use the Kelvin (°K) scale, simply add 273 times 6.13 Temperature Measurement The on-chip temperature sensor is designed to measure temperature and optionally compensate for temperature drift of the voltage reference. It uses the VBE of a transistor to determine temperature. Temperature measurements are stored in the Temperature register (T) which, by default, is configured to a range of ±128 degrees on the Celsius (°C) scale. also need more range. Since -40°C to +85°C is 233°K to 358°K, a TFS of 512 degrees should be used in the TGAIN calculation. To use the Fahrenheit (°F) scale, multiply ∆VBE by 5/9 and add 32 times the new ∆VBE / ADFS x 223 to TOFF since 0°C = 32°F. You will also want to use a TFS of 256 degrees to cover the -40°C to +85°C range. The Temperature register (T) updates every 2240 output word rate (OWR) samples. The Status register bit TUP indicates when T is updated. DS682F1 21 CS5464 7. USING THE CS5464 7.1 Initialization The CS5464 uses a power-on-reset circuit (POR) to provide an internal reset until the analog voltage reaches 4.0 V. The RESET input pin can also be used by the application circuit to reset the part. After RESET is removed and the oscillator is stable, an initialization program is executed to set the default register values. A Software Reset command is also provided to allow the application to run the initialization program without removing power or asserting RESET. The application should avoid sending commands during initialization. The DRDY bit in the Status register indicates when the initialization program has completed. change. Modes register bit Ichan selects the energy channel, and is normally driven by the CS5464 program. This affects the pulse registers and pulse energy outputs. (See figure 8). The application program can also choose the more appropriate energy channel. Modes register bit Ihold disables automatic selection and Ichan can be driven by the application. Shown below is the channel selector. 7.2 Power-down States The CS5464 has two power-down states, stand-by and sleep. In the stand-by state, all circuitry except the voltage reference and crystal oscillator is powered off. In sleep state, all circuitry except the instruction decoder is powered off. To return the device to the active state, send a WakeUp/Halt command to the device. When returning from stand-by mode, registers will retain their contents prior to entering the stand-by state. When returning from sleep mode, a complete initialization occurs. AVG AVG Figure 8. Energy Channel Selection 7.3 Tamper Detection and Correction The CS5464 provides compensation for at least two forms of meter tampering. A second current input is provided in the event that the primary input is impaired by tampering. (See Figure 14 on page 42). An internal RMS voltage reference is also available in the event that the voltage input has been compromised by tampering. Power and energy are calculated for BOTH current inputs (both energy channels). The CS5464 can automatically choose the channel with the greater magnitude. The register EMIN, (also called IrmsMIN) sets a minimum level for automatic channel selection, and IchanLEVEL sets a minimum difference that will allow a channel If the application detects that the voltage input has been impaired it may choose to use the fixed internal RMS voltage reference by setting the VFIX bit in the Modes register. The value of this reference (VFRMS) is by default 0.707107 (full-scale RMS) but can be changed by the application program. (See figure 9) Figure 9. Fixed RMS Voltage Selection 22 DS682F1 CS5464 7.4 Command Interface Commands and data are transferred most-significant bit (MSB) first. Figure 1 on page 12, defines the serial port timing. Commands are clocked in on SDI using SCLK. They are a single byte (8 bits) long and fall into one of four basic types: 1. Register Read 2. Register Write 3. Synchronizing 4. Instructions Register reads will cause up to four bytes of register data to be clocked out, MSB first on the SDO pin by SCLK. During this time, other commands can be clocked in on the SDI pin. Other commands will not interrupt read data, except another register read, which will cause the new read data to appear on SDO. Synchronizing can be sent while read data is being clocked out if no other commands need to be sent. Synchronizing commands are also used to synchronize the serial port to a byte boundary. The CS and RESET pins will also synchronize the serial port. Register writes require three bytes of write data to follow, clocked in on the SDI pin, MSB first by SCLK. Instructions are commands that will interrupt any instruction currently executing and begin the new instruction. These include conversions, calibrations, power control, and soft reset. (See Section 7.6 Commands on page 24). 7.5 Register Paging Read and Write commands access one of 32 registers within a specified page. The Resgister Page Select register’s (Page) default value is 0. To access registers in another page, write the desired page number to the Page register. The Page register is always at address 31 and is accessible from within any page. DS682F1 23 CS5464 7.6 Commands All commands are 1 byte (8 bits) long. Many command values are unused and should NOT be written by the application program. All commands except register reads, register writes, or synchronizing commands will abort any conversion, calibration, or any initialization sequence currently executing. This includes reset. No commands other than reads or synchronizing should be executed until the reset sequence completes. 7.6.1 Conversion B7 1 B6 1 B5 1 B4 0 B3 CC B2 0 B1 0 B0 0 Executes a conversion (measurement) program. CC Continuous/Single Conversion 0 = Perform a Single Conversion (0xE0) 1 = Perform Continuous Conversion (0xE8) 7.6.2 Synchronization (SYNC0 and SYNC1) B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 B0 SYNC The serial interface is bidirectional. While reading data on the SDO output, the SDI input must be receiving commands. If no command is needed during a read, SYNC0 or SYNC1 commands can be sent while read data is received on SDO. The serial port is normally initialized by de-asserting CS. An alternative method of initialization is to send 3 or more SYNC1 commands followed by a SYNC0. This is useful in systems where CS is not used and tied low. 7.6.3 Power Control (Stand-by, Sleep, Wake-up/Halt and Software Reset) B7 1 B6 0 B5 S1 B4 S0 B3 0 B2 0 B1 0 B0 0 The CS5464 has two power-down states, stand-by and sleep. In stand-by, all circuitry except the voltage reference and clocks are turned off. In sleep, all circuitry except the command decoder is turned off. A Wake-up/Halt command restores full-power operation after stand-by and issues a hardware reset after sleep. The Software Reset command is a program that emulates a pin reset and is not a power control function. S[1:0] 00 = Software Reset 01 = Sleep 10 = Wake-up/Halt 11 = Stand-by 24 DS682F1 CS5464 7.6.4 Calibration B7 1 B6 0 B5 CAL5 B4 CAL4 B3 CAL3 B2 CAL2 B1 CAL1 B0 CAL0 The CS5464 can perform gain and offset calibrations using either DC or AC signals. Proper input levels must be applied to the current inputs and voltage input before performing calibrations. CAL[5:4]* 00 = DC Offset 01 = DC Gain 10 = AC Offset 11 = AC Gain 0001 = Current for Channel 1 0010 = Voltage for Channel 1 0100 = Current for Channel 2 1000 = Voltage for Channel 2 Anywhere from 1 to all 4 channels can be calibrated simultaneously. Voltage channels 1 and 2 use the same voltage input. Commands with CAL[5:0] = 0 are not calibrations. CAL[3:0] Note: DS682F1 25 CS5464 7.6.5 Register Read and Write B7 0 B6 W/R B5 RA4 B4 RA3 B3 RA2 B2 RA1 B1 RA0 B0 0 Read and Write commands provide access to on-chip registers. After a Read command, the addressed data can be clocked out the SDO pin by SCLK. After a Write command, 24 bits of write data must follow. The data is transferred to the addressed register after the 24th data bit is received. Registers are organized into pages of 32 addresses each. To access a desired page, write its number to the Page register at address 31. W/R Write/Read control 0 = Read 1 = Write Register address. RA[4:0] Page 0 Registers Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 31 W RA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 11111 Name Config I1 V1 P1 P1AVG I1RMS V1RMS I2 V2 P2 P2AVG I2RMS V2RMS Q1AVG Q1 Status Q2AVG Q2 I1PEAK V1PEAK S1 PF1 I2PEAK V2PEAK S2 PF2 Mask T Ctrl EPULSE SPULSE QPULSE Page Description Configuration Instantaneous Current Channel 1 Instantaneous Voltage Channel 1 Instantaneous Power Channel 1 Active Power Channel 1 RMS Current Channel 1 RMS Voltage Channel 1 Instantaneous Current Channel 2 Instantaneous Voltage Channel 2 Instantaneous Power Channel 2 Active Power Channel 2 RMS Current Channel 2 RMS Voltage Channel 2 Reactive Power Channel 1 Instantaneous Quadrature Power Channel 1 Internal Status Reactive Power Channel 2 Instantaneous Quadrature Power Channel 2 Peak Current Channel 1 Peak Voltage Channel 1 Apparent Power Channel 1 Power Factor Channel 1 Peak Current Channel 2 Peak Voltage Channel 2 Apparent Power Channel 2 Power Factor Channel 2 Interrupt Mask Temperature Control Active Energy Pulse Output Apparent Energy Pulse Output Reactive Energy Pulse Output Register Page Select Warning: Do not write to unpublished register locations. 26 DS682F1 CS5464 Page1 Registers Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 W RA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11111 Name I1OFF I1GAIN V1OFF V1GAIN P1OFF I1ACOFF V1ACOFF I2OFF I2GAIN V2OFF V2GAIN P2OFF I2ACOFF V2ACOFF PulseWidth PulseRate Modes Epsilon IchanLEVEL N Q1WB Q2WB TGAIN TOFF EMIN (IrmsMIN) TSETTLE LoadMIN VFRMS G Time Page Description Current DC Offset Channel 1 Current Gain Channel 1 Voltage DC Offset Channel 1 Voltage Gain Channel 1 Power Offset Channel 1 Current AC (RMS) Offset Channel 1 Voltage AC (RMS) Offset Channel 1 Current DC Offset Channel 2 Current Gain Channel 2 Voltage DC Offset Channel 2 Voltage Gain Channel 2 Power Offset Channel 2 Current AC (RMS) Offset Channel 2 Voltage AC (RMS) Offset Channel 2 Pulse Output Width Pulse Output Rate (frequency) Mode Control Ratio of Line to Sample Frequency Irms or E Channel Select Trip Level Cycle Count (Number of OWR Samples in One Low-rate Interval) Wideband Reactive Power from Power Triangle Channel 1 Wideband Reactive Power from Power Triangle Channel 2 Temperature Sensor Gain Temperature Sensor Offset Energy Channel Selector Minimum Operating Level Filter Settling Time for Conversion Startup No Load Threshold Voltage RMS Fixed Reference System Gain System Time (in samples) Register Page Select Page2 Registers Address 0 1 4 5 8 9 12 13 31 W RA[4:0] 00000 00001 00100 00101 01000 01001 01100 01101 11111 Name V1SagDUR V1SagLEVEL I1FaultDUR I1FaultLEVEL V2SagDUR V2SagLEVEL I2FaultDUR I2FaultLEVEL Page Description V Sag Duration Channel 1 V Sag Level Channel 1 I Fault Duration Channel 1 I Fault Level Channel 1 V Sag Duration Channel 2 V Sag Level Channel 2 I Fault Duration Channel 2 I Fault Level Channel 2 Register Page Select Warning: Do not write to unpublished register locations. DS682F1 27 CS5464 8. REGISTER DESCRIPTIONS 1. “Default” = bit states after power-on or reset 2. DO NOT write a “1” to any unpublished register bit. 3. DO NOT write to any unpublished register address. 8.1 Page Register 8.1.1 Page – Address: 31, Write-only, can be written from ANY page. MSB 26 2 5 LSB 2 4 2 3 2 2 2 1 20 Default = 0 Register Read and Write commands contain only 5 address bits. But the internal address bus of the CS5464 is 12 bits wide. Therefore, registers are organized into “Pages”. There are 128 pages of 32 registers each. The Page register provides the 7 high-order address bits and selects one of the 128 register pages. Not all pages are used, Page is a write-only integer containing 7 bits. 8.2 Page 0 Registers 8.2.1 Configuration (Config) – Address: 0 23 PC7 15 EWA 7 22 PC6 14 6 21 PC5 13 5 20 PC4 12 IMODE 4 iCPU 19 PC3 11 IINV 3 K3 18 PC2 10 2 K2 17 PC1 9 1 K1 16 PC0 8 0 K0 Default = 1 (K=1) PC[7:0] EWA Phase compensation for channel 1. Sets a delay in voltage, relative to current. Phase is signed and in the range of -1.0 ≤ value < 1.0 sample (OWR) intervals. Allows the E1 and E2 pins to be configured as open-drain outputs. 0 = Normal Outputs 1 = Open-drain Outputs Interrupt configuration. Selects INT pin behavior. 00 = Low Logic Level When Asserted 01 = High Logic Level When Asserted 10 = Low-going Pulse on New Interrupt 11 = High-going Pulse on New Interrupt Inverts the CPUCLK output. 0 = Default 1 = Invert CPUCLK. Clock divider. Divides MCLK by K to generate internal clock DCLK. (DCLK = MCLK/K). K is unsigned and in the range of 1 to 16. When zero, K = 16. At reset, K = 1. IMODE, IINV iCPU K[3:0] 28 DS682F1 CS5464 8.2.2 Instantaneous Current (I1, I2), Voltage (V1, V2), and Power (P1, P2) Address: 1 (I1), 2 (V1), 3 (P2), 7 (I2), 8 (V2), 9 (P2) MSB -(2 ) 0 LSB 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 I1 (I2) and V1 (V2) contain instantaneous current and voltage, respectively, which are multiplied to yield instantaneous power, P1 (P2). These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. 8.2.3 Active Power (P1AVG , P2AVG ) Address: 4 (P1AVG), 10 (P2AVG) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Instantaneous power is averaged over each low-rate interval (N samples) to compute active power, P1AVG (P2AVG). These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. 8.2.4 RMS Current (I1RMS, I2RMS ) and Voltage (V1RMS, V2RMS ) Address: 5 (I1RMS), 6 (V1RMS), 11 (I2RMS), 12 (V2RMS) MSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 LSB 2-24 I1RMS (I2RMS) and V1RMS (V2RMS) contain the root mean square (RMS) values of I1 (I2) and V1 (V2), calculated each low-rate interval. These are unsigned values in the range of 0 ≤ value < 1.0, with the binary point to the left of the MSB. 8.2.5 Instantaneous Quadrature Power (Q1, Q2) Address: 14 (Q1), 17 (Q2) MSB -(2 0) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Instantaneous quadrature power, Q1 (Q2), the product of voltage1 (voltage2) shifted 90 degrees and current1 (current2). These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. 8.2.6 Reactive Power (Q1AVG, Q2AVG ) Address: 13 (Q1AVG), 16 (Q2AVG) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Reactive power Q1AVG (Q2AVG) is Q1 (Q2) averaged over every N samples. These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. DS682F1 29 CS5464 8.2.7 Peak Current (I1PEAK, I2PEAK ) and Peak Voltage (V1PEAK, V2PEAK ) Address: 18 (I1PEAK), 19 (V1PEAK), 22 (I2PEAK), 23 (V2PEAK) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Peak current, I1PEAK (I2PEAK) and peak voltage, V1PEAK (V2PEAK) are the instantaneous current and voltage samples with the greatest magnitude detected during the last low-rate interval. These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. 8.2.8 Apparent Power (S1, S2) Address: 20 (S1), 24 (S2) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Apparent power S1 (S2) is the product of V1RMS and I1RMS (V2RMS and I2RMS), These are two's complement values in the range of 0 ≤ value < 1.0, with the binary point to the right of the MSB. 8.2.9 Power Factor (PF1, PF2) Address: 21 (PF1), 25 (PF2) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Power factor is calculated by dividing active power by apparent power. The sign is determined by the active power sign. These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. 8.2.10 Temperature (T) – Address: 27 MSB -(27) 26 25 24 23 22 21 20 ..... 2-10 2-11 2-12 2-13 2-14 2-15 LSB 2-16 T contains results from the on-chip temperature measurement. By default, T uses the Celsius scale, and is a two's complement value in the range of -128.0 ≤ value < 128.0 (oC), with the binary point to the right of bit 16. T can be rescaled by the application using the TGAIN and TOFF registers. 8.2.11 Active, Apparent, and Reactive Energy Pulse Outputs (EPULSE, SPULSE, QPULSE ) Address: 29 (EPULSE), 30 (SPULSE), 31 (QPULSE) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 These drive the pulse outputs when configured to do so. If the Ichan bit in Modes is “0”, these registers are driven from P1AVG, S1, and Q1AVG, respectively. If the Ichan bit is “1”, these registers are driven from P2AVG, S2, and Q2AVG, respectively. These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. 30 DS682F1 CS5464 8.2.12 Internal Status (Status) and Interrupt Mask (Mask) Address: 15 (Status); 26 (Mask) 23 DRDY 15 E2OR 7 TUP 22 I2OR 14 I1ROR 6 TOD 21 V2OR 13 V1ROR 5 I2OD 20 CRDY 12 E1OR 4 VOD 19 I2ROR 11 I1FAULT 3 I1OD 18 V2ROR 10 V1SAG 2 LSD 17 I1OR 9 I2FAULT 1 FUP 16 V1OR 8 V2SAG 0 IC Default = 1 (Status), 0 (Mask) The Status register indicates a variety of conditions within the chip. Writing a '1' to a Status register bit will clear that bit if the condition that set it has been removed. Writing a '0' to any bit has no effect. The Mask register is used to control the activation of the INT pin. Placing a logic '1' to a Mask register bit will allow the corresponding Status register bit to activate the INT pin when set. DRDY I1OR (I2OR) V1OR (V2OR) CRDY I1ROR (I2ROR) V1ROR (V2ROR) E1OR (E2OR) Data Ready. During conversion, this bit indicates that low-rate results have been updated. It indicates completion of other commands and the reset sequence. Current Out of Range. Set when the measured current would cause the I1 (I2) register to overflow. Voltage Out of Range. Set when the measured voltage would cause the V1 (V2) register to overflow. Conversion Ready. Indicates that sample rate (output word rate) results have been updated. RMS Current Out of Range. Set when RMS current would cause the I1RMS (I2RMS) register to overflow. RMS Voltage Out of Range. Set when RMS voltage would cause the V1RMS (V2RMS) register to overflow. Energy Out of Range. Set when average power would cause P1AVG (P2AVG) to overflow. I1FAULT (I2FAULT)Indicates when a current fault condition has occurred. V1SAG (V2SAG) TUP TOD VOD I1OD (I2OD) LSD FUP IC Indicates when a voltage sag condition has occurred. Indicates when the Temperature register (T) has been updated. Modulator oscillation has been detected in the temperature A/D. Modulator oscillation has been detected in the voltage A/D. Modulator oscillation has been detected in the current1 (current2) A/D. Low Supply Detect. Set when the voltage on the PFMON pin falls below the specified low level. LSD bit cannot be reset until the voltage rises above the specified high level. Frequency Updated. Indicates the Epsilon register has been updated. Invalid Command. Normally logic 1. Set to 0 when an invalid command is received. It may also indicate loss of serial command synchronization and the part may need to be re-initialized. DS682F1 31 CS5464 8.2.13 Control (Ctrl) – Address: 28 23 PC7 15 7 22 PC6 14 6 21 PC5 13 5 I1gain 20 PC4 12 I2gain 4 INTOD 19 PC3 11 3 18 PC2 10 2 NOCPU 17 PC1 9 1 NOOSC 16 PC0 8 STOP 0 - Default = 0 PC[7:0] Phase compensation for channel 2. Sets a delay in voltage relative to current. Phase is signed and in the range of -1.0 ≤ value < 1.0 sample (OWR) intervals. I1gain (I2gain) Sets the gain of the current1 (current2) input. 0 = Gain is set for ±250mV range. 1 = Gain is set for ±50mV range. STOP Terminates E2PROM command sequence (if used). 0 = No Action 1 = Stop E2PROM Commands. Converts INT output pin to an open drain output. 0 = Normal Output 1 = Open-drain Output Saves power by disabling the CPUCLK output pin. 0 = CPUCLK Enabled 1 = CPUCLK Disabled Disables the crystal oscillator, making XIN a logic-level input. 0 = Crystal Oscillator Enabled 1 = Crystal Oscillator Disabled INTOD NOCPU NOOSC 32 DS682F1 CS5464 8.3 Page 1 Registers 8.3.1 DC Offset for Current (I1OFF , I2OFF ) and Voltage (V1OFF , V2OFF ) Address: 0 (I1OFF), 2 (V1OFF), 7 (I2OFF), 9 (V2OFF) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default = 0 DC offset registers I1OFF & V1OFF (I2OFF & V2OFF) are initialized to zero on reset. During DC offset calibration, selected registers are written with the inverse of the DC offset measured. The application program can also write the DC offset register values. These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. 8.3.2 Gain for Current (I1GAIN , I2GAIN ) and Voltage (V1GAIN , V2GAIN ) Address: 1 (I1GAIN), 3 (V1GAIN), 8 (I2GAIN), 10 (V2GAIN) MSB 21 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 LSB 2-22 Default = 1.0 Gain registers I1GAIN & V1GAIN (I2GAIN & V2GAIN) are initialized to 1.0 on reset. During AC or DC gain calibration, selected register are written with the multiplicative inverse of the gain measured. These are unsigned fixed-point values in the range of 0 ≤ value < 4.0, with the binary point to the right of the second MSB. 8.3.3 Power Offset (P1OFF , P2OFF ) Address: 4 (P1OFF ), 11 (P2OFF ) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default = 0 Power offset P1OFF (P2OFF) is added to instantaneous power and averaged over a low-rate interval to yield P1AVG (P2AVG) register results. It can be used to reduce systematic energy errors. These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. 8.3.4 AC Offset for Current (I1ACOFF , I2ACOFF ) and Voltage (V1ACOFF , V2ACOFF ) Address: 5 (I1ACOFF), 6 (V1ACOFF), 12 (I2ACOFF), 13 (V2ACOFF) MSB -(20) 2 -1 LSB 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 Default = 0 AC offset registers I1ACOFF & V1ACOFF (VACOFF & V2ACOFF) are initialized to zero on reset. These are added to the RMS results before being stored to the RMS result registers. They can be used to reduce systematic errors in the RMS results. These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. DS682F1 33 CS5464 8.3.5 Mode Control (Modes) – Address: 16 23 Ichan 15 IvsE 7 IHPF2 22 VFIX 14 E1MODE1 6 VHPF1 21 13 E1MODE0 5 IHPF1 20 12 Ihold 4 19 11 3 E3MODE1 18 10 E2MODE1 2 E3MODE0 17 9 E2MODE0 1 POS 16 8 VHPF2 0 AFC Default = 0 Ichan Chooses an energy channel to drive the EPULSE, SPULSE, and QPULSE registers. 0 = Pulse registers driven by energy channel 1. 1 = Pulse registers driven by energy channel 2. Use internal RMS voltage reference instead of voltage input for average active power. 0 = Use voltage input. 1 = Use Internal RMS voltage reference, VFRMS. Use IRMS results instead of PAVG for energy channel selection 0 = Use P1AVG and P2AVG instead of I1RMS and I2RMS. 1 = Use I1RMS and I2RMS instead of P1AVG and P2AVG. E1, E2, and E3 alternate Output Mode (when enabled by E2MODE) 00 = E1, E2 = P1AVG, P2AVG 01 = E1, E2 = S1, S2 10 = E1, E2 = Q1AVG, Q2AVG 11 = E1, E2 = Q1WB, Q2WB Suspends automatic channel selection. 0 = Channel selected automatically by magnitude compare. 1 = Channel selected by application (host). E2 Output Mode 00 = Energy Sign 01 = Apparent Energy 10 = Channel In Use 11 = Enable E1MODE VFIX IvsE E1MODE[1:0] Ihold E2MODE[1:0] VHPF2:IHPF2 High-pass Filter Enable for Energy Channel 2 00 = No Filter 01 = HPF on Current, PMF on Voltage 10 = HPF on Voltage, PMF on Current 11 = HPF on both Voltage and Current VHPF1:IHPF1 High-pass Filter Enable for Energy Channel1 00 = No Filter 01 = HPF on Current, PMF on Voltage 10 = HPF on Voltage, PMF on Current 11 = HPF on both Voltage and Current E3MODE[1:0] E3 Output Mode (with E1MODE disabled) 00 = Reactive Energy (default) 01 = Power Fail Monitor 10 = Voltage Sign 11 = Apparent Energy DS682F1 34 CS5464 E3MODE[1:0] E3 Output Mode (with E1MODE enabled) 00 = Power Fail Monitor 01 = Energy Sign 10 = not used 11 = not used Positive Energy Only. Suppresses negative values in P1AVG and P2AVG. If a negative value is calculated, zero will be stored instead. Enables automatic line frequency measurement which sets Epsilon every time a new line frequency measurement completes. Epsilon is used to control the gain of the 90 degree phase shift integrator used in quadrature power calculations. POS AFC 8.3.6 Line to Sample Frequency Ratio (Epsilon) – Address: 17 MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default = 0.0125 (4.0 kHz x 0.0125 or 50 Hz) Epsilon is the ratio of the input line frequency to the output word rate (OWR). It can either be written by the application program or calculated automatically from the line frequency (from the voltage input) using the AFC bit in the Modes register. It is a two's complement value in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. Negative values are not used. 8.3.7 Pulse Output Width (PulseWidth) – Address: 14 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 1 (250 uS at OWR = 4 kHz) PulseWidth sets the duration of energy pulses. The actual pulse duration is the contents of PulseWidth divided by the output word rate (OWR). PulseWidth is an integer in the range of 1 to 8,388,607. 8.3.8 Pulse Output Rate (PulseRate) – Address: 15 MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default= -1 PulseRate sets the full-scale frequency for E1, E2, E3 pulse outputs. For a 4 kHz sample rate, the maximum pulse rate is 2 kHz. This is a two's complement value in the range of -1 ≤ value < 1, with the binary point to the left of the MSB. Refer to 6.10 Energy Pulse Rate on page 20 for more information. DS682F1 35 CS5464 8.3.9 Cycle Count (N) – Address: 19 MSB 0 2 22 LSB 2 21 2 20 2 19 2 18 2 17 2 16 ..... 26 2 5 2 4 2 3 2 2 2 1 20 Default = 4000 Determines the number of output word rate (OWR) samples to use in calculating low-rate results. Cycle Count (N) is an integer in the range of 10 to 8,388,607. Values less than 10 should not be used. 8.3.10 Channel Select Level (Ichanlevel ) – Address: 18 MSB 20 2 -1 LSB 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 Default = 1.02 (minimum difference = 2%) Sets the hysteresis level for energy channel selection. If the most positive value of P1AVG and P2AVG (I1RMS and I2RMS) is greater than IchanLEVEL multiplied by the least-positive value, and is also greater than IchanMIN, the channel associated with the most-positive value will be used. If not, the previous channel selection will remain. IchanLEVEL is an unsigned fixed-point value in the range of 0 ≤ value < 2.0, with the binary point to the left of the MSB. A value of 1.0 or less indicates no hysteresis will be used. 8.3.11 Channel Select Minimum Amplitude (EMIN or IrmsMIN ) – Address: 24 MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default = 0.003 Sets the minimum level for energy channel selection. If the most positive value of P1AVG and P2AVG (I1RMS and I2RMS) is less than IchanMIN then the previous channel selection will remain in use. It is a two's complement value in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. Negative values are not used. 8.3.12 Wideband Reactive Power (Q1WB , Q2WB ) Address: 20 (Q1WB), 21 (Q2WB) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Wideband reactive power is calculated using vector subtraction. (See Section 4.8 Power and Energy Results on page 16). The value is signed, but has a range of 0 ≤ value < 1.0. The binary point is to the right of the MSB. 36 DS682F1 CS5464 8.3.13 Temperature Gain (TGAIN ) – Address: 22 MSB 2 6 LSB 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 ..... 2-11 2 -12 2 -13 2 -14 2 -15 2 -16 2-17 Default = 0x2F02C3 Refer to 6.13 Temperature Measurement on page 21 for more information. 8.3.14 Temperature Offset (TOFF ) – Address: 23 MSB -(20 ) 2 -1 LSB 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 Default = 0xF3D35A Refer to 6.13 Temperature Measurement on page 21 for more information. 8.3.15 Filter Settling Time for Conversion Startup (TSETTLE ) – Address: 25 MSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 LSB 20 Default = 30 Sets the number of output word rate (OWR) samples that will be used to allow filters to settle at the beginning of Conversion and Calibration commands. This is an integer in the range of 0 to 8,388,607 samples. 8.3.16 No Load Threshold (LoadMIN) – Address 26 MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default = 0 LoadMIN is used to set the no load threshold. When the magnitude of the EPULSE register is less than LoadMIN, EPULSE will be zeroed. If the magnitude of the QPULSE register is less than LoadMIN, Qpulse will be zeroed. LoadMIN is a two’s compliment value in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. Negative values are not used. 8.3.17 Voltage Fixed RMS Reference (VFRMS) – Address 27 MSB -(20 ) 2 -1 LSB 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 Default = 0.7071068 (full scale RMS) If the application program detects that the meter has possibly been tampered with in such a manner that the voltage input is no longer working, it may choose to use this internal RMS reference instead of the disabled voltage input by setting the VFIX bit in the Modes register. This is a two's complement value in the range of 0 ≤ value < 1.0, with the binary point to the right of the MSB. Negative values are not used. DS682F1 37 CS5464 8.3.18 System Gain (G) – Address: 28 MSB -(2 ) 1 LSB 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2-16 2 -17 2 -18 2 -19 2 -20 2 -21 2-22 Default = 1.25 System Gain (G) is applied to all channels. By default, G = 1.25, but can be finely adjusted to compensate for voltage reference error. It is a two's complement value in the range of -2.0 ≤ value < 2.0, with the binary point to the right of the second MSB. Values should be kept within 5% of 1.25. 8.3.19 System Time (Time) – Address: 29 MSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 LSB 20 Default = 0 System Time (Time) is measured in output word rate (OWR) samples. This is an unsigned integer in the range of 0 to 16,777,215 samples. At 4.0 kHz, OWR it will overflow every 1 hour, 9 minutes, and 54 seconds. Time can be used by the application to manage real-time events. 8.4 Page 2 Registers 8.4.1 Voltage Sag and Current Fault Duration (V1SagDUR , V2SagDUR , I1FaultDUR , I2FaultDUR ) Address: 0 (V1SagDUR), 8 (V2SagDUR), 4 (I1FaultDUR), 12 (I2FaultDUR) MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0 Voltage sag duration, V1SagDUR (V2SagDUR) and current fault duration, I1FaultDUR (I2FaultDUR) determine the count of output word rate (OWR) samples utilized to determine a sag or fault event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 8.4.2 Voltage Sag and Current Fault Level (V1SagLEVEL , V2SagLEVEL , I1FaultLEVEL , I2FaultLEVEL ) Address: 1 (V1SagLEVEL), 9 (V2SagLEVEL), 5 (I1FaultLEVEL), 13 (I2FaultLEVEL) MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23 Default = 0 Voltage sag level, V1SagLEVEL (V2SagLEVEL) and current fault level, I1FaultLEVEL (I2FaultLEVEL) establish an input level below which a sag or fault is triggered These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB. Negative values are not used. 38 DS682F1 CS5464 9. SYSTEM CALIBRATION 9.1 Calibration The CS5464 provides DC offset and gain calibration that can be applied to the voltage and current measurements, and AC offset calibration which can be applied to the voltage and current RMS calculations. Since the voltage and current channels have independent offset and gain registers, offset and gain calibration can be performed on any channel independently. The data flow of the calibration is shown in Figure 10. The CS5464 must be operating in its active state and ready to accept valid commands. Refer to 7.6 Commands on page 24. The value in the Cycle Count register (N) determines the number of output word rate (OWR) samples that are averaged during a calibration. DC offset and gain calibrations take at least N + TSETTLE samples. AC offset calibrations take at least 6(N) + TSETTLE samples. As N is increased, the accuracy of calibration results tends to also increase. The DRDY bit in the Status register will be set at the completion of Calibration commands. If an overflow occurs during calibration, other Status register bits may be set as well. Figure 11. System Calibration of Offset External Connections + AIN+ 0V + CM + AINXGAIN + 9.1.1.1 DC Offset Calibration The DC Offset Calibration command measures and averages DC values read on specified voltage or current channels at zero input and stores the inverse result in the associated offset registers. This will be added to instantaneous measurements in subsequent conversions, removing the offset. Gain registers for channels being calibrated should be set to 1.0 prior to performing DC offset calibration. 9.1.1.2 AC Offset Calibration The AC Offset Calibration command measures the residual RMS values read on specified voltage or current channels at zero input and stores the inverse result in the associated AC offset registers. This will be added to RMS measurements in subsequent conversions, removing the offset. AC offset registers for channels being calibrated should first be cleared prior to performing the calibration. 9.1.1 Offset Calibration During offset calibrations, no line voltage or current should be applied to the meter. A zero-volt differential signal can also be applied to the voltage inputs VIN± or current inputs IIN1± (IIN2±) of the CS5464. (see Figure 11.) V1, I1, V2, I2 In Modulator Filter + X X Σ N ÷N √ + + + RMS I1RMS, V1RMS, I2RMS, V2RMS I1DCOFF, V1DCOFF, I1GAIN, V1GAIN, I2DCOFF, V2DCOFF I2GAIN, V2GAIN Σ N I1ACOFF, V1ACOFF, I2ACOFF, V2ACOFF AC Offset DC Offset AC Gain DC Gain 1 DCAVG ÷N DC AVG Negate Negate 0.6 RMS = READABLE/WRITABLE REGISTERS. Figure 10. Calibration Data Flow DS682F1 39 CS5464 9.1.2 Gain Calibration During gain calibration, a full-scale reference signal must be applied to the meter or optionally, scaled to the VIN±, IIN1± (IIN2±) pins of the CS5464. A DC reference must be used for DC gain calibration. Either an AC or DC reference can be used for RMS AC calibrations. If DC is used, the associated high-pass filter (HPF) must be off. Figure 12 shows the basic setup for gain calibration. External Connections R eference + Signal - During AC gain calibration the RMS level of the applied reference is measured with the preset gain, then divided into 0.6 and the quotient stored back into the corresponding gain register. 9.1.2.2 DC Gain Calibration With a DC reference applied, the DC Gain Calibration command measures and averages DC values read on the specified voltage or current channels and stores the reciprocal result in the associated gain registers, converting measured voltage into needed gain. Subsequent conversions will use the new gain value. IN+ + XG AIN + - 9.1.3 Calibration Order 1. DC offset. 2. DC or AC gain. 3. AC offset (if needed). If both AC gain and offset calibrations were performed, it is possible to repeat both to obtain additional accuracy as AC gain and offset may interact. CM + - IN- Figure 12. System Calibration of Gain. Using a reference that is too large or too small can cause an over-range condition during calibration. Either condition can set Status register bits I1OR (I2OR) V1OR (V2OR) for DC and I1ROR (I2ROR) V1ROR (V2ROR) for AC calibration. Full scale (FS) for the voltage input is ±250mV peak and for the current inputs is ±250mV or ±50mV peak depending on selected gain range. The normal peak voltage applied to these pins should not exceed these levels during calibration or normal operation. The range of the gain registers limits the gain calibration range and subsequently the range of the reference level that can be applied. The reference should not exceed FS or be lower than FS/4. 9.1.4 Temperature Sensor Calibration Temperature sensor calibration involves the adjustment of two parameters - ∆VBE and VBE0. These values must be known in order to calibrate the temperature sensor. See Section 6.13 Temperature Measurement on page 21 for an explanation of ∆VBE and VBE0 and how to calculate TGAIN and TOFF register values from them. 9.1.4.1 Temperature Offset Calibration Offset calibration can be done at any temperature, but should be done mid-scale if any gain error exists. Subtract the measured T register temperature from the actual temperature to determine the offset error. Multiply this error by ∆VBE and add it to VBE0 to yield a new VBE0 value. Recalculate TOFF using this new value. 9.1.2.1 AC Gain Calibration Full scale for AC RMS gain calibrations is 60% of the input’s full-scale range, which is either 250mV or 50mV depending on the gain range selected. That’s 150mV or 30mV, again depending on range. So the normal reference input level should be either 150 or 30 mVRMS, AC or DC. Prior to executing an AC Gain Calibration command, gain registers for any channel to be calibrated should be set to 1.0 if the reference level mentioned above is used, or to that level divided by the actual reference level used. 9.1.4.2 Temperature Gain Calibration Two temperature points far enough apart to give reasonable accuracy, for example 25°C and 85°C, are required to calibrate temperature gain. Divide the actual temperature difference by the measured (T register) difference for the two temperatures. This gives a gain correction factor. Update the TGAIN register by multiplying it’s value by this correction factor. Update ∆VBE by dividing its old value by the gain correction factor. It will be needed for subsequent offset calibrations. 40 DS682F1 CS5464 10.E2PROM OPERATION The CS5464 can accept commands from a serial E2PROM connected to the serial interface instead of a host microcontroller. A high level (logic 1) on the MODE input indicates that an E2PROM is connected. This makes the CS and SCLK pins become driven outputs. After reset and after running the initialization program, the CS5464 begins reading commands from the connected E2PROM. 10.2 E2PROM Code The EEPROM code should do the following: 1. Set any Configuration or Control register bits, such as HPF enables and phase compensation settings. 2. Write any calibration data to gain and offset registers. 3. Set energy output pulse width, rate, and formats. 4. Execute a Continuous Conversion command. 5. Set the STOP bit in the Control register (last). Below is an example E2PROM code set. -7E 00 00 01 Change to page 1. -60 00 01 E0 Write Modes Register, turn high-pass filters on. -42 7F C4 A9 Write value of 0x7FC4A9 to I1GAIN register. -46 FF B2 53 Write value of 0xFFB253 to V1GAIN register. -50 7F C4 A9 Write value of 0x7FC4A9 to I2GAIN register. -54 FF B2 53 Write value of 0xFFB253 to V2GAIN register. -7E 00 00 00 Change to page 0. -74 00 00 04 Set LSD bit to 1 in the Mask register. -E8 Start continuous conversions -78 00 01 00 Write STOP bit to the Control register (Ctrl) to terminate E2PROM command sequence. 10.1 E2PROM Configuration A typical connection between the CS5464 and a E2PROM is shown in Figure 13. The CS5464 asserts CS (logic 0), clocks SCLK, and sends Read commands to the E2PROM on SDO. Command format is identical to microcontroller mode, except the CS5464 will not attempt to write to the EE device. The command sequence stops when the STOP bit in the Control register (Ctrl) is written by the command sequence. VD + 5K E1 E2 Pulse Output Counter CS5464 SCLK SDI SDO MODE CS 5K EEPROM SCK SO SI CS Connector to Calibrator Figure 13. Typical Interface of E2PROM to CS5464 Figure 13 also shows the external connections that would be made to a calibration device, such as a notebook computer, handheld calibrator, or tester during meter assembly, The calibrator or tester can be used to control the CS5464 during calibration and program the required values into the E2PROM. 10.3 Which E2PROMs Can Be Used? Several industry-standard serial E2PROMs can be used with the CS5464. Some are listed below: • • • Atmel AT25010, AT25020 or AT25040 National Semiconductor NM25C040M8 or NM25020M8 Xicor X25040SI These serial E2PROMs expect a specific 8-bit command (00000011) in order to perform a memory read. The CS5464 has been hardware programmed to transmit this 8-bit command to the E2PROM after reset. DS682F1 41 CS5464 11. BASIC APPLICATION CIRCUITS Figure 14 shows the CS5464 configured to measure power in a single-phase, 2-wire system while operating in a single-supply configuration. In this diagram, a shunt resistor is used to sense the line current and a voltage divider is used to sense the line voltage. In this type of shunt-resistor configuration, the common-mode level of the CS5464 must be referenced to the line side of the power line. This means that the common-mode potential of the CS5464 will track the high-voltage levels, as well as low-voltage levels, with respect to earth ground. Isolation circuitry is required when an earth-ground-referenced communication interface is connected. A current transformer (CT) is connected to the return line current, which implements the tamper detection circuit. 5 kW L2 LINE VOLTAGE 10 kW L1 500 W 1uF 500 W 470µF 0.1µF 10 W 0.1 µF 18 VA+ 3 VD+ 21 PFMON 2 CPUCLK 1 XOUT 28 CS5464 9 C V+ R2 R1 VIN+ CVdiff R VCV10 19 R IR Shunt C I+ R I+ R I½ R Burden C IC Idiff C I+ 16 RI+ 12 11 4.096 MHz Optional Clock Source VINIIN- XIN C IC Idiff RESET 23 ISOLATION (Optional) Serial Data Interface 20 15 IIN+ IIN2- CT 7 CS 27 SDI 6 SDO 5 SCLK 24 INT 26 E2 25 E1 ½ R Burden IIN2+ VREFIN VREFOUT AGND 17 13 TEST1 14 TEST2 DGND 4 Pulse Output Counter LOAD 0.1µF Figure 14. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line) 42 DS682F1 CS5464 12. PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING N D E11 A2 A1 A E ∝ L e b2 SIDE VIEW END VIEW SEATING PLANE 123 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4° MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.15 1.75 -10.20 7.80 5.30 0.65 0.90 4° NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8° 2,3 1 1 JEDEC #: MO-150 Controlling Dimension is Millimeters Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch 2. and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. DS682F1 43 CS5464 13. ORDERING INFORMATION Model Temperature Package CS5464-IS CS5464-ISZ (lead free) -40 to +85 °C 28-pin SSOP 14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp 240 °C 260 °C MSL Rating* 2 3 Max Floor Life 365 Days 7 Days CS5464-IS CS5464-ISZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 44 DS682F1 CS5464 15. REVISION HISTORY Revision T1 PP1 PP2 F1 Date NOV 2005 MAR 2006 JAN 2007 MAR 2007 Target Data Sheet Preliminary Release Update to correspond to rev C1 Silicon Updated capitalization of register names for consistency with CS5467. Updated Typical Connection diagram. Updated Phase Compensation Range from ±2.8° to ±5.4°. Updated document number to F1 for quality process level (QPL). Changes DS682F1 45 CS5464 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 46 DS682F1