CS5571-ISZ

6/25/07 14:12 CS5571 ±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ∆Σ ADC Features & Description Single-ended Analog Input On-chip Buffers for High Input Impedance Conversion Time = 10 µS Settles in One Conversion Linearity Error = 0.0007% Signal-to-Noise = 92 dB S/(N + D) = 91 dB DNL = ±0.1 LSB Max. Self-calibration: - Maintains accuracy over time & temperature. General Description The CS5571 is a single-channel, 16-bit analog-to-digital converter capable of 100 kSps conversion rate. The input accepts a single-ended analog input signal. On-chip buffers provide high input impedance for both the AIN input and the VREF+ input. This significantly reduces the drive requirements of signal sources and reduces errors due to source impedances. The CS5571 is a delta-sigma converter capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in one conversion. The converter's 16-bit data output is in serial format, with the serial port acting as either a master or a slave. The converter is designed to support bipolar, ground-referenced signals when operated from ±2.5V analog supplies. The CS5571 uses self-calibration to achieve low offset and gain errors. The converter achieves a S/N of 92 dB. Linearity is 0.0007% of full scale. The converter can operate from an analog supply of 0-5V or from ±2.5V. The digital interface supports standard logic operating from 1.8, 2.5, or 3.3 V. ORDERING INFORMATION: See Ordering Information on page 31. VL Simple three/four-wire serial interface Power Supply Configurations: - Analog: +5V/GND; IO: +1.8V to +3.3V - Analog: ±2.5V; IO: +1.8V to +3.3V Power Consumption: - ADC Input Buffers On: 85 mW - ADC Input Buffers Off: 60 mW V1+ V2+ CS5571 VREF+ VREFDIGITAL FILTER LOGIC SERIAL INTERFACE SMODE CS SCLK ADC AIN ACOM SDO RDY BUFEN OSC/CLOCK GENERATOR CALIBRATION MICROCONTROLLER DITHER RST CONV CAL BP/UP MCLK V1- V2- TST DCR VLR A dvance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) JUN ‘07 DS768A5 6/25/07 14:12 CS5571 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DIGITAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DIGITAL FILTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 GUARANTEED LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Reset and Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Performing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 Output Coding Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 AIN & VREF Sampling Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 Converter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 Using the CS5571 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4. PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . 31 8. REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2 DS768A5 6/25/07 14:12 CS5571 LIST OF FIGURES Figure 1. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. SSC Mode - Read Timing, CS falling after RDY falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. SEC Mode - Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. CS5571 Configured Using ±2.5V Analog Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. CS5571 Configured for Unipolar Measurement Using a Single 5V Analog Supply . . . . 18 Figure 7. CS5571 Configured for Bipolar Measurement Using a Single 5V Analog Supply . . . . . 19 Figure 8. CS5571 DNL Plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. CS5571 DNL Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10. CS5571 Small Signal Performance (Dither On). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11. CS5571 Small Signal Performance (Dither Off). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12. CS5571 Spectral Response (DC to fs/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. CS5571 Spectral Response (DC to 10 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14. CS5571 Spectral Response (DC to 4fs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15. Simple Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 16. More Complex Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LIST OF TABLES Table 1. Output Coding, Two’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2. Output Coding, Offset Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DS768A5 3 6/25/07 14:12 1. CHARACTERISTICS AND SPECIFICATIONS • • • CS5571 Min / Max characteristics and specifications are guaranteed over the specified operating conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. VLR = 0 V. All voltages measured with respect to 0 V. TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL. DITHER = VL unless otherwise stated; BUFEN = V1+ unless otherwise stated. Connected per Figure 5. Bipolar mode unless otherwise stated. Parameter Accuracy Linearity Error Differential Linearity Error Positive Full-scale Error Negative Full-scale Error Full-scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift Noise Dynamic Performance Peak Harmonic or Spurious Noise Total Harmonic Distortion Signal-to-Noise S/(N + D) Ratio -3 dB Input Bandwidth 1. 2. 3. 4. 5. ANALOG CHARACTERISTICS Min After Reset After Calibration (Note 1) After Reset After Calibration (Note 1) After Reset After Calibration (Note 1) After Reset After Calibration (Note 1) 1 kHz, -0.5 dB Input 12 kHz, -0.5 dB Input 1 kHz, -0.5 dB Input -0.5 dB Input, 1 kHz -60 dB Input, 1 kHz - Typ 0.0007 1.0 1.0 ±1 Max ±0.1 - Unit ±%FS LSB16 %FS LSB16 %FS LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 µVrms dB dB dB dB dB dB kHz (Note 1) (Note 2) (Note 3) (Note 3) ±2 - (Note 3) (Note 4) ±1 36 -110 -110 -102 92 91 32 84 - (Note 5) Applies after calibration at any temperature within -40 °C to +85 °C. No missing codes is guaranteed at 16 bits resolution over the specified temperature range. Total drift over specified temperature range after calibration at power-up, at 25º C. With DITHER off the output will be dominated by quantization. Scales with MCLK. 4 DS768A5 6/25/07 14:12 ANALOG CHARACTERISTICS (CONTINUED) CS5571 TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL. DITHER = VL unless otherwise stated; BUFEN = V1+ unless otherwise stated. Connected per Figure 5. Parameter Analog Input Analog Input Range Input Capacitance CVF Current (Note 6) AIN Buffer On (BUFEN = V+) AIN Buffer Off (BUFEN = V-) ACOM Unipolar Bipolar 0 to +VREF / 2 ±VREF / 2 10 600 130 130 V V pF nA µA µA Min Typ Max Unit Voltage Reference Input Voltage Reference Input Range (VREF+) – (VREF-) Input Capacitance CVF Current VREF+ Buffer On (BUFEN = V+) VREF+ Buffer Off (BUFEN = V-) VREFIV1 IV2 IVL Normal Operation Buffers On Buffers Off (Note 8) V1+ , V2+ Supplies V1-, V2- Supplies (Note 7) 2.4 90 90 4.096 10 3 1 1 85 60 110 110 4.2 18 1.8 0.5 105 90 V pF µA mA mA mA mA mA mW mW dB dB Power Supplies DC Power Supply Currents Power Consumption Power Supply Rejection 6. 7. 8. Measured using an input signal of 1 V DC. For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer. Tested with 100 mVP-P on any supply up to 1 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at the same voltage potential. DS768A5 5 6/25/07 14:12 SWITCHING CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF. Parameter Master Clock Frequency Master Clock Duty Cycle Reset RST Low Time RST rising to RDY falling Calibration CAL pulse width CAL high setup time to RST rising Calibration Time RST rising (CAL high) to RDY falling Calibration Time CAL rising (RST high) to RDY falling Conversion CONV Pulse Width BP/UP setup to CONV falling CONV low to start of conversion Perform Single Conversion (CONV high before RDY falling) Conversion Time 9. 10. 11. CS5571 Symbol Internal Oscillator External Clock XIN fclk Min 12 0.5 40 Typ 14 16 120 1536 167298 167298 - Max 16 16.2 60 2 164 Unit MHz MHz % µs µs MCLKs MCLKs ns MCLKs MCLKs MCLKs ns MCLKs MCLKs MCLKs (Note 9) Internal Oscillator External Clock (Note 10, 11) (Note 10, 11) tres twup 1 4 0 - tpw tccw tscl tcal tcpw (Note 12) tscn tscn tbus tbuh 4 0 20 - (Note 13) Start of Conversion to RDY falling Reset must not be released until the power supplies and the voltage reference are within specification. CAL must remain high until RDY falls at the end of the calibration time. CAL can be controlled by the same signal used for RST. If CAL goes high simultaneously with RST, a calibration will be performed. CAL must remain high until RDY falls. 12. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls. 13. If CONV is held low continuously, conversions occur every 160 MCLK cycles. If RDY is tied to CONV, conversions will occur every 162 MCLKs. If CONV is operated asynchronously to MCLK, a conversion may take up to 164 MCLKs. RDY falls at the end of conversion. 6 DS768A5 6/25/07 14:12 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF. Parameter Serial Port Timing in SSC Mode (SMODE = VL) RDY falling to MSB stable Data hold time after SCLK rising Serial Clock (Out) (Note 14, 15) RDY rising after last SCLK rising 14. 15. CS5571 Symbol t1 t2 Pulse Width (low) Pulse Width (high) t3 t4 t5 Min 50 50 - Typ -2 10 8 Max - Unit MCLKs ns ns ns MCLKs SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resister. SCLK = MCLK/2. MCLK RDY t1 CS t2 SCLK(o) t3 t4 t5 SDO MSB MSB–1 LSB+1 LSB Figure 1. SSC Mode - Read Timing, CS remaining low (Not to Scale) DS768A5 7 6/25/07 14:12 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF. Parameter Serial Port Timing in SSC Mode (SMODE = VL) Data hold time after SCLK rising Serial Clock (Out) (Note 16, 17) RDY rising after last SCLK rising CS falling to MSB stable First SCLK rising after CS falling CS hold time (low) after SCLK rising SCLK, SDO tri-state after CS rising 16. 17. CS5571 Symbol t7 Pulse Width (low) Pulse Width (high) t8 t9 t10 t11 t12 t13 t14 Min 50 50 10 - Typ 10 8 10 8 5 Max - Unit ns ns ns MCLKs ns MCLKs ns ns SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resister. SCLK = MCLK/2. MCLK t10 RDY t13 CS t12 SCLK(o) t11 SDO MSB MSB–1 LSB+1 LSB t7 t8 t9 t14 Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale) 8 DS768A5 6/25/07 14:12 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF. Parameter Serial Port Timing in SEC Mode (SMODE = VLR) SCLK(in) Pulse Width (High) SCLK(in) Pulse Width (Low) CS hold time (high) after RDY falling CS hold time (high) after SCLK rising CS low to SDO out of Hi-Z Data hold time after SCLK rising Data setup time before SCLK rising CS hold time (low) after SCLK rising RDY rising after SCLK falling 18. - CS5571 Symbol Min 30 30 10 10 10 10 - Typ 10 10 10 Max - Unit ns ns ns ns ns ns ns ns ns t15 t16 (Note 18) t17 t18 t19 t20 t21 SDO will be high impedance when CS is high. In some systems it may require a pull-down resister. MCLK t21 RDY t15 CS t16 SCLK(i) t17 SDO MSB t20 t18 t19 LSB Figure 3. SEC Mode - Read Timing (Not to Scale) DS768A5 9 6/25/07 14:12 DIGITAL CHARACTERISTICS TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V Parameter Calibration Memory Retention Power Supply Voltage [V1+ = V2+] – [V1- = V2-] Input Leakage Current Digital Input Pin Capacitance Digital Output Pin Capacitance 19. CS5571 Symbol (Note 19) VMR Iin Cin Cout Min 4.0 - Typ 3 3 Max 2 - Unit V µA pF pF V1- and V2- can be any value from 0 to +5V for memory retention. Neither V1- nor V2- should be allowed to go positive. AIN1, AIN2, or VREF must not be greater than V1+ or V2+. This parameter is guaranteed by characterization. DIGITAL FILTER CHARACTERISTICS TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V Parameter Group Delay Symbol Min Typ 160 Max Unit MCLKs 10 DS768A5 6/25/07 14:12 GUARANTEED LOGIC LEVELS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V; Logic 1 = VL; CL = 15 pF. Guaranteed Limits Parameter Logic Inputs 3.3 Minimum High-level Input Voltage: CS5571 Sym VL Min Typ Max Unit Conditions 1.9 1.6 1.2 1.1 0.95 0.6 V V VIH 2.5 1.8 3.3 Maximum Low-level Input Voltage: VIL 2.5 1.8 Logic Outputs 3.3 Minimum High-level Output Voltage: 2.9 2.1 1.65 0.36 0.36 0.44 V IOH = -2 mA VOH 2.5 1.8 3.3 V IOH = -2 mA Maximum Low-level Output Voltage: VOL 2.5 1.8 DS768A5 11 6/25/07 14:12 RECOMMENDED OPERATING CONDITIONS (VLR = 0V, see Note 20) CS5571 Parameter Single Analog Supply DC Power Supplies: (Note 20) V1+ V2+ V1V2- Symbol Min Typ Max Unit V1+ V2V1+ V2- 4.75 4.75 - 5.0 5.0 0 0 5.25 5.25 - V V V V Dual Analog Supplies DC Power Supplies: (Note 20) V1+ V2+ V1V2(Note 21) [VREF+] – [VREF-] V1+ V2V1+ V2VREF +2.375 +2.375 -2.375 -2.375 2.4 +2.5 +2.5 -2.5 -2.5 4.096 +2.625 +2.625 -2.625 -2.625 4.2 V V V V V Analog Reference Voltage 20. 21. The logic supply can be any value VL – VLR = +1.71 to +3.465 volts as long as VLR ≥ V2- and VL ≤ 3.465 V. The differential voltage reference magnitude is constrained by the V1+ or V1- supply magnitude. ABSOLUTE MAXIMUM RATINGS (VLR = 0V) Parameter DC Power Supplies: [V1+] – [V1-] (Note 22) VL + [ |V1-| ] (Note 23) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Storage Temperature Notes: 22. V1+ = V2+; V1- = V223. 24. Symbol IIN VINA VIND Tstg Min 0 0 (V1-) – 0.3 VLR – 0.3 -65 Typ - Max 5.5 6.1 ±10 (V1+) + 0.3 VL + 0.3 150 Unit V V mA V V °C (Note 24) (AIN and VREF pins) V1- = V2Transient currents of up to 100 mA will not cause SCR latch-up. WARNING: Recommended Operating Conditions indicate limits to which functional operation of the device is guaranteed. Absolute Maximum Ratings indicate limits beyond which permanent damage to the device may occur. The Absolute Maximum Ratings are stress ratings only and the device should not be operated at these limits. Operation at conditions beyond the Recommended Operating Conditions may affect device reliability; functional operation beyond Recommended Operating Conditions is not implied. Performance specifications are guaranteed under the conditions specified for each table in the Characteristics and Specifications section. 12 DS768A5 6/25/07 14:12 2. OVERVIEW CS5571 The CS5571 is a 16-bit analog-to-digital converter capable of 100 kSps conversion rate. The analog input accepts a single-ended input with a magnitude of ±VREF / 2 volts. The device is capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in one conversion. The converter is a serial output device. The serial port can be configured to function as either a master or a slave. The CS5571 provides self-calibration circuitry to achieve low offset and gain errors. The converter can operate from an analog supply of 5V or from ±2.5V. The digital interface supports standard logic operating from 1.8, 2.5, or 3.3 V. The CS5571 may convert at rates up to 100 kSps when operating from a 16 MHz input clock. 3. THEORY OF OPERATION The CS5571 converter provides high-performance measurement of DC or AC signals. The converter includes on-chip calibration circuitry to minimize offset and gain errors. The converter can be used to perform single conversions or continuous conversions upon command. Each conversion is independent of previous conversions and settles to full specified accuracy, even with a full-scale input voltage step. This is due to the converter architecture which uses a combination of a high-speed delta-sigma modulator and a low-latency filter architecture. Once power is established to the converter, a reset must be performed. A reset initializes the internal converter logic and sets the offset register to zero and the gain register to a decimal value of 1.0. If the CAL pin is low when RST returns high, no calibration will be performed. If CAL is high when RST transitions from low to high, the converter’s offset & gain slope will be calibrated. If CONV is held low then the converter will convert continuously with RDY falling every 160 MCLKs. This is equivalent to 100 kSps if MCLK = 16.0 MHz. If CONV is tied to RDY, a conversion will occur every 162 MCLKs. If CONV is operated asynchronously to MCLK, it may take up to 164 MCLKs from CONV falling to RDY falling. Multiple converters can operate synchronously if they are driven by the same MCLK source and CONV to each converter falls on the same MCLK falling edge. Alternately, CONV can be held low and all devices are reset with RST rising on the same falling edge of MCLK. The output coding of the conversion word is a function of the BP/UP pin. 3.1 Reset and Calibration After the power supplies and the voltage reference are stable, the converter must be reset. The reset function initializes the internal logic in the converter, but does not initiate calibration. After reset has been performed, the converter can be used uncalibrated, or calibration can be performed. Calibration minimizes offset and gain errors inside the converter. If the device is used without calibration, conversions will include the offset and gain errors of the uncalibrated converter, but the converter will maintain its differential and integral linearity. Calibration of offset and gain can be performed upon command. Calibration can be initiated in either of two ways. If CAL is high when RST transitions from low to high a calibration cycle will be performed immediately after a reset is performed. When calibration is performed, the offset and full-scale points of the converter are calibrated. A calibration cycle takes 327,680 MCLK DS768A5 13 6/25/07 14:12 CS5571 cycles. The RDY signal falls upon completion of reset and calibration sequence. If CAL remains low when RST transitions from low to high, no calibration will be performed. Calibrations can be initiated any time the converter is idle by taking the CAL input high. RDY will fall at the end of the calibration cycle. The CAL pin should be returned low when not being used. A calibration cycle calibrates the offset and full-scale points of the converter transfer function. When the offset portion of the calibration is performed, the AIN and ACOM pins are disconnected from the input and shorted internally. The offset of the converter is then measured and a correction factor is stored in a register. Then the voltage reference is internally connected to act as the input signal to the converter and a gain calibration is performed. The gain correction results are also placed in a register. The contents of the offset and gain registers are used to map the conversion data prior to its output from the converter. 3.2 Performing Conversions The CS5571 converts at 100 kSps when synchronously operated (CONV = VLR) from a 16.0 MHz master clock. Conversion is initiated by taking CONV low. A conversion lasts 160 master clock cycles, but if CONV is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to when a conversion actually begins. This may extend the throughput to 164 MCLKs per conversion. When the conversion is completed, the output word is placed into the serial port and RDY goes low. To convert continuously, CONV should be held low. In continuous conversion mode with CONV held low, a conversion is performed in 160 MCLK cycles. Alternately RDY can be tied to CONV and a conversion will occur every 162 MCLK cycles. To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY falls. Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data is put into the port register. See Serial Port on page 23 for information about reading conversion data. Conversion performance can be affected by several factors. These include the choice of clock source for the chip, the timing of CONV, the setting of the DITHER function, and the choice of the serial port mode. The converter can be operated from an internal oscillator. This clock source has greater jitter than an external crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-frequency AC signals, but can become an issue for higher frequency AC signals. For maximum performance when digitizing AC signals, a low-jitter MCLK should be used. To achieve the highest resolution when measuring a DC signal with a single conversion the DITHER function should be off. If averaging is to be performed with multiple conversions of a DC signal, DITHER should be on. To maximize performance, the CONV pin should be held low in the continuous conversion state to perform multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK falls. When performing conversions on an AC signal, CONV should be held low in the continuous conversion state to perform multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK falls. If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause interference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interfer14 DS768A5 6/25/07 14:12 CS5571 ence due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a conversion is not is progress. 3.3 Clock The CS5571 can be operated from its internal oscillator or from an external master clock. The state of MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and be used as the clock source for the converter. If an external CMOS-compatible clock is input into MCLK, the converter will power down the internal oscillator and use the external clock. If the MCLK pin is held high, the internal oscillator will be held in the stopped state. The MCLK input can be held high to delete clock cycles to aid in operating multiple converters in different phase relationships. The internal oscillator can be used if the signals to be measured are essentially DC. The internal oscillator exhibits jitter at about 500 picoseconds rms. If the CS5571 is used to digitize AC signals, an external low-jitter clock source should be used. If the internal oscillator is used as the clock for the CS5571, the maximum conversion rate will be dictated by the oscillator frequency. 3.4 Voltage Reference The voltage reference for the CS5571 can range from 2.4 volt to 4.2 volts. A 4.096 volt reference is required to achieve the specified signal-to-noise performance. Figure 5 and Figure 6 illustrate the connection of the voltage reference with either a single +5 V analog supply or with ±2.5 V. For optimum performance, the voltage reference device should be one that provides a capacitor connection to provide a means of noise filtering, or the output should include some type of bandwidth-limiting filter. Some 4.096 volt reference devices need only 5 volts total supply for operation and can be connected as shown in Figure 5 or Figure 6. The reference should have a local bypass capacitor and an appropriate output capacitor. Some older 4.096 voltage reference designs require more headroom and must operate from an input voltage of 5.5 to 6.5 volts. If this type of voltage reference is used ensure that when power is applied to the system, the voltage reference rise time is slower than the rise time of the V1+ and V1- power supply voltage to the converter. An example circuit to slow the output startup time of the reference is illustrated in Figure 4. 5.5 to 15 V 2k 10µF VIN VOUT GND Refer to V1- and VREF1 pins. 4.096 V Figure 4. Voltage Reference Circuit DS768A5 15 6/25/07 14:12 3.5 Analog Input CS5571 The analog input of the converter is single-ended with an full-scale input of ±2.048 volts. This is illustrated in Figure 5 and Figure 6. These diagrams also illustrate a differential buffer amplifier configuration for driving the CS5571. The capacitors at the outputs of the amplifiers provide a charge reservoir for the dynamic current from the A/D inputs while the resistors isolate the dynamic current from the amplifier. The amplifiers can be powered from higher supplies than those used by the A/D but precautions should be taken to ensure that the op-amp output voltage remains within the power supply limits of the A/D, especially under start-up conditions. 3.6 Output Coding Format The reference voltage directly defines the input voltage range in both the unipolar and bipolar configurations. In the unipolar configuration (BP/UP low), the first code transition occurs 0.5 LSB above zero, and the final code transition occurs 1.5 LSBs below VREF. In the bipolar configuration (BP/UP high), the first code transition occurs 0.5 LSB above -VREF and the last transition occurs 1.5 LSBs below +VREF. See Table 1 for the output coding of the converter. Table 1. Output Coding, Two’s Complement Bipolar Input Voltage >(VREF-1.5 LSB) VREF-1.5 LSB 7F FE 00 00 -0.5 LSB FF FF 80 01 -VREF+0.5 LSB 80 00 (VREF-1.5 LSB) VREF-1.5 LSB FF FE 80 00 (VREF/2)-0.5 LSB 7F FF 00 01 +0.5 LSB 00 00