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VRE3050A

VRE3050A

  • 厂商:

    CIRRUS(凌云)

  • 封装:

  • 描述:

    VRE3050A - Precision Voltage Reference - Cirrus Logic

  • 数据手册
  • 价格&库存
VRE3050A 数据手册
P r o d u c t IIn n o vva t i o n FF r o m rom nno a VRE3050 VRE3050 DESCRIPTION Precision Voltage Reference FEaTuRES ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ +5 V Output, ± 0.5 mV (.01%) Temperature Drift: 0.6 ppm/ºC Low Noise: 3 μVP-P (0.1Hz-10Hz) Low Thermal Hysterisis: 1 ppm Typical ±15mA Output Source and Sink Current Excellent Line Regulation: 5 ppm/V Typical Optional Noise Reduction and Voltage Trim Industry Standard Pinout: 8-pin Surface Mount Package The VRE3050 is a low cost, high precision 5 V reference that operates from +10 V. The device features a buried zener for low noise and excellent long term stability. Packaged in an 8-pin SMT, the device is ideal for high resolution data conversion systems. The device provides ultrastable +5 V output with ±0.5 mV (.01%) initial accuracy and a temperature coefficient of 0.6 ppm/°C. This improvement in accuracy is made possible by a unique, patented multipoint laser compensation technique. Significant improvements have been made in other performance parameters as well, including initial accuracy, warm-up drift, line regulation, and long-term stability, making the VRE3050 series the most accurate reference available. For enhanced performance, the VRE3050 has an external trim option for users who want less than 0.01% initial error. For ultra low noise applications, an external capacitor can be attached between the noise reduction pin and the ground pin. aPPlICaTIONS The VRE3050 is recommended for use as a reference for 14, 16, or 18 bit data converters which require an external precision reference. The device is also ideal for calibrating scale factor on high resolution data converters. The VRE3050 offers superior performance over monolithic references. Figure . BlOCK DIaGRaM 8 2 + R1 R4 R2 R3 5 - 6 4 SElECTION GuIDE Model VRE3050A VRE3050B VRE3050C VRE3050J VRE3050K VRE3050L Initial Error Temp. Coeff. (mV) (ppm/ºC) ±0.5 ±0.8 ±1.0 ±0.5 ±0.8 ±1.0 0.6 1.0 2.0 0.6 1.0 2.0 Temp. Range (ºC) 0ºC to +70ºC 0ºC to +70ºC 0ºC to +70ºC -40ºC to +85ºC -40ºC to +85ºC -40ºC to +85ºC 8-pin Surface Mount Package Style GF VRE3050DS http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2009 (All Rights Reserved) MaR 2009  APEX − VRE3050DSREVF VRE3050 P r o d u c t I n n o v a t i o nF r o m . ChaRaCTERISTICS aND SPECIFICaTIONS aBSOluTE MaXIMuM RaTINGS Power Supply ........................... -0.3V to +40V OUT, TRIM................................ -0.3V to +12V NR .............................................. -0.3V to +6V Operating Temp. (A,B,C) ........... 0ºC to +70ºC Operating Temp. (J,K,L) ......... -40ºC to +85ºC Out Short Circuit to GND Duration (VIN< 12V) ........... Continuous Out Short Circuit to GND Duration (VIN< 40V) ..................... 5 sec Out Short Circuit to IN Duration (VIN< 12V) ............... Continuous Continuous Power Dissipation (TA = +70ºC) .................... 300mW Storage Temperature ......................................... -65ºC to +150ºC Lead Temperature (soldering,10 sec) .............................. +250ºC ElECTRICal SPECIFICaTIONS Parameter Input Voltage Output Voltage (Note 1) Output Voltage Temperature Coefficient (Note 2) Trim Adjustment Range Turn-On Settling Time Output Noise Voltage Temperature Hysterisis Long Term Stability Supply Current ∆VOUT/t IIN Symbol VIN VPS =±15V, T = +25ºC, RL = 10KΩ Unless Otherwise Noted. Conditions VRE3050A/J VOUT VRE3050B/K VRE3050C/L VRE3050A/J TCVOUT ∆VOUT TON en VRE3050B/K VRE3050C/L Figure 3 To 0.01% of final value 0.1Hz < f < 10Hz 10Hz < f < 1kHz Note 4 Min +8 +2.4995 +2.4992 +2.4990 +5.0000 +5.0000 +5.0000 0.3 0.5 1.0 ±5.0 2.0 3.0 2.5 1 6 3.5 Sourcing: 0mA ≤ IOUT ≤ 15mA Sinking: -15mA ≤ IOUT ≤ 0mA 8V ≤ VIN ≤ 10V 10V ≤ VIN ≤ 18V 8 8 25 5 4.0 12 12 35 10 5.0 Typ Max +36 +5.0005 +5.0008 +5.0010 0.6 1.0 2.0 mV µs µVp-p µVRMS ppm ppm/1000hrs. mA ppm/mA ppm/V ppm/ºC V units V Load Regualtion (Note 3) ∆VOUT/ ∆IOUT Line Regulation (Note 3) ∆VOUT/ ∆VIN NOTES: 1. The specified values are without external trim. 2. The temperature coefficient is determined by the box method. See discussion on temperature performance. 3. Line and load regulation are measured with pulses and do not include voltage changes due to temperature. 4. Hysterisis over the operating temperature range. 2 VRE3050DS P r o d u c t I n n o v a t i o nF r o m VRE3050 2. TYPICal PERFORMaNCE CuRVES VOUT vs. TEMPERATURE 1.00 0.75 0.50 1.00 0.75 0.50 VOUT vs. TEMPERATURE 1.00 0.75 0.50 VOUT vs. TEMPERATURE U p pe r Lim it ∆Vout (mV) 0.25 0 -0.25 -0.50 -0.75 -1.00 0 ∆Vout (mV) ∆Vout (mV) U p U p pe r LLm i t p er i im t 0.25 0 -0.25 -0.50 -0.75 -1.00 U p pe r Lim it 0.25 0 -0.25 -0.50 -0.75 -1.00 Lo wer Lim it L o woe re r LLm ii tt Lw i im Lo wer Lim it 20 30 40 50 60 70 0 20 30 40 50 60 70 0 20 30 40 50 60 70 Temperature (oC) VRE3050A VOUT vs. TEMPERATURE 2.0 1.5 1.0 Up per Lim it Temperature (oC) VRE3050B VOUT vs. TEMPERATURE 2.0 1.5 1.0 Up per Lim it Temperature (oC) VRE3050C VOUT vs. TEMPERATURE 2.0 1.5 1.0 Up per Lim it ∆Vout (mV) ∆Vout (mV) 0 -0.5 -1.0 -1.5 -2.0 -50 -25 L o we r Lim it 0 -0.5 -1.0 -1.5 -2.0 -50 -25 L o we r Lim it ∆Vout (mV) 0.5 0.5 0.5 0 -0.5 -1.0 -1.5 -2.0 -50 -25 L o we r Lim it 0 25 50 75 100 0 25 50 75 100 0 25 50 75 100 Temperature (oC) VRE3050J SUPPLY CURRENT VS. SUPPLY VOLTAGE 6.0 Temperature (oC) VRE3050K QUIESCENT CURRENT VS. TEMP 8.0 Temperature (oC) VRE3050L OUTPUT IMPEDIANCE VS. FREQUENCY Output Impediance ( Ω) Quiescent Current (mA) Supply Current (mA) 5.0 4.0 6.0 4.0 2.0 0 3.0 0 0 5 10 15 20 25 30 35 40 -50 0 50 100 Supply Voltage (V) Temperature (oC) Frequency (Hz) VRE3050DS 3 VRE3050 JUNCTION TEMP. RISE VS. OUTPUT CURRENT Ripple Rejection (dB) P r o d u c t I n n o v a t i o nF r o m 40 100 90 80 RIPPLE REJECTION Vs. FREQUENCY(CNR=0µF) A TURN-ON AND TURN-OFF TRANSIENT RESPONSE +10V 0V Junction Temperature Rise Above Ambient (oC) 30 20 V 10 0 cc = 10 V 70 60 10 B A: Vin, 10V/div B : V o u t , 1 V / di v 1 µs/div CHANGE IN OUTPUT VOLTAGE VS. INPUT VOLTAGE 0 2 4 6 8 10 100 1k 10k Output Current (mA) OUTPUT NOISE-VOLTAGE DENSITY vs. FREQUENCY Output Noise Density (nV/√Hz) 100 80 Frequency (Hz) CHANGE IN OUTPUT VOLTAGE VS. OUTPUT CURRENT 400 300 100 0 -100 -200 -300 -400 200 60 50 40 30 20 10 0 -10 02 4 6 8 10 12 14 16 60 40 20 10 Vout (ppm) Vout (µV) 100 1k 10k -20 0 9 10 11 12 13 14 15 16 Frequency (Hz) Iout(mA) 0.1Hz to 10Hz Noise Vin(V) ∆Vout, 1µV/Div 1 Sec/Div  VRE3050DS P r o d u c t I n n o v a t i o nF r o m VRE3050 3. ThEORY OF OPERaTION The following discussion refers to the block diagram in Figure 1. A FET current source is used to bias a 6.3 V zener diode. The zener voltage is divided by the resistor network R1 and R2. This voltage is then applied to the noninverting input of the operational amplifier which amplifies the voltage to produce a 5 V output. The gain is determined by the resistor networks R3 and R4: G=1 + R4/R3. The 6.3 V zener diode is used because it is the most stable diode over time and temperature. The current source provides a closely regulated zener current, which determines the slope of the references’ voltage vs. temperature function. By trimming the zener current a lower drift over temperature can be achieved. But since the voltage vs. temperature function is nonlinear this compensation technique is not well suited for wide temperature ranges. A nonlinear compensation network of thermistors and resistors that is used in the VRE series voltage references. This proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By adjusting the slope, a very stable voltage is produced over wide temperature ranges. This network is less than 2% of the overall network resistance so it has a negligible effect on long term stability. The proper connection of the VRE3050 series voltage references with the optional trim resistor for initial error and the optional capacitor for noise reduction is shown below. EXTERNal CONNECTIONS + VIN 2 Optional Noise Reduction Capacitor CN 1µF 8 6 VRE3050 4 5 + VOUT 10kΩ Optional Fine Trim Adjustment PIN DESCRIPTION 1, 3, 7 2 4 5 6 8 N. C. VIN GND TRIM OUT NR Internally connected. Do not use Positive power supply input Ground External trim input. Leave open if not used. Voltage reference output Noise Reduction . BaSIC CIRCuIT CONNECTION To achieve the specified performance, pay careful attention to the layout. A low resistance star configuration will reduce voltage errors, noise pickup, and noise coupled from the power supply. Commons should be connected to a single point to minimize interconnect resistances. VRE3050DS 5 VRE3050 Figure 3. 10000 1000 P r o d u c t I n n o v a t i o nF r o m Reference TC (ppm/ºC 100 8 BIT 10 10 BIT 12 BIT 1 14 BIT 16 BIT 18 BIT 0.01 1 10 20 BIT 100 0.1 Reference TC vs. ∆T change from 25°C for 1 LSB change 5. TEMPERaTuRE PERFORMaNCE The VRE3050 is designed for applications where the initial error at room temperature and drift over temperature are important to the user. For many instrument manufacturers, a voltage reference with a temperature coefficient less than 1 ppm/°C makes it possible to not perform a system temperature calibration, a slow and costly process. Of the three TC specification methods (slope, butterfly, and box), the box method is most commonly used. A box is formed by the min/max limits for the nominal output voltage over the operating temperature range. The equation follows: VMAX – VMIN T.C. = x 106 VNOMINAL x (TMAX – TMIN) This method corresponds more accurately to the method of test and provides a closer estimate of actual error than the other methods. The box method guarantees limits for the temperature error but does not specify the exact shape and slope of the device under test. A designer who needs a 14-bit accurate data acquisition system over the industrial temperature range (-40°C to +85°C), will need a voltage reference with a temperature coefficient (TC) of 1 ppm/°C if the reference is allowed to contribute an error equivalent to 1LSB. For 1/2LSB equivalent error from the reference you would need a voltage reference with a temperature coefficient of 0.5 ppm/°C. Figure 4 shows the required reference TC vs. delta T change from 25°C for resolution ranging from 8 bits to 20 bits. . ThERMal hYSTERISIS A change in output voltage as a result of a temperature change. When references experience a temperature change and return to the initial temperature, they do not always have the same initial voltage. Thermal hysterisis is difficult to correct and is a major error source in systems that experience temperature changes greater than 25°C. Reference vendors are starting to include this important specification in their datasheets. PIN CONFIGuRaTION N/C +VIN N/C GND 1 2 3 4 VRE3050 TOP VIEW 8 7 6 5 NOISE REDUCTION N/C VOUT TRIM  VRE3050DS P r o d u c t I n n o v a t i o nF r o m VRE3050 CONTaCTING CIRRuS lOGIC SuPPORT For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact tucson.support@cirrus.com. International customers can also request support by contacting their local Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex Precision Power, Apex and the Apex Precision Power logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. VRE3050DS 
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