WM8215CSEFL/R

WM8215 w 60MSPS 10-bit 3-Channel CCD Digitiser DESCRIPTION FEATURES The WM8215 is a 10-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 60MSPS.  10-bit ADC  60MSPS conversion rate  Low power – 400mW typical  3.3V single supply operation The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset adjust functions. The output from each of these channels is time multiplexed into a single high-speed 10-bit Analogue to Digital Converter. The digital output data is available in 10-bit wide parallel format.  3 channel operation  Correlated double sampling  Programmable gain (9-bit resolution)  Programmable offset adjust (8-bit resolution)  Flexible clamp timing  Programmable clamp voltage  Internally generated voltage references  32-lead QFN package  Serial control interface An internal 4-bit DAC is supplied for internal reference level generation. This may be used to reference CIS signals, in non-CDS mode or to clamp CCD signals during Reset Level Clamping. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 3.3V and a digital interface supply of 3.3V, the WM8215 typically only consumes 400mW. APPLICATIONS  Digital Copiers  USB2.0 compatible scanners  Multi-function peripherals  High-speed CCD/CIS sensor interface BLOCK DIAGRAM WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Production Data, September 2012, Rev 4.3 Copyright 2012 Wolfson Microelectronics plc. WM8215 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1  FEATURES ............................................................................................................ 1  APPLICATIONS..................................................................................................... 1  BLOCK DIAGRAM ................................................................................................ 1  TABLE OF CONTENTS ......................................................................................... 2  PIN CONFIGURATION .......................................................................................... 3  ORDERING INFORMATION .................................................................................. 3  PIN DESCRIPTION ................................................................................................ 4  ABSOLUTE MAXIMUM RATINGS ........................................................................ 5  RECOMMENDED OPERATING CONDITIONS ..................................................... 5  THERMAL PERFORMANCE ................................................................................. 5  ELECTRICAL CHARACTERISTICS ..................................................................... 6  INPUT VIDEO SAMPLING .............................................................................................. 8  SERIAL INTERFACE..................................................................................................... 10  INTERNAL POWER ON RESET CIRCUIT .......................................................... 11  DEVICE DESCRIPTION ...................................................................................... 13  INTRODUCTION ........................................................................................................... 13  INPUT SAMPLING ........................................................................................................ 13  RESET LEVEL CLAMPING (RLC) ................................................................................ 14  CDS/NON-CDS PROCESSING..................................................................................... 16  OFFSET ADJUST AND PROGRAMMABLE GAIN........................................................ 16  ADC INPUT BLACK LEVEL ADJUST ........................................................................... 17  OVERALL SIGNAL FLOW SUMMARY ......................................................................... 18  CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT ...................................... 19  REFERENCES .............................................................................................................. 20  POWER MANAGEMENT .............................................................................................. 20  LINE-BY-LINE OPERATION ......................................................................................... 20  CONTROL INTERFACE ................................................................................................ 20  NORMAL OPERATING MODES ................................................................................... 22  DEVICE CONFIGURATION ................................................................................. 23  REGISTER MAP............................................................................................................ 23  REGISTER MAP DESCRIPTION .................................................................................. 24  APPLICATIONS INFORMATION ........................................................................ 28  RECOMMENDED EXTERNAL COMPONENTS ........................................................... 28  RECOMMENDED EXTERNAL COMPONENT VALUES .............................................. 28  PACKAGE DIMENSIONS .................................................................................... 29  IMPORTANT NOTICE ......................................................................................... 30  ADDRESS: .................................................................................................................... 30  REVISION HISTORY ........................................................................................... 31  w PD, Rev 4.3, September 2012 2 WM8215 Production Data PIN CONFIGURATION ORDERING INFORMATION DEVICE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE 32-lead QFN WM8215CSEFL o 0 to 70 C (5x5x0.9mm) MSL1 260C MSL1 260C (Pb-free) 32-lead QFN WM8215CSEFL/R o 0 to 70 C (5x5x0.9mm) (Pb-free, tape and reel) Note: Reel quantity = 3,500 w PD, Rev 4.3, September 2012 3 WM8215 Production Data PIN DESCRIPTION PIN NAME TYPE 1 RSMP Digital input DESCRIPTION Reset sample pulse (when CDS=1) or clamp control 2 MCLK Digital input Master (ADC) clock. This clock determines the ADC conversion rate. 3 DGND Supply 4 SEN Digital input 5 DVDD2 Supply 6 SDI Digital input Serial data input. 7 SCK Digital input Serial clock. 8 NC No connect No internal connection. 9 NC No connect No internal connection. Digital ground. Enables the serial interface when high. Digital supply, all digital I/O pins. Digital output data bus. ADC output data (d9:d0) is available in 10-bit parallel format. 10 OP[0] Digital output d0 (LSB) 11 OP[1] Digital output d1 12 OP[2] Digital output d2 13 OP[3] Digital output d3 14 OP[4] Digital output d4 15 OP[5] Digital output d5 16 OP[6] Digital output d6 17 OP[7] Digital output d7 18 OP[8] Digital output d8 19 OP[9]/SDO Digital output d9 (MSB) Alternatively, pin OP[9]/SDO may be used to output register read-back data when OEB=0, OPD(register bit)=0 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. Supply Analogue supply. This must be operated at the same potential as DVDD1. AGND1 Supply Analogue ground. VRB Analogue output Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. 23 VRT Analogue output Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. 24 VRX Analogue output Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. 25 VRLC/VBIAS Analogue I/O 26 BINP Analogue input 27 GINP Analogue input Green channel input video. 28 RINP Analogue input Red channel input video. 29 AGND2 Supply Analogue ground. 30 DVDD1 Supply Digital supply for logic and clock generator. This must be operated at the same potential as AVDD. 31 OEB Digital input Output Hi-Z control. All digital outputs set to high-impedance state when input pin OEB=1 or register bit OPD=1. 32 VSMP Digital input Video sample pulse. 20 AVDD 21 22 w Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. Blue channel input video. PD, Rev 4.3, September 2012 4 WM8215 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at Red… offset and gain registers applied to the red input channel. When auto-cycling is enabled, the RSMP pin alone cannot be used to control reset level clamping. Reset level clamping may be enabled in this situation by setting the CLAMPCTRL and RLCEN bits so that he logical AND of RSMP and VSMP closes the clamp switch. When auto-cycling is enabled, the RSMP pin cannot be used for reset sampling (i.e. CDS must be set to 0). 3:2 INTM[1:0] 00 When LINEBYLINE=0 or ACYC=1 this bit has no effect. When LINEBYLINE=1 and ACYC=0: Controls the PGA/offset mux selector: 00 = Red PGA/Offset registers applied to input channel 01 = Green PGA/Offset registers applied to input channel 10 = Blue PGA/Offset registers applied to input channel 11 = Reserved. 000111 (07h) Setup Register 5 Must be set to 0 7:4 Reserved 0000 0 REDPD 0 1 GRNPD 0 When set powers down green S/H, PGA 2 BLUPD 0 When set powers down blue S/H, PGA 3 ADCPD 0 When set powers down ADC. Allows reduced power When set powers down red S/H, PGA consumption without powering down the references which have a long time constant when switching on/off due to the external decoupling capacitors. 4 VRLCDACPD 0 When set powers down 4-bit RLCDAC, setting the output to a high impedance state and allowing an external reference to be driven in on the VRLC/VBIAS pin. 5 ADCREFPD 0 When set disables VRT, VRB buffers to allow external references to be used. 6 VRXPD 0 7 Not Used 0 4:0 5 Not Used RLCEN 00000 1 6 CLAMPCTRL 0 When set disables VRX buffer to allow an external reference to be used. 001000 (08h) Setup Register 6 Must be set to 0 Must be set to 0 Reset Level Clamp Enable. When set Reset Level Clamping is enabled. The method of clamping is determined by CLAMPCTRL. 0 = RLC switch is controlled directly from RSMP input pin: RSMP = 0: switch is open RMSP = 1: switch is closed 1 = RLC switch is controlled by logical combination of RSMP and VSMP. RSMP && VSMP = 0: switch is open RSMP && VSMP = 1: switch is closed 7 w Reserved 0 Must be set to 0 PD, Rev 4.3, September 2012 26 WM8215 ADDRESS Production Data REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION 100000 (20h) Offset DAC (Red) 7:0 DACR[7:0] 10000000 Red channel 8-bit offset DAC value (mV) = 255*(DACR[7:0]-127.5)/127.5 100001 (21h) Offset DAC (Green) 7:0 DACG[7:0] 10000000 Green channel 8-bit offset DAC value (mV) = 255*(DACG[7:0]-127.5)/127.5 100010 (22h) Offset DAC (Blue) 7:0 DACB[7:0] 10000000 Blue channel 8-bit offset DAC value (mV) = 255*(DACB[7:0]-127.5)/127.5 100011 Offset DAC 7:0 DACRGB[7:0] - (23h) (RGB) A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value 100100 PGA Gain LSB 0 PGAR[0] 0 (24h) (Red) This register bit forms the LSB of the red channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 28 hex. 7:1 Reserved 0000000 100101 PGA Gain LSB 0 PGAG[0] 0 (25h) (Green) 7:1 Reserved 0000000 100110 PGA Gain LSB 0 PGAB[0] 0 (26h) (Blue) Must be set to 0 This register bit forms the LSB of the green channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 29 hex. Must be set to 0 This register bit forms the LSB of the blue channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 2A hex. 100111 PGA Gain LSB (27h) (RGB) 101000 (28h) PGA gain MSBs 7:1 Reserved 0000000 0 PGARGB[0] - 7:1 Reserved 0000000 7:0 PGAR[8:1] 00001100 7:0 PGAG[8:1] 00001100 Must be set to 0 Writing a value to this location causes red, green and blue PGA LSB gain values to be overwritten by the new value. (Red) Must be set to 0 Bits 8 to 1 of red PGA gain. Combined with red LSB register bit to form complete PGA gain code. This determines the gain of the red channel PGA according to the equation: Red channel PGA gain (V/V) = 0.66 + PGAR[8:0]x7.34/511 101001 (29h) PGA gain MSBs (Green) Bits 8 to 1 of green PGA gain. Combined with green LSB register bit to form complete PGA gain code. This determines the gain of the green channel PGA according to the equation: Green channel PGA gain (V/V) = 0.66 + PGAG[8:0]x7.34/511 101010 (2Ah) PGA gain MSBs 7:0 PGAB[8:1] 00001100 Bits 8 to 1 of blue PGA gain. Combined with blue LSB register bit to form complete PGA gain code. This determines the gain of the blue channel PGA according to the equation: 7:0 PGARGB[8:1] - A write to this register location causes the red, green and blue PGA MSB gain registers to be overwritten by the new value. (Blue) Blue channel PGA gain (V/V) = 0.66 + PGAB[8:0]x7.34/511 101011 (2Bh) PGA gain MSBs (RGB) Table 6 Register Control Bits w PD, Rev 4.3, September 2012 27 WM8215 Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 18 External Components Diagram RECOMMENDED EXTERNAL COMPONENT VALUES COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION C1 100nF De-coupling for DVDD1. C2 100nF De-coupling for DVDD2. C3 100nF De-coupling for AVDD. C5 1F C6 100nF De-coupling for VRB. C7 100nF De-coupling for VRX. C8 100nF De-coupling for VRT. C9 100nF De-coupling for VRLC. C10 10F Reservoir capacitor for DVDD1. C11 10F Reservoir capacitor for DVDD2. C12 10F Reservoir capacitor for AVDD. Ceramic de-coupling between VRT and VRB (non-polarised). Table 7 External Components Descriptions w PD, Rev 4.3, September 2012 28 WM8215 Production Data PACKAGE DIMENSIONS FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH DM101.A D DETAIL 1 D2 32 25 L 1 24 4 EXPOSED GROUND 6 PADDLE INDEX AREA (D/2 X E/2) E2 17 E 8 16 2X 15 9 b B e 1 bbb M C A B 2X aaa C aaa C TOP VIEW BOTTOM VIEW ccc C A3 A 5 0.08 C C A1 SIDE VIEW SEATING PLANE M M 45° DETAIL 2 0.30 EXPOSED GROUND PADDLE DETAIL 1 W Exposed lead T A3 G H b Half etch tie bar DETAIL 2 Symbols A A1 A3 b D D2 E E2 e G H L T W MIN 0.80 0 0.18 3.30 3.30 0.30 Dimensions (mm) NOM MAX NOTE 0.90 1.00 0.02 0.05 0.203 REF 1 0.25 0.30 5.00 BSC 3.45 5.00 BSC 3.45 0.50 BSC 0.20 0.1 0.40 0.103 3.60 2 3.60 2 0.50 0.15 Tolerances of Form and Position aaa bbb ccc REF: 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VHHD-5. NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VHHD-5. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. w PD, Rev 4.3, September 2012 29 WM8215 Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PD, Rev 4.3, September 2012 30 WM8215 Production Data REVISION HISTORY DATE REV ORIGINATOR CHANGES 04/09/12 4.3 JMacD Order codes changed from WM8215SEFL and WM8215SEFL/R to WM8215CSEFL and WM8215CSEFL/R to reflect change to copper wire bonding. 04/09/12 4.3 JMacD Package Diagram changed to DM101.A w PD, Rev 4.3, September 2012 31