CPC5601D

CPC5601 LITELINK™ Family Auxiliary Programmable Driver IC Features • • • • Meets PC Card (PCMCIA) height requirements Zero standby current PCB real estate and cost savings Can be used with LITELINK II and LITELINK III parts Description The CPC5601 is a serially-programmed driver IC for use with Clare, Inc. LITELINK Silicon Data Access Arrangement (DAA) ICs. The CPC5601 allows hostequipment control of DAA characteristics for worldwide DAA implementations, avoiding multiple implementations with discrete component changes or “stuff” options. The small, low-profile package makes the CPC5601 ideal for 56K PC Card (PCMCIA) modems, PC motherboards, and soft-modems. The CPC5601 uses opto-electronics to maintain the isolation barrier required in the data access arrangement for connection of host devices to the public switched telephone network (PSTN). The one-bit serial input of the CPC5601 recovers clocking information from the input signal to set bits in the shift register. The shift register outputs connect to open-drain FET latches that are used to switch in different external components to set V/I slope, DC termination current limit, gain, and AC termination value in LITELINK DAA implementations.The CPC5601 does not need a clock signal for shift register operation, but relies on internal timing instead. 16 LED- Compliance The supplied application circuits comply with the requirements of TIA/EIA/IS-968 (FCC part 68), UL1950, UL60950, EN60950, IEC60950, EN55022B, CISPR22B, EN55024, and TBR-21. Ordering Information Part Number CPC5601D Description 16-pin SOIC, .300 inch wide package Figure 1. CPC5601 Block Diagram RING 1 15 GND 2 14 LED+ VDDLINE The CPC5601 also includes an opto-coupler for ring detection applications where the AC coupled ring detector of the LITELINK DAA is not used. INPUT 3 Shift Register Drivers NC 6 13 12 11 10 9 8 7 B1 B2 B3 B4 B5 B6 -BR DS-CPC5601-R3.0 www.clare.com 1 CPC5601 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 1 Absolute Minimum and Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 2 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 3 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 5 Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 4 5 2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. 1 Application Circuit Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. 2 AC Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. 3 LITELINK III Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. 4 Current Limiting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. 5 Figure 4 Part List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. 6 Figure 5 Part List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2. 7 Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2. 8 Output Current Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. 1 Latch Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. 2 Programming Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. 3 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 4 Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 LITELINK Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. 1 Clare Design Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. 2 Third Party Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 www.clare.com R3.0 CPC5601 1. Specifications 1.1 Absolute Minimum and Maximum Ratings Parameter Isolation Voltage Operating temperature Storage temperature Soldering temperature Minimum 1500 0 -40 Maximum +85 +125 +220 Unit VRMS °C °C °C Conditions From pins 1, 2, and 3 to pins 7 through 16 Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability. 1.2 Electrical Characteristics Parameter Data Input Input high threshold current Input low threshold current Input voltage drop b1 Through b5 Output Driver Output Current Output Breakdown Voltage On Resistance b6 Output Driver Output Current Output Breakdown Voltage On Resistance Ring Detect Input Input Control Current Input Voltage drop Ring Detect Output Blocking Voltage Dark Current Saturation Voltage Current transfer ratio Power Requirements Supply Voltage Total supply current (input current low) Total supply current (input current high) 2.5 3.5 0.01 10 5.5 1 20 V µA µA 20 33 50 50 0.3 400 500 0.5 V nA V % IC = 10 mA IF = 0 mA IC = 2 mA, IF = 16 mA IF = 6 mA, VCE = 0.5 V 6 0.9 20 1.2 100 1.4 mA V IC = 2 mA, VCE = 0.5 V IF = 5 mA 0.5 120 6 1.4 mA V Ω Supply voltage >= 2.8 V 10 10 6 11 mA V Ω Supply voltage >= 2.8 V 0.10 0.9 1 0.20 1.2 5 1.4 mA mA V IF = 5 mA Minimum Typical Maximum Unit Conditions Specifications subject to change without notice. All performance characteristics based on the use of Clare, Inc. application circuits. Functional operation of the device at conditions beyond those specified here is not implied. Specification conditions: VDD = 5V, temperature = 25 °C, unless otherwise indicated. R3.0 www.clare.com 3 CPC5601 1.3 Timing Characteristics Parameter Setup time Data hold time Data latch time Input hold time for output on Input hold time for output off Minimum 50 60 200 Typical Maximum 140 50 Unit µS µS µS µS µS Conditions logic low before positive timing transition on input (pin 3) hold time after internal 140 µS clock period from positive transition on input 1.4 Pinout Pin 1 2 3 4 5 6 7 8 9 Name RING GND INPUT NC NC NC BRB6 B5 Function Opto-isolated ring output Analog host system ground Serial data input used to program outputs b1 through b6. No connection No connection No connection Phone line side common Output b6 Output b5 Output b4 Output b3 Output b2 Output b1 Telephone line side voltage source Ring LED anode Ring LED cathode Figure 2. CPC5601 Pinout 1 2 3 16 15 14 13 12 6 7 8 11 10 9 10 B4 11 B3 12 B2 13 B1 14 VDDLINE 15 LED+ 16 LED- 4 www.clare.com R3.0 CPC5601 1.5 Mechanical Specifications Figure 3. CPC5601 Mechanical Specifications 16-pin SOIC .635 x 45° (.025 x 45°) 1.981 ±.025 (.078 ±.001) 2.108 max (.083) 1.106 typ. (.040) .254 ±.0127 (.010 ±.0005) 10.160 ±.051 (.400 ±.002) 1.270 typ. (.050) 7.493 ±.127 (.295 ±.005) 10.363 ±.127 (.408 ±.005) .483 ±.102 (.019 ±.009) 3.81 ±.381 (.150 ±.150) .406 typ. (.016) 8.890 typ. (.350) Printed Circuit Board Pattern (top view) 1.270 (.050) 9.278 ±.051 (.383 ±.002) 1.193 (.047) .787 (.031) Dimensions: mm (inches) R3.0 www.clare.com 5 CPC5601 2. Application In the application circuits shown below, the CPC5601 is used to switch AC termination and gain. Loop-current limit switching is optional. Figure 4. CPC5601 Application Circuit Using the LITELINK II and the Optical Snoop Circuit II 501K C3 0.1 REFM R77 499K 1% 0.015 301 ¹This design was tested and found to comply with FCC part 68 with this part. Other compliance requirements may require a different part. ²Higher noise power supplies may require substitution of a 220 µH inductor, Toko 380HB-2215 or similar. See the power quality section of Clare application note AN-146, Guidelines for Effective LITELINK Designs for more informa- tion. Both application circuits use the same components for setting AC termination and the telephone line current limit. 3 Addition of this capacitor improves trans-hybrid loss. 6 www.clare.com R3.0 CPC5601 Figure 5. CPC5601 Application Circuit Using the LITELINK III and the LITELINK Snoop Circuit 3.3 or 5 V R23² 10 C16 10 FB1 600 Ω 200 mA A 1 R1 (RTX) 80.6K 1% TXTX+ MODE OH RING CID RXRX+ C13 0.1 C2 0.1 2 3 4 5 6 7 8 9 VDD TXSM TXTX+ TX MODE GND OH RING C1 1 C9 0.1 A U1 LITELINK III REFL TXF ZTX ZNT TXSL BRNTS GAT NTF DCS1 DCS2 ZDC BRRPB RXS VDDL 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 R4 (RPB) 68.1 1% BRR8 (RHTX) 221K 1% C18 15 pF³ TIP SP1¹ 1 R12 (RNTF) 499K 1% R15 (RDCS2) 1.69M 1% R16 (RZDC) 8.2 1% R78 (RHNTF) 200K 1% BRR20 (RVDDL) 2 R10 499K 1% R75 (RNTX) 261K 1% R13 (RNTS) 501K 1% BRR5 (RTXF) 60.4K 1% C10 0.01 500V C15 0.01 500V Q1 CPC5602C BR- R22 (RDCS1A) 6.8 M 1% R21 (RDCS1B) 6.2 M 1% R14 (RGAT) 47 C21 (CGAT) 100 pF BR- 10 CID C14 0.1 11 RXC4 0.1 12 RX+ 13 SNP+ 14 SNP15 RXF 16 RX R2 (RRXF) 130K 1% C12 (CDCS) 0.027 + DB1 NOTE: Unless otherwise noted, all resistors are in Ohms, 5%. All capacitors are in microFarads. A BR2 RING C7 (CSNP-) 220pF 2000V R3 (RSNPD) 1.5M 1% R6 (RSNP-2) 1.8M 1/10W 1% R44 (RSNP-1) 1.8M 1/10W 1% R7 (RSNP+2) C8 (CSNP+) 1.8M 1/10W 1% 220pF 2000V U4 CPC5601 1 RING LEDLED+ VDDLINE B1 B2 B3 B4 B5 16 15 14 13 12 11 10 9 R67 301 1% R66 4.99K 1% 2 GND R65 3 PROG 470 4 NC 5 NC 6 NC 7 BR8 B6 -BR R45 (RSNP+1) 1.8M 1/10W 1% R76 100K 5% C34 2.2 µF -BR A PROG C31 0.68 µF R71 165 1% R72 59 1% C33 0.024 µF R75 200K 1% R73 R18 (RZTX) 10K 1% -BR ¹This design was tested and found to comply with FCC part 68 with this part. Other compliance requirements may require a different part. ²Higher noise power supplies may require substitution of a 220 µH inductor, Toko 380HB-2215 or similar. See the power quality section of Clare application note AN-146, Guidelines for Effective LITELINK Designs for more information. Both application circuits use the same components for setting AC termination and the telephone line current limit. 3Addition of this capacitor improves trans-hybrid loss. R3.0 www.clare.com 7 CPC5601 2.1 Application Circuit Configurations Figure 4 shows LITELINK II in circuit designed to use the optical snoop circuit in the CPC5601 for ring detection. Figure 5 shows LITELINK III in a circuit that uses the LITELINK snoop circuit ring detection and display feature (caller ID) signal processing. Note that either generation of LITELINK can be used with either signal monitoring scheme. Using the optical path on the CPC5601 for ring detect precludes on-hook display feature signal processing. 2.2.2 LITELINK III The networks connected to outputs b1 and b3 provide selectable telephone line AC termination depending on which network is switched in place of RZNT (see the appropriate LITELINK data sheet and the application note Understanding LITELINK for more information). The resistor connected to output b2 provides the required bias current for North American applications. In North American applications, turn outputs b1 and b2 on, and turn output b3 off to switch in the required 600 Ω AC termination. For European applications, turn outputs b1 and b2 off, and output b3 on to switch in the complex AC termination network. 2.2 AC Termination 2.2.1 LITELINK II The networks connected to outputs b1, b2, b3 and b4 provide selectable telephone line AC termination depending on which network is switched in place of RZNT (see the appropriate LITELINK data sheet and the application note Understanding LITELINK for more information). In North American applications, turn outputs b1 and b2 on, and turn outputs b3 and b4 off to switch in the required 600 Ω AC termination. For European applications, turn outputs b1 and b2 off, and outputs b3 and b4 on to switch in the complex AC termination network. 2.3 LITELINK III Gain Turning output 5 on adds attenuation to the receive path, which is required for the complex termination. Asserting the MODE pin on LITELINK III corrects for the added attenuation. 2.4 Current Limiting Clare recommends using the default value for RZDC to set the loop-current limit to 133 mA. You can, if required, adjust the current limit level by adding R73 and using output b6 to switch this value in parallel with RZDC. See the appropriate LITELINK datasheet for more information on setting loop-current limits. 2.5 Figure 4 Part List Qty. 1 1 1 1 1 1 2 1 1 U1 U4 Q1 Q2 DB1 D1 Z1, Z2 SP1 FB1 Reference Value CPC561x LITELINK II CPC5601 Auxiliary Programmable Driver CPC5602C N-Channel Depletion-Mode FET MMBT4126 PNP bipolar transistor S1ZB60 or DB104 Bridge Rectifier 1N914 10V Zener Diode P3100SB Sidactor 600 Ω, 200 mA ferrite bead Teccor, TI, ST Microelectronics Murata BLM11A601S or similar Fairchild Sindengen Co., Diodes, Inc. Clare, Inc. Suppliers 8 www.clare.com R3.0 CPC5601 Qty. 1 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C1 C2, C3, C4, C9, C13, C14 C10 C12 C15 C16 C29 C30 C31 C32 C33 C34 R1 R2 R4 R5 R8, R9 R13 R14 R15 R20 R21 R22 R23 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 Reference 1 µF, 16 V, ± 10% 0.1 µF, 16 V, ± 10% 0.01 µF, 500 V, ± 10%1 0.027 µF, 16 V, ± 10% 0.0022 µF, 500 V, ± 10%1 10 µF, 16 V, ± 10% 1.5 µF, 16 V, ± 10% 0.47 µF, 300 V, ± 10% 0.68 µF, 16 V, ± 10% 0.47 µF, 16 V, ± 10% 0.015 µF, 16 V, ± 10% 2.2 µF, 16 V, ± 10% 80.6 KΩ, 1/16W, ± 1% 127 KΩ, 1/16W, ± 1% 68.1 Ω, 1/16W, ± 1% 42.2 KΩ, 1/16W, ± 1% 200 KΩ, 1/16W, ± 1% 501 KΩ, 1/16W, ± 1% 47 Ω, 1/16W, ± 1% 1.69 MΩ, 1/16W, ± 1% 2 Ω, 1/16W, ± 1% 6.2 MΩ, 1/4W, ± 1% 6.8 MΩ, 1/4W, ± 1% 10 Ω, 1/16W, ± 5% or 220 µH inductor 10 kΩ, 1/16W, ± 5% 470 Ω, 1/16W, ± 5% 150 Ω, 1/16W, ± 1% 301 Ω, 1/16W, ± 1% 82.5 Ω, 1/16W, ± 1% 29.4 Ω, 1/16W, ± 1% 8.2 kΩ, 1/4W, ± 5% 165 Ω, 1/16W, ± 1% 59 Ω, 1/16W, ± 1% optional, see text 10 Ω, 1/16W, ± 1% 402 kΩ, 1/16W, ± 1% 100 kΩ, 1/16W, ± 5% 499 kΩ, 1/16W, ± 1% Panasonic, Electro Films, FMI, Vishay, etc. Panasonic, AVX, Novacap, Murata, SMEC Value Suppliers R3.0 www.clare.com 9 CPC5601 2.6 Figure 5 Part List Qty. 1 1 1 1 1 1 1 4 2 2 1 1 1 1 1 1 1 1 1 1 1 U1 U4 Q1 DB1 SP1 FB1 C1 C7, C8 C10, C15 C12 C15 C16 C18 C21 C29 C30 C31 C32 C33 C34 Reference Value CPC562x LITELINK III CPC5601 Auxiliary Programmable Driver CPC5602C N-Channel Depletion-Mode FET S1ZB60 or DB104 Bridge Rectifier P3100SB Sidactor 600 Ω, 200 mA ferrite bead 1 µF, 16 V, ± 10% 220 pF, 2 kV, ±5%1 0.01 µF, 500 V, ± 10%1 0.027 µF, 16 V, ± 10% 0.0022 µF, 500 V, ± 10%1 10 µF, 16 V, ± 10% 15 pF, 50 V, ± 10% 100 pF, 50 V, ± 10% 1.5 µF, 16 V, ± 10% 0.47 µF, 300 V, ± 10% 0.68 µF, 16 V, ± 10% 0.47 µF, 16 V, ± 10% 0.024 µF, 16 V, ± 10% 2.2 µF, 16 V, ± 10% Panasonic, AVX, Novacap, Murata, SMEC Sindengen Co., Diodes, Inc. Teccor, TI, ST Microelectronics Murata BLM11A601S or similar Clare, Inc. Suppliers C2, C9, C13, C14 0.1 µF, 16 V, ± 10% 10 www.clare.com R3.0 CPC5601 Qty. 1 1 1 1 1 4 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R1 R2 R3 R4 R5 R8 R10, R12 R13 R14 R15 R16 R18 R20 R21 R22 R23 R64 R65 R66 R67 R71 R72 R73 R75 R76 R77 R78 Reference Value 80.6 KΩ, 1/16W, ± 1% 130 KΩ, 1/16W, ± 1% 1.5 MΩ, 1/16W, ± 1% 68.1 Ω, 1/16W, ± 1% 60.4 KΩ, 1/16W, ± 1% 221 KΩ, 1/16W, ± 1% 499 KΩ, 1/16W, ± 1% 501 KΩ, 1/16W, ± 1% 47 Ω, 1/16W, ± 1% 1.69 MΩ, 1/16W, ± 1% 8.2 Ω, 1/16W, ± 1% 10 KΩ, 1/16W, ± 1% 2 Ω, 1/16W, ± 1% 6.2 MΩ, 1/4W, ± 1% 6.8 MΩ, 1/4W, ± 1% 10 Ω, 1/16W, ± 5% or 220 µH inductor 10 kΩ, 1/16W, ± 5% 470 Ω, 1/16W, ± 5% 150 Ω, 1/16W, ± 1% 301 Ω, 1/16W, ± 1% 165 Ω, 1/16W, ± 1% 59 Ω, 1/16W, ± 1% optional, see text 402 kΩ, 1/16W, ± 1% 100 kΩ, 1/16W, ± 5% 499 kΩ, 1/16W, ± 1% 200 kΩ, 1/16W, ± 1% Panasonic, Electro Films, FMI, Vishay, etc. Suppliers R6, R7, R44, R45 1.8 MΩ, 1/10W, ± 1% 2.7 Operational Sequence In the application circuits above, the CPC5601 is powered from the telephone line only when the LITELINK is off-hook. This requires that you set the telephone line characteristics controlled by the CPC5601 under host system control immediately after taking the DAA off-hook or after pulse dialing is complete, using the following sequence: 1. For incoming calls, validate a ring signal by having the host system poll or read the output of RING (ring detect via snoop circuit on the LITELINK) or RING (ring detect via opto-isolated ring circuit in the CPC5601). 2. Assert OH to complete the connection. 3. Set the telephone line characteristics of the DAA using the CPC5601 via the programming method (see “Programming” on page 12). R3.0 With this circuit, you must program the CPC5601 as soon as possible after asserting off hook. Leaving the CPC5601 unprogrammed leaves open the possibility of LITELINK instability due to lack of AC termination. 2.8 Output Current Ratings Output b6 is the only output that can be used for the current limiting function of a DAA. The FET on output b6 can sink up to 120 mA of current, while the other outputs can sink up to 10 mA. The other outputs can be used for any of the other switchable functions on the telephone line side of a DAA, as long as the current does not exceed the 10 mA limit. www.clare.com 11 CPC5601 3. Programming 3.1 Latch Circuit Description Data applied to the input pin is optically coupled to the shift register through a pulse generator. Each low-tohigh transition in the pulse generator triggers a clock pulse. Clock pulses are applied to the CLK input of six rising-edge-triggered flip-flops. The non-inverted input data is fed to the flip-flops at all times, but the flip-flops are only clocked on receipt of a pulse from the pulse generator. The flip-flops drive six FET switches. 3.2 Programming Protocol Figure 6. Latch Circuit Timing to Turn an Output On t0 INPUT (pin 3) >=50µs (tsetup) 140µs 200µs thold CLOCK Transition after setup time initiates clock pulse First flip-flop reads data at the rising edge of the clock B1 output FET off (drain open) B1 output FET on (sinking current) B1 (pin 13) A setup pulse on the input of at least 50 µS starts the bit programming sequence. The trailing edge of the setup pulse starts a timer on the CPC5601 (t0). After 140 µS, the value of the input is latched into the shift register. To set an output, hold the input high for 200 µS from the leading edge after the setup pulse. This turns on the corresponding open-drain FET to sink current. Figure 7. Latch Circuit Timing to Turn an Output Off t0 >=50m s (tsetup) INPUT (pin 3) Transition after setup time initiates clock pulse CLOCK First flip-flop reads data at the rising edge of the clock 50m s 140m s 150m s min B1 (pin 13) B1 output FET on (sinking current) B1 output FET off (drain open) To clear an output, hold the input high for 50 µS after the setup pulse, then take the input low for at least 150 µS. Repeat the sequence of the setup pulse followed by the appropriate input condition for each successive bit. Bear the following in mind while programming the CPC5601: 12 www.clare.com R3.0 CPC5601 • All bits must be set in each programming sequence, even to change just one of the outputs. • Data is placed in least-significant bit (output 1) first. • After setting all the bits, take the input low. In the absence of low-to-high transitions on the input, the internal CPC5601 clock is held high, preventing any output changes. • The CPC5601 does not employ a shift register load function. As new data is shifted into the flip-flops, the outputs (starting with b1) change throughout the data input sequence. 3.3.1 LITELINK III b1 (LSB) off b2 off b3 on b4 off b5 on b6 (MSB) off 3.3.2 LITELINK II b1 (LSB) off b2 off b3 on b4 on b5 on b6 (MSB) off 3.3 Programming Example This programming example sets the following CPC5601 output state, suitable for a European DAA: 1. Hold the input low for 50 µS. 2. Set the input high for 50 µS to trigger the timer. 3. Set the input low for 150 µS to set output b1 to off. 4. Repeat the steps as shown in the programming waveform below to program all six outputs to the desired pattern. Figure 8. LITELINK III European Programming Sample Input Waveform t0 setup timer trigger setup bit 1 set off timer trigger setup bit 2 set off bit 3 set on timer trigger setup bit 4 set off timer trigger setup bit 5 set on timer trigger setup bit 6 set off timer trigger 50µS/div. Figure 9. LITELINK II European Programming Sample Input Waveform t0 setup timer trigger setup bit 1 set off timer trigger setup bit 2 set off bit 3 set on timer trigger setup bit 4 set on timer trigger setup bit 5 set on timer trigger setup bit 6 set off timer trigger 50µS/div. 4. Regulatory Information CPC5601 can be used to build products that comply with the requirements of TIA/EIA/IS-968 (formerly FCC part 68), FCC part 15B, TBR-21, EN60950, UL1950, EN55022B, IEC950/IEC60950, CISPR22B, EN55024, and many other standards. CPC5601 comR3.0 plies with the requirements of UL1577. CPC5601 provides supplementary isolation. Metallic surge requirements are met through the inclusion of a Sidactor in the application circuit. Longitudinal surge protection is provided by CPC5601’s optical-across-the13 www.clare.com barrier technology and the use of high-voltage components in the application circuit as needed. The information provided in this document is intended to inform the equipment designer but it is not sufficient to assure proper system design or regulatory compliance. Since it is the equipment manufacturer's responsibility to have their equipment properly designed to conform to all relevant regulations, designers using CPC5601 are advised to carefully verify that their endproduct design complies with all applicable safety, EMC, and other relevant standards and regulations. Semiconductor components are not rated to withstand electrical overstress or electro-static discharges resulting from inadequate protection measures at the board or system level. 5. LITELINK Design Resources 5.1 Clare Design Resources The Clare, Inc. web site has a wealth of information useful for designing with LITELINK, including application notes and reference designs that already meet all applicable regulatory requirements. LITELINK data sheets also contains additional application and design information. See the following links: LITELINK datasheets and reference designs Application note AN-107 LOCxx Series - Isolated Amplifier Design Principles Application note AN-114 ITC117P Application note AN-117 Customize Caller-ID Gain and Ring Detect Voltage Threshold for CPC5610/11 Application note AN-140, Understanding LITELINK Application note AN-141, Enhanced Pulse Dialing with LITELINK Application note AN-143, Loop Reversal Detection with LITELINK Application note AN-146, Guidelines for Effective LITELINK Designs Application note AN-147, Worldwide Application of LITELINK For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specifications: DS-CPC5601-R3.0 © Copyright 2002, Clare, Inc. LITELINK™ is a trademark of Clare, Inc. All rights reserved. Printed in USA. 6/5/2002 Application note AN-149, Increased LITELINK II Transmit Power Application note AN-150, Ground-start Supervision Circuit Using IAA110 5.2 Third Party Design Resources The following also contain information useful for LITELINK designs. All of the books are available on amazon.com. Understanding Telephone Electronics, Stephen J. Bigelow, et. al., Butterworth-Heinenman; ISBN: 0750671750. Newton’s Telecom Dictionary, Harry Newton, CMP Books; ISBN: 1578200695. Photodiode Amplifiers: Op Amp Solutions, Jerald Graeme, McGraw-Hill Professional Publishing; ISBN: 007024247X Teccor, Inc. Surge Protection Products United States Code of Federal Regulations, CFR 47 Part 68.3.