CPC5710N

CPC5710N Phone Line Monitor (PLM) IC Features • Excellent common-mode rejection ratio (CMRR) • Application circuits can meet isolation requirements of worldwide telephony standards • Small 8-pin SOIC • Worldwide telephone network compatibility • Full-wave ringing level detector comparator with internal threshold, large hysteresis, and logic-level output • 3.3V or 5V operation • High differential input impedance • Very low common-mode input impedance • Fixed gain • Differential or single-ended linear output • TTL logic level input • CMOS logic level output (TTL compatible) • Virtually non-detectable in voice monitoring applications Description The Clare CPC5710N is a selectable dual function CMOS special purpose integrated high-impedance input, fixed-gain amplifier and an internally set voltage level comparator for telephone line monitoring. The high (>40dB) common-mode rejection ratio makes the CPC5710N an excellent choice for signaling detection, line condition monitoring, discrete voice recording and CID buffering applications. In addition to voice applications, the CPC5710N is ideal for data applications such as embedded modem designs utilized in broadband set-top boxes. Ordering Information Part Number CPC5710N CPC5710NTR Description PLM IC, Tubed, 100/Tube PLM IC, Tape &Reel, 2000/Reel Applications • The CPC5710N can be used for line monitoring or detection of signaling states and loop conditions such as: • Display feature (caller ID) signal buffering • Line-In-Use (LIU) detection • Ringing signal with adjustable detection level • Battery presence monitoring • Tip to ring line voltage monitoring • Line polarity • Imperceptible voice recording Figure 1. CPC5710N Block Diagram VDD 50kΩ + VDD 1.625 V + 6 IN+ IN7 ++ AV=6 -0V 2V Switch shown in Detector Mode 5 LINOUT+ 4 LINOUT2 CMPOUT VDD 1 VDD 3 LIN/CMP VSS Pb RoHS 2002/95/EC e3 + 1.25 V GND 8 GND DS-CPC5710-R02 www.clare.com 1 CPC5710N 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Recommended Operating Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Detector Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 LIN/CMP Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Using CPC5710N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 LIN/CMP Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Amplifier Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Linear Amplifier Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Detector Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Ringing Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Setting Ringing Detection Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Power Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Line-In-Use (LIU) and Line Polarity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Non-Intrusive Line Monitoring, Display Feature (Caller ID) Signal Reception, and Ringing Detection Application . . . . . . . . . . . . . 3.2.1 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Regulatory Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 3 4 4 4 4 4 5 5 5 5 5 5 5 6 7 7 8 8 8 4. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1.1 8-Pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1.2 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 Washing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 www.clare.com R02 CPC5710N 1. Specifications 1.1 Package Pinout 1.2 Pin Description Pin 1 1 2 3 4 VDD CMPOUT LIN/CMP LINOUT+ GND IN IN + LINOUT- Name VDD CMPOUT LIN/CMP LINOUTLINOUT+ IN+ INGND Power supply Detector output Description 8 7 6 5 2 3 4 5 6 7 8 Comparator Enable - disables linear amplifier outputs. Linear amplifier inverting output Linear amplifier non-inverting output Non-inverting differential input Inverting differential input Ground 1.3 Absolute Maximum Ratings Parameter VDD Storage temperature Total package power dissipation Logic input voltage -0.3 Minimum Maximum -0.3 -40 6 +125 300 VDD + 0.3 Unit V °C mW V Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. 1.4 Recommended Operating Environment Parameter Temperature Humidity Non-condensing Conditions Minimum -40 5 Typical Maximum +85 95 Unit °C % R02 www.clare.com 3 CPC5710N 1.5 Electrical Characteristics Unless otherwise specified, minimum and maximum values are guaranteed by production testing requirements. Typical values, the result of engineering evaluations, are characteristic of the device and are provided for informational purposes only. They are not however, a part of the production testing requirements. Unless otherwise indicated: VDD = 5V, Temperature = 25°C 1.5.1 AC Characteristics Parameter Input Impedance Input offset voltage Input offset current Output DC bias level Output Low Voltage Gain Common-mode rejection ratio Equivalent input noise voltage Symbol ZIN VIO IIO ICM = 0, No common-mode signal applied. ICM = 12µA (per lead) signal applied. Conditions Minimum 10 0.9 5.88 40 Typical 1.0 6 -90 Maximum 40 35 125 1.1 50 6.12 Unit MΩ mV nA nA V mV dB dBm/Hz VOUT_DC At LINOUT+ or LINOUT-, IO = 0.5mA VOUT AV CMRR VN IO = 0.5mA 0 to 20kHz Common-mode current ≤ 12µA per lead, 0 to 120Hz 1.5.2 Detector Threshold Characteristics Parameter Detection threshold Detector hysteresis Symbol VIN_DET ICM = 0 ICM = ±12µA Conditions Minimum 675 488 300 Typical 750 750 375 Maximum 850 1012 450 Unit mV mV mV VIN_HYST ICM = 0 1.5.3 LIN/CMP Input Characteristics Parameter Input low voltage Input high voltage Input low leakage current Input high leakage current Symbol VIL VIH IIL IIH VIL = 0.4V VIH = 2.4V Conditions Minimum 2.0 Typical Maximum 0.8 -120 -120 Unit V V µA µA 1.5.4 Power Characteristics Parameter Supply voltage Supply current 4 Symbol VDD IDD All inputs and outputs open www.clare.com Conditions Minimum 3.0 Typical Maximum 5.5 10 Unit V mA R02 CPC5710N 2. Using CPC5710N 2.1 LIN/CMP Input The LIN/CMP input selects the active output, either the detector output CMPOUT or the linear outputs, LINOUT- and LINOUT+. Set LIN/CMP low for linear output and high for comparator output. Note that both outputs cannot be used at once. With LIN/CMP at logic low (LIN/CMP = 0), the amplifier outputs are biased at a nominal 1VDC and CMPOUT is held high. With LIN/CMP at logic high (LIN/CMP = 1), LINOUT+ is 0V and LINOUT- is 2V. 6 R SNPD GAIN CID ( dB ) = 20 log ---------------------------------------------------------------------------------------2 1 (4R +R ) + ------------------------SNP SNPD ( π fC SNP ) 2 where ƒ is the frequency of the signal. Clare Application Note AN-117 Customize Caller ID Gain and Ringing Detect Voltage Threshold is a spreadsheet for trying different component values in this type of circuit. Figure 2. LIN/CMP Timing for Caller-ID Signal Reception 2s 500 ms 3s 475 ms 2s 2.3 Detector Considerations 2.3.1 Ringing Signal Detection The CPC5710N detector is a full-wave configuration. Ringing signals will assert the output on both positive and negative parts of the ringing waveform. Hysteresis is employed by the internal comparator circuit to provide noise immunity. The set-up of the detector causes CMPOUT output pulses to remain low for most of the ringing signal positive and negative half-cycles. CMPOUT returns high when the ringing signal is near the zero-voltage crossing. Caller ID data LIN/CMP Signal levels not to scale Figure 3. CMPOUT Relative to Input 2.2 Amplifier Design Considerations Amplifier inputs are biased at a nominal 1.25VDC, the internal voltage reference. The internal common-mode circuitry maintains the average of the inputs at 1.25VDC. For example, if one input reaches 1.3V, the common-mode circuit drives the other input to 1.2V. Ringing Signal CMPOUT 2.3.2 Setting Ringing Detection Threshold 2.2.1 Linear Amplifier Gain Display feature information (caller ID) and voice signals are coupled through the linear amplifier. In North America, CID data signals are typically sent between the first and second ringing signal burst. Referring to Figure 6., signal gain from tip and ring to LINOUT+ and LINOUT- is determined by: The ringing detection threshold depends on the component values of the input network. The values for these components shown in the application circuit are recommended for typical operation. Referring to Figure 6., the ringing detection threshold can be changed according to the following formula: 750 mV V RINGPK =  -------------------  R RSNPD 2 1 ( 4 R SNP + R SNPD ) + ------------------------------------2 ( π f RING C SNP ) R02 www.clare.com 5 CPC5710N With the application circuit in Figure 6., the series capacitors serve to reduce the magnitude of the high-amplitude, low-frequency ringing signals, while making the ringing detection threshold of the CPC5710N variable with the frequency of the ringing signal. With the circuit as given, CMPOUT will change states with a 15Hz ringing signal at approximately 48VPEAK. For a 68Hz ringing signal, CMPOUT will change states with a ringing signal amplitude of approximately 11.5VPEAK. In applications where CPC5710N will be used only as a ringing level detector, or if significant attenuation of the amplified signal can be tolerated, the frequency variability of the ringing detection threshold can be reduced by increasing the value of the resistors and capacitors in series with the input. Clare Application Note AN-117 Customize Caller ID Gain and Ringing Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit for LITELINK snoop circuit applications. 2.4 Power Quality CPC5710N works best with a clean power supply. To clean up power supply noise, Clare, Inc., recommends using a pi network on the VDD pin as shown in Figure 4., if needed. Figure 4. Optional Power Supply pi Network 3.3 or 5 V R100 10 C101 10 FB100 600 Ω 200 mA A C100 1 A To VDD Pin 1 Note: For lower-frequency noise, use a 220 µH inductor in series with R100. 6 www.clare.com R02 CPC5710N 3. Applications 3.1 Line-In-Use (LIU) and Line Polarity Detector This circuit performs two phone line interface functions, LIU and line polarity detection. The LIU output is logic high if the tip to ring voltage is less than approximately 17V. This will occur whenever a parallel device on the line such as a telephone or FAX is taken off hook. This circuit can also be used to detect for the presence or loss of battery. The Polarity output indicates the polarity of the phone line. Whenever tip is positive with respect to ring, Polarity out will be a logic high. Figure 5. LIU and Polarity Detection Application Circuit +V U1 CPC5710 VDD 3 50kΩ LIN/CMP VDD 1.625 V + + VDD VDD CMPOUT 1 2 INR17 4.7MΩ 0V ++ AV=6 -2V Switch shown in Linear Mode LINOUT+ LINOUT5 4 R11 499KΩ R10 21KΩ +V R13 20KΩ R14 4.7MΩ +V IN+ 1/4 U2 LM339 OUT +V R16 10KΩ Polarity R15 10KΩ TIP R1 R3 R2 R4 6 R5 604KΩ IN+ IN- R12 20KΩ +V IN+ 1/4 U2 LM339 OUT RING R1-4 8.06MΩ 1% 1206 7 INR6 4.7MΩ +V IN+ 1/4 U2 LM339 OUT C1 1nF VSS R8 20KΩ GND + 1.25 V GND 8 LIU R9 499KΩ R7 21KΩ IN- Unless noted otherwise: All resistors 1%, 1/16 W. All capacitors 16 V 10%. R02 www.clare.com 7 CPC5710N 3.2 Non-Intrusive Line Monitoring, Display Feature (Caller ID) Signal Reception, and Ringing Detection Application This application uses the logic input LIN/CMP to select between ringing detection or buffering display feature (caller-ID) and voice signals. Note the AC coupling of the tip and ring signals. With this circuit, setting LIN/CMP to a logic high enables the ringing detector. After a valid ringing period, configure LIN/CMP with a logic low to couple the audio frequency signal to the output pins. Please see “Detector Considerations” on page 5 for more information on ringing detection. Figure 6. Non-Intrusive Line Monitoring, Display Feature (Caller ID) Signal Reception, and Ringing Detection Application Circuit U1 CPC5710 From Control Logic VDD 50kΩ + VDD 1.625 V + TIP R1 R2 C1 IN+ 6 0V ++ AV=6 -2V Switch shown in Detector Mode 5 LINOUT+ 4 LINOUTDisplay Feature Output VOUT = VIN at 500 Hz VDD 1 VDD 2 CMPOUT 3.3 or 5 V LIN/CMP 3 RINGING DET R3 RING R4 C2 R5 1.5MΩ 0603 7 IN- R1-4 C1,2 1.8 MΩ 220 pF VSS + 1.25 V GND 8 GND Unless noted otherwise: All resistors are 1/8 W, 1%, 1206. 3.2.1 Frequency Response The blocking capacitors used in this application circuit affect the frequency response of the system. With the components shown, response rolls off 3dB @ 166Hz. Other values can be used for different response characteristics. 3.3 Regulatory Issues Component sizing and value recommendations shown in the application circuits above will need to be reviewed with regard to the regulatory and safety requirements for each particular application. 8 www.clare.com R02 CPC5710N 4. Manufacturing Information Note that the CPC5710N branding (package imprinting) leaves off the last character of the part number, the letter “N,” due to package space limitations. 4.1 Mechanical Dimensions 4.1.1 8-Pin SOIC Package 8-Pin SOIC Package 0.19 / 0.25 (0.008 / 0.010) Recommended PCB Land Pattern 5.80 / 6.20 (0.23 / 0.24) PIN 1 0.356 / 0.457 (0.014 / 0.018) 4.80 / 4.98 (0.19 / 0.20) 3.81 / 3.99 (0.15 / 0.16) 0.41 / 1.27 (0.016 / 0.050) 1.55 (0.061) 5.40 (0.213) 1.27 TYP (0.05 TYP) 1.37 / 1.58 (0.05 / 0.06) 0.60 (0.024) 1.27 (0.050) 0.10 / 0.25 (0.004 / 0.010) 1.52 / 1.73 (0.06 / 0.07) Dimensions mm (inches) 0.53 REF (0.021 REF) 4.1.2 Tape and Reel Specifications Tape and Reel Packaging for 8-Pin SOIC Package 330.2 DIA. (13.00 DIA.) Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) W = 12.00 ± 0.30 (0.472 ± 0.012) B0 = 5.30 ± 0.10 (0.209 ± 0.004) Top Cover Tape Embossed Carrier P = 8.00 ± 0.10 (0.315 ± 0.004) K0= 2.10 ± 0.10 (0.083 ± 0.004) User Direction of Feed A0 = 6.50 ± 0.10 (0.256 ± 0.004) Embossment Dimensions mm (inches) NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 R02 www.clare.com 9 CPC5710N 4.2 Soldering For proper assembly, the component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy. 4.3 Washing Clare does not recommend ultrasonic cleaning of this part. Pb RoHS 2002/95/EC e3 For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC5710 - R02 © Copyright 2008, Clare, Inc. All rights reserved. Printed in USA. 8/7/08 10 www.clare.com R02