CPC7582BCTR

Not for New Designs CPC7582 Line Card Access Switch Features • Small 16-pin SOIC and 16-pin DFN • DFN package printed-circuit board footprint is 60 percent smaller than the SOIC version, 70 percent smaller than 4th generation EMR solutions. • Monolithic IC reliability • Low matched RON • Eliminates the need for zero cross switching • Flexible switch timing to transition from ringing mode to talk mode. • Clean, bounce-free switching • Tertiary protection consisting of integrated current limiting, voltage clamping, and thermal shutdown for SLIC protection • 5 V operation with power consumption < 10 mW • Intelligent battery monitor • Latched logic-level inputs, no external drive circuitry required • SOIC version is pin compatible with Agere product Description The CPC7582 is a monolithic solid-state switch in a 16-pin SOIC or DFN surface-mount package. It provides the necessary functions to replace two 2-Form-C electro-mechanical relays on traditional analog and integrated voice and data (IVD) line cards found in Central Office, Access, and PBX equipment. The device contains solid state switches for tip and ring line break, ringing injection/ringing return and test access. The CPC7582 requires only a +5V supply and offers break-before-make or make-before-break switch operation using simple logic-level input control. The CPC7582xC logic states differ from the CPC7582xA/B. See “Functional Description” on page 12 for more information. The CPC7582xC also has a higher trigger and hold current for the protection SCR. Ordering Information CPC7582 part numbers are specified as shown here: B - 16-pin SOIC delivered 50/Tube, 1000/Reel M - 16-pin DFN delivered 52/Tube, 1000/Reel Applications • • • • • • • • Central office (CO) Digital Loop Carrier (DLC) PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) Fiber in the Loop (FITL) Pair Gain System Channel Banks CPC7582 x x xx TR - Add for Tape & Reel Version A - With Protection SCR B - Without Protection SCR C - With Protection SCR with higher trigger and hold currents and “Monitor Test State” Figure 1. CPC7582 Block Diagram +5 Vdc TTEST 5 4 TRING 6 VDD Tip Secondary Protection TLINE 3 X SW5 X SW3 SW1 CPC7582 2 TBAT X SLIC RLINE 14 SW6 SW2 15 RBAT SCR and Trip Circuit (CPC7582xB/C) VREF Switch Control Logic L A T C H 7 TSD 9 10 11 INTEST INRINGING LATCH Ring X X X SW4 RTEST 12 13 300Ω (min.) 1 FGND 16 VBAT 8 DGND VBAT RINGING Pb www.clare.com RoHS 2002/95/EC e3 1 DS-CPC7582-R05 CPC7582 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6.2 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.6.3 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6.4 Test Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.7 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.8 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.9 CPC7582xA/B Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.10 CPC7582xC Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 CPC7582xA/B Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 CPC7582xC Logic States: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Make-Before-Break Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Make-Before-Break Operation for All Versions (Ringing to Talk Transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Break-Before-Make Operation - CPC7582xA/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Break-Before-Make Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 Break-Before-Make Operation for all Version (Ringing to Talk Transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 16-Pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Printed-Circuit Board Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 16-Pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 16-Pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 12 13 13 13 13 13 14 14 14 14 15 15 15 15 15 15 16 17 17 17 17 18 18 18 18 18 19 19 19 19 19 2 www.clare.com R05 CPC7582 1. Specifications 1.1 Package Pinout 1.2 Pinout Pin 16 VBAT CPC7582 FGND TBAT TLINE TRINGING TTEST VDD TSD 1 Name FGND TBAT TLINE TTEST VDD TSD DGND INTEST LATCH RTEST RLINE RBAT VBAT Fault ground Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 15 RBAT 14 13 RLINE RRINGING Tip lead to the SLIC Tip lead of the line side Tip lead of the test bus +5 V supply Temperature shutdown pin Digital ground Logic control input Data latch enable control input Ring lead of the test bus Ring lead of the line side Ring lead to the SLIC Battery supply TRINGING Ringing generator return 12 RTEST 11 LATCH 10 9 INRINGING INTEST DGND 8 INRINGING Logic control input RRINGING Ringing generator source R05 www.clare.com 3 CPC7582 1.3 Absolute Maximum Ratings Parameter +5 V power supply (VDD) Battery Supply DGND to FGND separation Logic input voltage Logic input to switch output isolation Switch open-contact isolation (SW1, SW2, SW3, SW5, SW6) Switch open-contact isolation (SW4) Operating relative humidity Operating temperature Storage temperature Minimum Maximum -0.3 -5 -0.3 5 -40 -40 7 -85 +5 VDD +0.3 320 320 465 95 +110 +150 Unit V V V V V V V % °C °C 1.5 General Conditions Unless otherwise specified, minimum and maximum values are production testing requirements. Typical values are characteristic of the device at 25°C and are the result of engineering evaluations. They are provided for informational purposes only and are not part of the manufacturing testing requirements. Specifications cover the operating temperature range TA = -40°C to +85°C. Also, unless otherwise specified all testing is performed with VDD = +5Vdc, logic low input voltage is 0Vdc and logic high input voltage is +5Vdc. 1.4 ESD Rating ESD Rating (Human Body Model) 1000 V Absolute maximum electrical ratings are at 25°C. Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability. 4 www.clare.com R05 CPC7582 1.6 Switch Specifications 1.6.1 Break Switches, SW1 and SW2 Parameter Off-state leakage current +25° C +85° C -40° C RON +25° C +85° C -40° C RON match DC current limit +25° C +85° C -40° C Dynamic current limit (t ≤ 0.5 μs) Break switches on, all other switches off, apply ±1 kV 10x1000 μs pulse with appropriate protection in place. VSW (TLINE, RLINE) = ±320 V, logic inputs = GND VSW (TLINE, RLINE) = ±330 V, logic inputs = GND VSW (TLINE, RLINE) = ±310 V, logic inputs = GND ISW VSW (on) = ±10 V ISW 80 300 160 400 2.5 425 A mA ISW = ±10 mA, ±40 mA, RBAT and TBAT = -2 V Per on-resistance test condition of SW1, SW2. Magnitude RON SW1 - RONSW2 14.5 RON Δ RON 20.5 10.5 0.15 28 0.8 Ω VSW (differential) = -320 V to GND VSW (differential) = +260 V to -60 V VSW (differential) = -330 V to GND VSW (differential) = +270 V to -60 V VSW (differential) = -310 V to GND VSW (differential) = +250 V to -60 V ISW 0.1 0.3 0.1 1 μA Conditions Symbol Minimum Typical Maximum Unit Logic input to switch output isolation +25° C +85° C -40° C dv/dt sensitivity 0.1 0.3 0.1 200 V/μs 1 μA R05 www.clare.com 5 CPC7582 1.6.2 Ringing Return Switch, SW3 Parameter Off-state leakage current +25° C +85° C -40° C RON +25° C +85° C -40° C DC current limit +25° C +85° C -40° C Dynamic current limit (t ≤ 0.5 μs) Ringing switches on, all other switches off, apply ±1 kV 10x1000 μs pulse, with appropriate protection in place. VSW (TRINGING, TLINE) = ±320 V, logic inputs = GND VSW (TRINGING, TLINE) = ±330 V, logic inputs = GND VSW (TRINGING, TLINE) = ±310 V, logic inputs = GND ISW VSW (on) = ±10 V ISW 70 135 85 210 2.5 A mA ISW (on) = ±0 mA, ±10 mA RON 60 85 45 100 Ω VSW (differential) = -320 V to GND VSW (differential) = +260 V to -60 V VSW (differential) = -330 V to GND VSW (differential) = +270 V to -60 V VSW (differential) = -310 V to GND VSW (differential) = +250 V to -60 V ISW 0.1 0.3 0.1 1 μA Conditions Symbol Minimum Typical Maximum Unit Logic input to switch output isolation +25° C +85° C -40° C dv/dt sensitivity 0.1 0.3 0.1 200 V/μs 1 μA 6 www.clare.com R05 CPC7582 1.6.3 Ringing Switch, SW4 Parameter Off-state leakage current +25° C +85° C -40° C On Voltage Ringing generator current to ground VSW (differential) = -255 V to +210 V VSW (differential) = +255 V to -210 V VSW (differential) = -270 V to +210 V VSW (differential) = +270 V to -210 V VSW (differential) = -245 V to +210 V VSW (differential) = +245 V to -210 V ISW (on) = ± 1 mA Ringing switches on, inputs set for ringing mode Ringing switches on, all other switches off, apply ±1 kV 10 x 1000 μs pulse, with appropriate protection in place. ISW (on) = ±70 mA, ±80 mA VSW (RRINGING, RLINE) = ±320 V, logic inputs = gnd VSW (RRINGING, RLINE) = ±330 V, logic inputs = gnd VSW (RRINGING, RLINE) = ±310 V, logic inputs = gnd ISW VSW IRINGING ISW IRINGING RON 0.1 300 10 0.25 150 2 15 mA mA A μA Ω ISW 0.05 0.1 0.05 1.5 3 V 1 μA Conditions Symbol Minimum Typical Maximum Unit On steady-state current* Inputs set for ringing mode Surge current* Release current RON Logic input to switch output isolation +25° C +85° C -40° C dv/dt sensitivity 0.1 0.3 0.1 200 V/μs 1 μA *Secondary protection and ringing source current limiting must prevent exceeding this parameter. R05 www.clare.com 7 CPC7582 1.6.4 Test Switches, SW5 and SW6 Parameter Off-state leakage current +25° C +85° C -40° C RON +25° C +85° C -40° C DC current limit +25° C +85° C -40° C Dynamic current limit (t ≤ 0.5 μs) Test switches on, all other switches off, apply ±1 kV at 10x1000 μs pulse, with appropriate protection in place. VSW (TTEST, TLINE) = ±320 V, logic inputs = gnd VSW (TTEST, TLINE) = ±330 V, logic inputs = gnd VSW (TTEST, TLINE) = ±310 V, logic inputs = gnd ISW VSW (on) = ±10 V ISW 80 175 110 210 2.5 250 A mA ISW(ON) = ±10 mA, ±40 mA, TBAT = -2 V 38 RON 46 28 70 Ω VSW (differential) = -320 V to GND VSW (differential) = +260 V to -60 V VSW (differential) = -330 V to GND VSW (differential) = +270 V to -60 V VSW (differential) = -310 V to GND VSW (differential) = +250 V to -60 V ISW 0.1 0.3 0.1 1 μA Conditions Symbol Minimum Typical Maximum Unit Logic input to switch output isolation +25° C +85° C -40° C 0.1 0.3 0.1 1 μA 8 www.clare.com R05 CPC7582 1.7 Additional Electrical Characteristics Parameter Digital input characteristics Input low voltage Input high voltage Input leakage current (high) Input leakage current (low) Voltage Requirements VDD VBAT1 1 Conditions VDD = 5.5 V, VBAT = -75 V, VIH = 5 V VDD = 5.5 V, VBAT = -75 V, VIL = 0 V Symbol VIL VIH IIH IIL Minimum 3.5 - Typical 0.1 0.1 Maximum 1.5 1 Unit V μA 1 - VDD VBAT 4.5 -19 5.0 -48 5.5 -72 V V VBAT is used only for internal protection circuitry. If VBAT goes more positive than -10 V, the device will enter the all-off state and will remain in the all-off state until the battery goes more negative than -15 V Power requirements Power consumption in talk and all-off states Power consumption in all other states VDD current in talk and all-off states VDD current in all other states VDD = 5 V, VBAT = -48 V, measure IDD and IBAT P 6.5 IDD VDD = 5 V, VBAT = -48 V IDD 1.3 0.1 2.0 10 μA 1.1 10 2.0 mA 5.5 10 mW IBAT VBAT current in any state VDD = 5 V, VBAT = -48 V Temperature Shutdown Requirements (temperature shutdown flag is active low) Shutdown activation temperature Shutdown circuit hysteresis Not production tested - limits are guaranteed by design and Quality Control sampling audits. TTSD_on TTSD_off 110 10 125 - 150 25 °C °C R05 www.clare.com 9 CPC7582 1.8 Protection Circuitry Electrical Specifications Parameter Voltage drop at continuous current (50/60 Hz) Voltage drop at surge current Surge current Conditions Symbol Minimum Typical Maximum Unit Parameters Related to the Diodes in the Diode Bridge Apply ± dc current limit of break switches Apply ± dynamic current limit of break switches T=+25°C Trigger current T=+85°C T=+25°C Hold current T=+85°C Gate trigger voltage IGATE = ITRIGGER** VTBAT or VRBAT IVBAT VTBAT or VRBAT VTBAT or VRBAT IHOLD ITRIG Forward Voltage Forward Voltage 2.1 5 3 V - Parameters Related to the Protection SCR 60 (CPC7582xA, xB) 70 (CPC7582xC) 35 (CPC7582xA, xB) 40 (CPC7582xC) 100 (CPC7582xA, xB) 135 (CPC7582xC) * mA VBAT -2 1.0 V μA V V A 60 (CPC7582xA, xB) 70 (CPC7582xA, xB) 110 (CPC7582xC) 115 (CPC7582xC) VBAT -4 -3 -5 Reverse leakage current VBAT = -48 V 0.5 A, t = 0.5 μs On-state voltage 2.0 A, t = 0.5 μs *Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. **VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate. 1.9 CPC7582xA/B Truth Table State Talk Test Ringing All Off Latched All off 1 2 INRINGING 0 0 1 1 X X INTEST 0 1 0 1 X X LATCH TSD Break Switches On Off Off Off Off Ringing Switches Off Off On Off Unchanged Off Test Switches Off On Off Off Off 0 1 or Floating1 1 X 02 If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally. Forcing TSD to ground overrides the logic input pins and forces an all off state. 10 www.clare.com R05 CPC7582 1.10 CPC7582xC Truth Table State Talk Test/Monitor Ringing Ringing Test Latched All off INRINGING 0 0 1 1 X X INTEST 0 1 0 1 X X 1 X 02 Off 0 1 or Floating1 LATCH TSD Break Switches On On Off Off Ringing Switches Off Off On On Unchanged Off Off Test Switches Off On Off On 1If T is tied high, thermal shutdown is disabled. If T is left floating, the thermal shutdown mechanism functions normally. SD SD 2Forcing T to ground overrides the logic input pins and forces an all off state. SD R05 www.clare.com 11 CPC7582 2. Functional Description 2.1 Introduction 2.1.1 CPC7582xA/B Logic States • Talk. Break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. • Ringing. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test switches SW5 and SW6 open. • Test. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and loop test switches SW5 and SW6 closed. • All off. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. 2.1.2 CPC7582xC Logic States: • Talk. Break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. • Ringing. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test switches SW5 and SW6 open. • Test/Monitor. Break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 closed. • Ringing Test. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test switches SW5 and SW6 closed. • All off. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. The CPC7582 offers break-before-make and makebefore-break switching from the ringing state to the talk state with simple logic-level input control. Solid-state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State control is via logic-level input so no additional driver circuitry is required. The linear break switches SW1 and SW2 have exceptionally low RON and excellent matching characteristics. The ringing switch SW4 has a minimum open contact breakdown voltage of 480 V. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator). Integrated into the CPC7582 is an over voltage clamping circuit, active current limiting, and a thermal shutdown mechanism to provide protection to the 12 SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and hazardous potentials are diverted to ground via diodes and, in xA/C parts, an integrated SCR. Power-cross potentials are also reduced by the current limiting and thermal shutdown circuits. To protect the CPC7582 from an overvoltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7582BC will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. The CPC7582 operates from a +5 V supply only. This gives the device extremely low idle and active power consumption and allows use with virtually any range of battery voltage. Battery voltage is also used by the CPC7582 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7582 enters the all-off state. 2.2 Switch Logic The CPC7582 provides, when switching from the ringing state to the talk state, the ability to control the release timing of the ringing switches SW3 and SW4 relative to the state of the break switches SW1 and SW2 using simple logic-level inputs. This is referred to as make-before-break or break-before-make operation. When the break switch contacts (SW1 and SW2) are closed (or made) before the ringing switch contacts (SW3 and SW4) are opened (or broken), this is referred to as make-before-break operation. Break-before-make operation occurs when the ringing contacts (SW3 and SW4) are opened (broken) before the break switch contacts (SW1 and SW2) are closed (made). With the CPC7582, the make-before-break and break-before-make operations can easily be selected by applying logic-level inputs to the device. The logic sequences for these modes of operation are given in “Make-Before-Break Operation for All Versions (Ringing to Talk Transition)” on page 13, “Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition)” on page 13, and “Break-Before-Make Operation for all Version (Ringing to Talk Transition)” on page 14. Logic states and input control settings are given in “CPC7582xA/B Truth R05 www.clare.com CPC7582 Table” on page 10 and “CPC7582xC Truth Table” on page 11. 2.2.1 Make-Before-Break Operation - All Versions To use make-before-break operation, change the logic inputs to the talk state immediately following the ringing state. Application of the talk state opens the ringing return switch (SW3) as the break switches (SW1 and SW2) close. The ringing switch (SW4) remains closed until the next zero-crossing of the ringing supply current. While in the make-before-break state, ringing potentials in excess of the CPC7582 protection circuitry trigger levels will be diverted to ground. 2.2.2 Make-Before-Break Operation for All Versions (Ringing to Talk Transition) Ringing Ringing Return Break Test Switch Switches Switch Switches (SW4) (SW3) Off On On Off State INRINGING 1 INTEST 0 LATCH TSD Timing Ringing SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of the ringing cycle. In this Floating transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. Zero-cross current has occurred Makebeforebreak 0 0 0 On Off On Off Talk 0 0 On Off Off Off 2.2.3 Break-Before-Make Operation - CPC7582xA/B Break-before-make operation of the CPC7582xA/B can be achieved using two different techniques. The first method uses manipulation of the INRINGING and INTEST logic inputs as shown in “Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition)” on page 13. 1. At the end of the ringing state apply the all off state (0, 0). This releases the ringing return switch (SW3) while the ringing switch remains on, waiting for the next zero current event. 2. Hold the all off state for at least one-half of a ringing cycle to assure that a zero crossing event occurs and that the ringing switch (SW4) has opened. Break-before-make operation occurs when the ringing switch opens before the break switches (SW1 and SW2) close. 2.2.4 Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition) Ringing Ringing Return Break Test Switch Switches Switch Switches (SW4) (SW3) Off Off On Off On On Off Off State INRINGING 1 1 INTEST 0 1 LATCH TSD Timing Ringing All-Off BreakBeforeMake Talk Hold this state for at least one-half of the ringing cycle. SW4 waiting for zero current to turn off. SW4 has opened Close Break Switches 0 1 0 1 0 Floating Off On Off Off Off Off Off Off 2.2.5 Break-Before-Make Operation - All Versions The second break-before-make method for the CPC7582xA/B is also the only method available for R05 the CPC7582xC. As shown in “CPC7582xA/B Truth Table” on page 10 and “CPC7582xC Truth Table” on page 11, the bidirectional TSD interface disables all of 13 www.clare.com CPC7582 the CPC7582 switches when pulled to a logic low. Although logically disabled, if the ringing switch (SW4) is active (closed), it will remain closed until the next current zero crossing event. As shown in the table “Break-Before-Make Operation for all Version (Ringing to Talk Transition)” on page 14, this operation is similar to the one shown in “Break-Before-Make Operation - All Versions” on page 13, except in the method used to select the all off state, and in when the INRINGING and INTEST inputs are reconfigured for the talk state. 1. Pull TSD to a logic low to end the ringing state. This opens the ringing return switch (SW3) and prevents any other switches from closing. 2. Keep TSD low for at least one-half the duration of the ringing cycle period to allow sufficient time for a zero crossing current event to occur and for the circuit to enter the break before make state. 3. During the TSD low period, set the INRINGING and INTEST inputs to the talk state (0, 0). 4. Release TSD, allowing the internal pull-up to activate the break switches. When using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces an all off state) and float (allows switch control via logic input pins and the thermal shutdown mechanism is active). This requires the use of an open-collector type buffer. Forcing TSD to a logic high disables the thermal shutdown circuit and is therefore not recommended as this could lead to device damage or destruction in the presence of excessive tip or ring potentials. 2.2.6 Break-Before-Make Operation for all Version (Ringing to Talk Transition) Ringing Ringing Return Break Test Switch Switches Switch Switches (SW4) (SW3) Off Off On Off On On Off Off State INRINGING 1 0 INTEST 0 0 LATCH TSD Floating Timing Ringing All-Off BreakBeforeMake Talk Hold this state for at least one-half of the ringing cycle. SW4 waiting for zero current to turn off. SW4 has opened 0 0 0 0 0 0 Off On Off Off Off Off Off Off Floating Close Break Switches 2.3 Data Latch The CPC7582 has an integrated data latch. The latch operation is controlled by logic-level input pin 11 (LATCH). The data input of the latch is pin 10 (INRINGING) and pin 9 (INTEST) of the device while the output of the data latch is an internal node used for state control. When LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in the switch state. When LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. The TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and the TSD input will override state control. 2.4 Thermal Shutdown Setting TSD to +5 V allows switch control using the logic inputs. This setting, however, also disables the thermal shutdown circuit and is therefore not recommended. When using logic controls via the input pins, pin 7 (TSD) should be allowed to float. As a result, the two recommended states when using pin 7 (TSD) as a control are 0, which forces the device to the all-off state, or float, which allows logic inputs to remain active. This requires the use of an open-collector type buffer. 2.5 Ringing Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The R05 14 www.clare.com CPC7582 switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See application note AN-144, Impulse Noise Benefits of Line Card Access Switches. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 Ω in series with the ringing generator is recommended. and faults are shunted to FGND via the SCR or the diode bridge. In order for the SCR to crowbar or foldback, the on voltage (see “Protection Circuitry Electrical Specifications” on page 10) of the SCR must be less negative than the VBAT voltage. If the VBAT voltage is less negative than the SCR on voltage or if the VBAT supply is unable to source the trigger current, the SCR will not crowbar. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to the diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the VBAT voltage by two to four volts, steering the current to ground. 2.8.2 Current Limiting function If a lightning strike transient occurs when the device is in the talk state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of the active switches during the talk state. During the talk state, when a 1000V 10x1000 μs pulse (GR-1089-CORE lightning) is applied to the line though a properly clamped external protector, the current seen at pins 2 (TBAT) and pin 15 (RBAT) will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 μs. If a power-cross fault occurs with the device in the talk state, the current is passed though break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to a power cross fault, the limited current measured at pin 3 (TLINE) and pin 14 (RLINE) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the all-off state. 2.6 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7582. CPC7582 switch state control is powered exclusively by the +5 V supply. As a result, the CPC7582BC exhibits extremely low power dissipation during both active and idle states. The battery voltage is not used for switch control but rather as a supply for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 2 (TBAT) or pin 15 (RBAT) drops 2 to 4 V below the voltage on pin 16 (VBAT). This trigger prevents a fault induced overvoltage event at the TBAT or RBAT nodes. 2.7 Battery Voltage Monitor The CPC7582 also uses the VBAT voltage to monitor battery voltage. If battery voltage is lost, the CPC7582 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the system battery voltage goes more positive than –10 V, and remains in the all-off state until the battery voltage goes more negative than –15 V. This battery monitor feature draws a small current from the battery (less than 1 μA typical) and will add slightly to the device’s overall power dissipation. 2.8 Protection 2.8.1 Diode Bridge/SCR The CPC7582 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via FGND. Voltage is clamped to a diode drop above ground. During a negative transient of 2 to 4 V more negative than the voltage at VBAT, the SCR conducts R05 2.9 Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110° C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 7 (TSD) will read 0 V. Normal output of TSD is +VDD. www.clare.com 15 CPC7582 If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to the all-off state. At this point the current measured at pin 3 (TLINE) and pin 14 (RLINE) through the break switches will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the deactivation level of the thermal shutdown circuit. This will permit the device to return to normal operation. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The thermal shutdown mechanism of the CPC7582 can be disabled by applying a logic high to pin 7 (TSD). 2.10 External Protection Elements The CPC7582 requires only overvoltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for protection on the line side. The secondary protector limits voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7582. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare’s application note, AN-100, “Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces” for equations related to the specifications of external secondary protectors, fused resistors and PTCs. 16 www.clare.com R05 CPC7582 3. Manufacturing Information 3.1 Mechanical Dimensions 3.1.1 16-Pin SOIC 10.211 ± 0.254 (0.402 ± 0.010) NOTES: 1. Coplanarity = 0.1016 (0.004) max. 2. Leadframe thickness does not include solder plating (1000 microinch maximum). PIN 16 10.312 ± 0.381 (0.406 ± 0.015) 7.493 ± 0.127 (0.295 ± 0.005) DIMENSIONS mm (inches) 1.270 TYP (0.050 TYP) 0.406 ± 0.076 (0.016 ± 0.003) 0.254 MIN / 0.737 MAX X 45° (0.010 MIN / 0.029 MAX X 45°) PIN 1 2.337 ± 0.051 (0.092 ± 0.002) 2.540 ± 0.152 (0.100 ± 0.006) 0.649 ± 0.102 (0.026 ± 0.004) 0.203 ± 0.102 (0.008 ± 0.004) 0.889 ± 0.178 (0.035 ± 0.007) 0.2311 MIN / 0.3175 MAX (0.0091 MIN / 0.0125 MAX) 3.1.2 16-Pin DFN 7.00 ± 0.25 (0.276 ± 0.01) 6.00 ± 0.25 (0.236 ± 0.01) INDEX AREA 0.90 ± 0.10 (0.035 ± 0.004) TOP VIEW 0.02, + 0.03, - 0.02 (0.0008, + 0.0012, - 0.0008) 1 SIDE VIEW 0.30 ± 0.05 (0.012 ± 0.002) SEATING PLANE 0.20 (0.008) EXPOSED METALLIC PAD 4.25 ± 0.05 (0.167 ± 0.002) Terminal Tip 0.80 (0.032) 16 6.00 ± 0.05 (0.236 ± 0.002) BOTTOM VIEW Dimensions mm (inch) 0.55 ± 0.10 (0.022 ± 0.004) R05 www.clare.com 17 CPC7582 3.2 Printed-Circuit Board Land Patterns 3.2.1 16-Pin SOIC 1.27 (0.050) 3.2.2 16-Pin DFN 0.35 (0.014) 9.40 (0.370) 2.00 (0.079) 1.05 (0.041) 5.80 (0.228) 0.60 (0.024) DIMENSIONS mm (inches) 0.80 (0.031) DIMENSIONS mm (inches) NOTE: Because the metallic pad on the bottom of the DFN package is connected to the substrate of the die, Clare recommends that no printed circuit board traces or vias be placed under this area to maintain minimum creepage and clearance values. 3.3 Tape and Reel Packaging 3.3.1 16-Pin SOIC Tape and Reel Packaging for 16-Pin SOIC Package 330.2 Dia (13.00 Dia) Top Cover Tape Thickness 0.102 Max (0.004 Max) Top Cover Tape P=12.00 (0.47) A0=10.90 + 0.15 (0.429 + 0.010) Dimensions mm (inches) Pin 1 B0=10.70 + 0.15 (0.421 + 0.01) W=16.00 + 0.30 (0.630 + 0.010) K0=3.20 + 0.15 (0.193 + 0.01) K1=2.70 + 0.15 (0.106 + 0.01) Embossed Carrier User Direction of Feed Embossment NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 18 www.clare.com R05 CPC7582 3.3.2 16-Pin DFN B0=7.24 + 0.10 (0.285 + 0.004) 330.2 Dia (13.00 Dia) Top Cover Tape Thickness 0.102 Max (0.004 Max) Pin 1 W=16.00 + 0.30 (0.630 + 0.012) Embossed Carrier K0=1.61 + 0.10 (0.063 + 0.004) P=12.00 + 0.10 (0.472 + 0.004) A0=6.24 + 0.10 (0.246 + 0.004) User Direction of Feed Embossment Dimensions mm (inches) NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 3.4 Soldering 3.4.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity for this product using IPC/JEDEC standard J-STD-020. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-033 per the labeled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 3 for the DFN package. 3.4.2 Reflow Profile For proper assembly, this component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy. 3.5 Washing Clare does not recommend ultrasonic cleaning of this part. Pb RoHS 2002/95/EC e3 For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specifications: DS-CPC7582-R05 © Copyright 2009, Clare, Inc. All rights reserved. Printed in USA. 10/14/09 R05 www.clare.com 19