FX919AP4

CML Semiconductor Products 4-Level FSK Modem Data Pump FX919A D/919A/4 June 1996 Advance Information 1.0 Features • 4-Level FSK Modulation • Half Duplex, 4800 to 19.2k bits/sec • Full Packet Data Framing • Flexible Operating Modes • Host Bus Interface • Low Power 3.3V to 5V Operation • 24-Pin Small Form Package Option 1.1 Brief Description The FX919A is a CMOS integrated circuit that contains all of the baseband signal processing and Medium Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data Modem. It interfaces with the modem host processor and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data over the wireless link. The FX919A assembles application data received from the processor, adds forward error correction (FEC) and error detection (CRC) information and interleaves the result for burst-error protection. After adding symbol and frame sync codewords, it converts the packet into filtered 4-level analogue signals for modulating the radio transmitter. In receive mode, the FX919A performs the reverse function using the analogue signals from the receiver discriminator. After error correction and removal of the packet overhead, the recovered application data is supplied to the processor. Any residual uncorrected errors in the data will be flagged. A readout of the SNR value during receipt of a packet is also provided. The FX919A uses data block sizes and FEC/CRC suitable for applications which require the high-speed transfer of data over narrow-band wireless links. The device is programmable to operate at most standard bitrates from a wide choice of Xtal/clock frequencies. © 1996 Consumer Microcircuits Limited 4-Level FSK Modem Data Pump FX919A CONTENTS Section Page 1.0 Features.......................................................................................................... 1 1.1 Brief Description............................................................................................ 1 1.2 Block Diagram................................................................................................ 3 1.3 Signal List....................................................................................................... 4 1.4 External Components.................................................................................... 6 1.5 General Description....................................................................................... 7 1.5.1 Description of Blocks ....................................................................... 7 1.5.2 Modem - µC Interaction ................................................................. 10 1.5.3 Binary to Symbol Translation......................................................... 11 1.5.4 Frame Structure ............................................................................ 12 1.5.5 The Programmer's View ................................................................ 13 1.5.5.1 Data Block Buffer ....................................................................... 13 1.5.5.2 Command Register .................................................................... 14 1.5.5.3 Control Register ......................................................................... 22 1.5.5.4 Mode Register............................................................................ 24 1.5.5.5 Status Register........................................................................... 25 1.5.5.6 Data Quality Register ................................................................. 27 1.5.6 CRC, FEC, and Interleaving .......................................................... 28 1.6 Application Notes ........................................................................................ 29 1.6.1 Transmit Frame Examples ............................................................ 29 1.6.2 Receive Frame Examples ............................................................. 32 1.6.3 Clock Extraction & Level Measurement Systems.......................... 35 1.6.4 AC Coupling .................................................................................. 36 1.6.5 Radio Performance........................................................................ 38 1.7 Performance Specification ......................................................................... 39 1.7.1 Electrical Performance .................................................................. 39 1.7.2 Packaging...................................................................................... 43 Note: As this product is still in development, it is likely that a number of changes and additions will be made to this specification. Items marked TBD or left blank will be included in later issues. © 1996 Consumer Microcircuits Limited 2 D/919A/4 4-Level FSK Modem Data Pump FX919A 1.2 Block Diagram Figure 1 Block Diagram © 1996 Consumer Microcircuits Limited 3 D/919A/4 4-Level FSK Modem Data Pump FX919A 1.3 Signal List Package P4/D2/D5 Pin No. 1 Name IRQN Signal Type O/P A 'wire-ORable' output for connection to the host µC's Interrupt Request input. This output has a low impedance pull down to VSS when active and is high impedance when inactive. ) ) ) ) ) ) ) ) Description 2 3 4 5 6 7 8 9 10 D7 D6 D5 D4 D3 D2 D1 D0 RDN BI BI BI BI BI BI BI BI I/P 8-bit bidirectional 3-state µC interface data lines. Read. An active low logic level input used to control the reading of data from the modem into the host µC. Write. An active low logic level input used to control the writing of data into the modem from the host µC. The negative supply rail (ground). Chip Select. An active low logic level input to the modem, used to enable a data read or write operation. ) ) Two logic level modem register select inputs. 11 WRN I/P 12 13 Vss CSN Power I/P 14 15 16 17 A0 A1 XTALN XTAL/CLOCK I/P I/P O/P I/P The output of the on-chip oscillator. The input to the on-chip oscillator, for external Xtal circuit or clock. ) ) ) Connections to the Rx level measurement circuitry. A capacitor should be connected from each pin to VSS. 18 19 DOC 2 DOC 1 O/P O/P © 1996 Consumer Microcircuits Limited 4 D/919A/4 4-Level FSK Modem Data Pump FX919A Package P4/D2/D5 Pin No. 20 21 Name TXOP VBIAS Signal Description Type O/P O/P The Tx signal output from the modem. A bias line for the internal circuitry, held at ½ VDD. This pin must be decoupled to VSS by a capacitor mounted close to the device pins. The input to the Rx input amplifier. The output of the Rx input amplifier and the input to the Rx RRC filter. The positive supply rail. Levels and voltages are dependent upon this supply. This pin should be decoupled to VSS by a capacitor. 22 23 RXIN RXFB I/P O/P 24 VDD Power Notes: I/P = O/P = BI = Input Output Bidirectional Internal protection diodes are connected from each signal pin to VDD and VSS. © 1996 Consumer Microcircuits Limited 5 D/919A/4 4-Level FSK Modem Data Pump FX919A 1.4 External Components Figure 2 Recommended External Components R1 R2 R3 R4 X1 See Section 1.5.1 100k ohm ± 5% 1M ohm ± 20% 100k ohm ± 5% See Section 1.5.5.3 C1 C2 C3 C4 0.1 µF ± 20% 0.1 µF ± 20% ± 20%, see Note 1 ± 20%, see Note 1 C5 C6 C7 C8 ± 5%, see Note 3 ± 20%, see Note 2 ± 20%, see Note 2 ± 5%, see Note 3 Note 1: The values used for C3 and C4 should be suitable for the frequency of the crystal X1. As a guide, values (including stray capacitances) of 33pF at 1MHz falling to 18pF at 10MHz will generally prove suitable. The 'Phase-Locked Loop Modes' part of section 1.5.5.3 discusses crystal frequency tolerances. Note 2: C6 and C7 values (in nano Farads) should be equal to 50000 ÷ symbol rate, e.g. Symbol Rate 2400 symbols/second 4800 symbols/second 9600 symbols/second C6/C7 (nF) 22.0 10.0 4.7 Note 3: C5 and C8 values (in pico Farads) should be equal to 750000 ÷ symbol rate, e.g. Symbol Rate 2400 symbols/second 4800 symbols/second 9600 symbols/second C5/C8 (pF) 330 150 82 © 1996 Consumer Microcircuits Limited 6 D/919A/4 4-Level FSK Modem Data Pump FX919A 1.5 1.5.1 General Description Description of Blocks Data Bus Buffers Eight bidirectional 3-state logic level buffers between the modem's internal registers and the host µC's data bus lines. Address and R/W Decode This block controls the transfer of data bytes between the µC and the modem's internal registers, according to the state of the Write and Read Enable inputs (WRN and RDN), the Chip Select input (CSN) and the Register Address inputs A0 and A1. The Data Bus Buffers, Address and R/W Decode blocks provide a byte-wide parallel µC interface, which can be memory-mapped, as shown in Figure 3. Figure 3 Typical Modem µC Connections Status and Data Quality Registers Eight-bit registers which the µC can read to determine the status of the modem and the received data quality. Command, Mode and Control Registers The values written by the µC to these 8-bit registers control the operation of the modem. Data Buffer A 12-byte buffer used to hold receive or transmit data to or from the µC. CRC Generator/Checker A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum bits, which may be included in transmitted data blocks so that the receive modem can detect transmission errors. © 1996 Consumer Microcircuits Limited 7 D/919A/4 4-Level FSK Modem Data Pump FX919A FEC Generator/Checker In transmit mode, this circuit adds Forward Error Correction bits to the transmitted data, then converts the resulting binary data to 4-level symbols. In receive mode, it translates received 4-level symbols to binary data, using the FEC information to correct a large proportion of transmission errors. Interleave/De-interleave Buffer This circuit interleaves data symbols within a block before transmission and de-interleaves the received data so that the FEC system is best able to handle short noise bursts or fades. Frame Sync Detect This circuit, which is only active in receive mode, is used to look for the 24-symbol Frame Synchronisation pattern which is transmitted to mark the start of every frame. Rx I/P Amp This amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the external components R1 and R2. The value of R1 should be calculated to give 0.2 x VDD pk-pk at the RXFB pin for a received '...+3 +3 -3 -3 ...' sequence. A capacitor may be fitted in series with R1 if ac coupling of the received signal is desired (see Section 1.6.4), otherwise the dc level of the received signal should be adjusted so that the signal at the modem's RXFB pin is centred around VBIAS (½ VDD). RRC Low Pass Filter This filter, which is used in both transmit and receive modes, is a linear-phase lowpass filter with a 'Root Raised Cosine' frequency response defined by: H(f) =1 = square root of {0.5 [1 - sin(π T (f - 0.5/T)/b)]} =0 where b = 0.2, T = 1/symbol rate for for for 0 (1-b)/(2T)